JPH0353658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory control device, and particularly to a memory control device for transferring cache memory data to a main memory device in an information processing system equipped with a set associative type and store swap type cache memory. The present invention relates to a memory control device related to an output means.

(Prior Art) In large-scale information processing systems, the processing speed of the memory element for the main memory device has not been improved relative to the improvement in the processing speed of the arithmetic and control unit. In order to absorb the difference in processing speed between the two, there is a system in which a store-swap type cache memory is installed in the memory control device to shorten the average memory access time and improve the load on the main memory device. In systems that have only store-through type cache memory, the latest memory data always exists in the main memory device during operation, but in systems like the one described above that have store-swap type cache memory, depending on the memory data, the latest memory data always exists in the main memory device. Memory data does not necessarily reside on the main memory device, but may reside only on cache memory. Such non-currentness of main memory device data poses a major hindrance to dynamic changes in logical connections between devices in the system configuration. 1 to 3 show examples of connections between devices. Memory control device 1
01, 102 are main memory devices 201, 202, 2
03, 204, and further connected to arithmetic control units 301, 302, and input/output control units 401,
402. A solid line between devices indicates a state in which they are logically and physically connected, and a broken line indicates a state in which they are physically connected but logically disconnected. All the devices shown in FIG. 1 are logically connected and operated as a so-called multiprocessor. The system shown in FIG. 2 is divided into two parts, and both are operated independently as a duplex system. Further, the memory control device 102 shown in FIG. 3 is in a disconnected state due to a failure or the like. It is desirable that state changes between these system configurations be performed without affecting users who are using the system. Especially when the system is used online, it must be avoided to affect end users.

In a system having store-swap type cache memory in the memory control units 101 and 102, only one memory control unit is logically connected to one main memory unit, as shown in FIGS. 1 to 3. Generally, the configuration is such that only As a result, even if the main memory device data is registered in the cache memory in the memory control device to which this main memory device is logically connected, it will be registered in the cache memory in the memory control device to which the main memory device is logically unconnected. Therefore, the data between the cache memories becomes exclusive, and there is no need to control data interference between the two.

In such a configuration, for example, when transitioning from the system configuration shown in FIG. 3 to the system configuration shown in FIG. Because the main memory device 20 exists in the cache memory within the main memory device 20, it is not possible to simply switch the logical connection relationship after system configuration migration.
Memory access to 3,204 cannot be performed normally.

The following method can be used to transition from the system configuration shown in FIG. 3 to the system configuration shown in FIG. 1 without inconsistency in the latestness of memory data.

The first method is to stop the system once, change the logical connections between devices, and then restart the system starting with system initialization (main memory data continuity is not required).
In this case, a lot of time is required from the time the system is stopped until the restart is completed, which has a large impact on the users who are using the system.

The second method is to suspend the processing of the arithmetic control units 301 and 302 at the command break, and also to prevent the start of new input/output operations. Exports the cache memory data to the main memory device. Upon completion of this writing, the data in the main memory devices 203 and 204 becomes the latest state. Thereafter, the logical connection relationship between the devices is changed and processing is restarted while maintaining the continuity of the main memory data. Although this method does not affect the user as much as the first method, it still has a large impact on the user because it requires a considerable amount of time to wait for the input/output operation currently being executed to stop.

The third method is to stop and suspend the processing of the arithmetic control units 301 and 302 at the command break, and to inhibit and suspend the memory access processing in the memory control unit 101 as the input/output processing is currently being processed. When memory access is inhibited, the memory control device 101
The internal cache memory data is flushed out to the main memory device, and when the flushing is completed, the logical connection relationship between the devices is changed, and processing is restarted while maintaining the continuity of the main memory data. With this method, system stoppage from the user's perspective is not a big problem during the time it takes for the cache memory data to be flushed to the main memory device. There is a risk that the frequent occurrence of overruns and data overruns will not be able to be brought under control.

If the arithmetic control unit for the cache memory can process the memory access from the input/output device normally while writing out the cache memory data to the main memory unit, there is no need to use the above method. However, when there is a memory access to the cache memory data that has already been written to the main memory device, problems occur in the processing. The same process as described above can be applied to transition between the system configuration shown in FIG. 1 and the system configuration shown in FIG.

As mentioned above, conventional systems like this
This system has drawbacks such as the lack of effective means for changing the system configuration.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of conventional memory control devices, and to eliminate the last memory By allowing memory access by input/output processing to the unextracted cache memory data until starting the row extrusion process, and by limiting new block allocation to only unextracted rows when a cache memory miss occurs. The objective is to shorten the memory access inhibition time due to input/output processing and improve dynamic changes in system configuration.

(Structure of the Invention) According to the present invention, a plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a memory access request from the arithmetic control devices and the input/output control device to the main memory device. information including a plurality of memory control devices interposed between the memory control devices, each memory control device having a set associative type and store swap type cache memory shared by each of the arithmetic control units and input/output control devices. In the processing system, a circuit for specifying a line in the cache memory and prohibiting new block registration to that line; and a circuit for specifying a line in the cache memory and transferring the data in that line to the corresponding main memory device. There is obtained a memory control device characterized in that it includes an output circuit and a circuit for inhibiting memory access from the input/output control device to the memory control device.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 4 shows an embodiment of the present invention. In FIG. 4, one embodiment of the present invention is connected to an arithmetic control device 301 and an input/output control device 401, and further connected to a main memory device 201, and is connected to an arithmetic control device 301 and an input/output control device 401. In a memory control device 101 having a shared set associative type or store swap type cache memory, a circuit 119 for specifying a line in the cache memory and prohibiting new block registration to that line; It includes a write control circuit 123 that writes data to the cache memory device 201, and a circuit 124 that inhibits memory access from the input/output control device 401 to the memory control device 101.

Furthermore, this memory control device 101 includes request reception port circuits 111 and 126 connected to the input/output control device 401, and request reception port circuits 110 and 1 connected to the arithmetic control device 301.
27, an output column address counter 122 connected to the output control circuit 123, and the request reception port circuits 110, 111, 126, 1
27 and the stage 1 request register 112 connected to the exposed column address counter 122.
and a stage 2 request register 113 connected to the stage 1 request register 112.
and a stage 3 request register 11 connected to the stage 2 request register 113 and whose output is further connected to the main memory device 201.
4.

The stage 1 request register 112 is connected to the write data register 115, the address array 130, and the address comparison circuit 121, and is further connected to the row designation new allocation prohibition bit 119, the write control circuit 123, and the input/output control device request reception inhibition bit 124. It is connected. The row designation new allocation prohibition bit 119 is connected to the replacement circuit 132. Extrusion control circuit 1
23 is connected to the arithmetic and control unit, and the input/output control unit request reception inhibiting bit 124 is connected to the input/output control unit 401.

Write data register 115 is connected to read data selection circuit 125 and cache memory 131. Address array 130 is connected to address array data selection circuit 117 via address array register 116.

The stage 2 request register 113 has a cache memory 131 and a replacement circuit 13.
It is connected to 2.

Stage 3 request register 14 is connected to main memory request buffer 120 and stage 1 request register 112. Furthermore, main memory request buffer 120 is connected to cache memory 131 and write data register 115. The cache memory 131 is connected to the read data selection circuit 125 via the read data register 118.
and is connected to the main memory device 201. The read data selection circuit 125 is the write data register 115
and read data register 118, and supply the selected data to arithmetic control device 301 and input/output control device 401.

Next, memory control device 1 for normal memory access
An example of the operation in 01 will be explained. When a memory access is made to the memory control device 101 from the arithmetic control device 301 or the input/output control device 401, request information such as an operation designation code, address, and store data is received by the request reception port circuit 110 or 111. Next, one piece of request information is selected from the request reception port circuit and the stage 1 request register 11
Sent to 2. Stage 1 request register 1
At step 12, the operation designation code is decoded, and the following operations are performed in accordance with the operation designation.

When the operation designation is a read request, the address array 130 is first indexed to check whether the required data exists on the cache memory. When a cache memory hit exists (referred to as a cache memory hit), the corresponding data is read from the cache memory 131 to the successive data register 118 and sent to the requesting device. Also, the referenced cache memory block is reflected from the stage 2 request register 113 to the replacement circuit 132.

If the operation designation is a write request and the corresponding data exists on the cache memory as a result of address array 130 indexing, writing to the corresponding data in cache memory 131 from write data register 115 is performed. Main memory device 20
Writing to 1 is not performed at this time.

At this time, the information is reflected to the replacement circuit 132 in the same way as when reading. By the way, in address array 130, modification bits are provided corresponding to cache memory blocks. When this modification bit is on, it indicates that the latest data of the corresponding block is not present in the main memory device 201 but only in the cache memory 131. Qualifier bits must be turned on when a write is performed. When the corresponding data exists in the cache memory due to a write request, the data in the address array 130 is transferred to the address array register 11.
6 and examines the value of the modification bit. When this modification bit is off, the write request information is stored in stage 3 request register 114.
Stage 1 request register 112 via
The data is returned to address array 130, and a registration operation is performed in address array 130 to turn on the modification bit of the corresponding block in address array 130.

When a read request or a write request is performed and the required data does not exist in the cache memory as a result of address array 130 indexing (referred to as a cache memory miss), the following operations are performed. The stage 2 request register is accessed by the replacement circuit 132 to determine the row number of the block to be newly allocated.

Based on this number, the address array data selection circuit 117 selects the address array data of the block to be replaced from the address array register 116 in which the data read from the address array 130 is stored, and selects it as part of the data in the stage 3 request register 114. Become. The information in the stage 2 request register 113 is also stage 3
It is sent to the request register 114.

A block transfer request is issued from the stage 3 request register 114 to the main memory device 201.
Further, request information being requested to the main memory device is stored in the main memory request buffer 120. The types of this request information include the column address and row address of the cache memory where the block transfer data is to be written, and store data when the request from the request source is a write request.

The contents of stage 3 request register 114 are returned to stage 1 request register, and new allocation block information is registered in address array 130. When the request from the request source is a write request, the modification bit is turned on at the same time. When the modification bit of the block in the replaced address array is on, the latest data of the block to be replaced does not exist in the main memory device 201 and is stored in the cache memory 13.
Since it only exists in one corresponding block, it is necessary to return this data to the main memory device. At this time, the request information in the stage 1 request register 112 including the address of the replaced block is transferred to the stage 2 request register 113.
Further, a block write request is made to the main memory device 201 using the address of the replaced block from the stage 3 request register 114. At this time, the data to be written to the main memory device 201 is sent from the cache memory 131 via the read data register 118. When the request from the request source is a read request, when the block transfer data is read from the main memory device 201, the data is stored in the write data register 115. At this time, the row address and column address of the cache memory to which the data is to be written are taken out from the main memory request buffer 120, and the data in the write data register 115 is written into the cache memory 131. Further, the data is sent to the request source via the read data selection circuit 125. When the request from the request source is a write request, when block transfer data is sent from the main memory device 201, store data is extracted from the main memory request buffer 120, merged with the block transfer data, and written. The data is placed in the data register 115.

In the above request processing, since a plurality of requests are processed in a pipeline manner, address interference occurs between request processings, but an address comparison circuit 121 is provided to avoid this. The address comparison circuit 121 stores the address currently being processed, and compares this address with the address that has newly entered the stage 1 request register 112. If they match, the request processing of the stage 1 request register 112 is inhibited. Ru.

Next, a description will be given of how cache memory data is written to the main memory device during dynamic change according to one embodiment of the present invention.

In this embodiment, the following individual operation functions are provided in the memory control device, and each function is realized by microinstruction control of an arithmetic control device or the like.

The first function is the line specification new allocation prohibition bit 11.
It is 9. This prohibition bit is provided for each row of the cache memory and can be set or canceled upon request from the request source. When this prohibition bit is set, the corresponding line is prohibited from being replaced in the event of a cache memory miss. However, when a cache memory hit occurs, read/write access to the corresponding row is permitted. In many devices, cache memory is generally equipped with row-based degrade bits for the purpose of detaching faulty cache memory row by row, but it is possible to prevent rows corresponding to these degrade bits from being replaced. and cache memory hit inhibition, whereas the row-specified new allocation prohibition bit performs only the former operation.

The second function is to output cache memory data line by line to the main memory device. This row-by-row printing operation is instructed by a request from a request source, and is controlled by a printing control circuit 123 and a printing column address counter 122. When a row printout request is received from a request source, the printout control circuit 123 is activated and the printout column address counter 122 is initialized. When the stage 1 request register 112 receives a print request with the column address of the print column address counter 122 and the row address specified by the request source as a print request, the designated row and column of the address array 130 are indexed. If the index results in a valid bit-off or a qualified bit-off for that block, processing ends there. The operation when the valid bit is on and the modification bit is on is that block transfer processing is not performed in response to the cache memory miss of the normal memory access request mentioned above, and the valid bit of the corresponding block of address address 130 is turned off. The same operation is performed except for this point. This causes the latest data that is only on the cache memory to be flushed out to the main memory device.

The third function is the installation of an input/output control device request reception suppression bit 124. This inhibition bit can be set or canceled by a request from the requesting device. The value of this bit is sent to all input/output control devices, and when set, the input/output control device inhibits memory access to the memory control device 101. Since the request reception inhibition signal from the memory control device 101 to each requesting device already exists for the purpose of conveying that the request reception port circuits 110, 111, etc. are busy, the content of the input/output control device request reception inhibition bit is based on that signal. It is possible to share it with

Next, the arithmetic and control unit 30 combines the above functions to dynamically change the system configuration from FIG. 3 to the system configuration shown in FIG.
An example of the operation procedure when 1 is executed is shown below.

Setting the new allocation prohibition bit for cache memory row N (assuming that the cache memory is composed of rows 0 to N) of the memory control device 101.

Instructs to write out the cache memory row N of the memory control device 101.

After completing row N, set the new allocation prohibition bit for N-1.

An instruction to write out the cache memory row N-1 of the memory control device 101.

The following operations are repeated until the end of row 1.

Set the input/output control device request reception suppression bit 124 of the memory control device 101.

Instructs to write out row 0 of the cache memory of the memory control device 101.

After writing out line 0, change the logical connection status between devices as shown in Figure 1.

Clearing the new allocation prohibition bit from row N to row 1 of the memory control device 101, and canceling the input/output control device request reception inhibition bit.

The main memory device 2 that is logically connected to the memory control device 102 after the system configuration is changed by the above procedure.
03,204 data can be updated to the latest state. In FIG. 3 of the above procedure, the arithmetic and control unit 3
If 02 is also logically connected to the memory control device 101, the arithmetic control device 301 sends a processing suppression request to the arithmetic control device 302 through the inter-device communication means before the procedure, and the memory control from the arithmetic control device 302 is performed. Stop memory access to device 101. Further, when a part of the row of the cache memory in the memory control device 101 is disconnected due to a failure state or the like, that row must be excluded from the target of extraction in the above procedure. In the above procedure, the process that requires the most processing time is the process of writing out the cache memory data to the main memory device, but as explained above (effects of the invention), the present invention Compared to the case where all memory accesses of the input/output control device are inhibited while memory data is being written out, this inhibition time can be reduced to 1/the number of lines in the cache memory. The risk of input/output processing overrun can be reduced.

[Brief explanation of drawings]

1, 2, and 3 are diagrams showing various system configurations in a memory control device, and FIG. 4 is a block diagram showing an embodiment of the present invention. 101, 102... memory control device, 110,
111, 126, 127...Request reception port circuit, 112...Stage 1 request register, 113...Stage 2 request register,
114...Stage 3 request register, 11
5...Write data register, 116...Address array register, 117...Address array data selection circuit, 118...Read data register, 1
19...Line specification new allocation prohibition bit, 120...
Main memory request buffer, 121...Address comparison circuit, 122...Extrusion column address counter, 123...Extrusion control circuit, 124...
Input/output control device request reception suppression bit, 12
5...Read data selection circuit, 130...Address array, 131...Cache memory, 132...
...Replacement circuit, 201, 202, 20
3,204...Main memory device, 301,302...
... Arithmetic control device, 401, 402 ... Input/output control device.

Claims (1)

[Claims] 1 includes a plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a plurality of memory control devices that mediate memory access requests from the arithmetic control devices and the input/output control devices to the main memory device. In an information processing system, each of the memory control devices includes a cache memory of a set associative type and a store swap type, which is shared by each of the arithmetic control units and input/output control units. a circuit that specifies a line in the cache memory and prohibits new block registration in that line; a circuit that specifies a line in the cache memory and writes data in that line to the corresponding main memory device; 1. A memory control device comprising: a circuit for inhibiting memory access to the memory control device.