JPS6147667A - Method of controlling self-arc-extinguishing semiconductor element - Google Patents

Abstract

PURPOSE:To obtain an effect equivalent to the effect obtained by utilizing a gate driving circuit in which both gates are provided with a gate controlling power supply, by providing a capacitor between one gate and the main electrode connected with a gate controlling power supply for the other gate. CONSTITUTION:When a switch 16 is opened and a switch 17 is closed, by P<+>- N<->-N<+> junction between a gate 14 and a cathode 1 is biased reversely. Under this condition, holes and electrons are swept away from a gate electrode 8 and a cathode electrode 6, respectively, as the reverse current of the gate 4. When a channel 5 is thereby depleted completely, the current is inhibited from flowing from an anode 2 to the cathode 1 and the cathode current becomes zero. As a result, the anode current flows through an N type buffer layer 10, going out from a second gate 20, flowing via a capacitor 9, and stops, applying an overvoltage to the capacitor 9. At the next moment, the reverse recovery current flows, whereby electrons and holes are swept away from a second gate electrode 20 and an anode electrode 7, respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for controlling a self-extinguishing semiconductor device, particularly a buried gate type electrostatic induction thyristor having two types of gates of mutually opposite conductivity types. It is.

[Conventional technology]

The electrostatic induction thyristor (hereinafter referred to as 8I thyristor) is
This thyristor was invented in recent years as a thyristor capable of high power and high-speed switching, and its gate portion differs in shape from conventional thyristors with a four-layer structure.

There are two types of 8I silices known, depending on the gate structure: a surface gate type and a buried gate type. Also,
Depending on the number of gates, they can be classified into single gate type and digital gate type.

Dual gate type 8I thyristors are particularly attracting attention as elements capable of high breakdown voltage and high speed operation.

The present applicant had previously developed an SI thyristor (hereinafter referred to as 2nd
8I thyristor with gate) patent application filed in 1984-104
No. 132 "Self-extinguishing semiconductor device" is currently being filed.

The known dual day 1-8I thyristor and the pending M2 gated 8-thyristor are both characterized by having a gate for controlling the main current not only in the cathode region but also in the anode region. Regarding the control method, a special method is required, which is different from that of the conventional single gate type SI thyristor. Hereinafter, using the pending 8I thyristor with a second gate as an example, an SI with two types of gates will be described.
The driving method and operation of the thyristor will be explained.

FIG. 4 is a schematic diagram showing the cross-sectional structure of a unit element of a second gated SI thyristor, and an actual 8I thyristor pellet has a structure in which a large number of these unit elements are connected in parallel.

The present unit device includes a buffer layer 10 having an intermediate resistance between the two layers of the anode 2 and the base region 3, and a part of the buffer layer 10 is exposed on the same surface as the surface of the anode 2. A second gate electrode 20 is provided on this exposed surface. The structure of other parts is conventional buried gate type S.
It is similar to the I thyristor, and has a shape surrounding the N layer called channel 5 in the part of the base region 3 near the cathode 1, and P
The structure includes a gate 4 consisting of two layers of low resistance regions in the shape of a cathode 1. Anode 2. A cathode electrode 6 is provided on the surface of the gate 4, respectively. An anode electrode 7° and a gate electrode 8 are provided.

Next, a conventional method for operating an 8I thyristor having such a structure will be described.

Fig. 5 is a circuit diagram for explaining the operation when opening and closing a DC circuit using the 8I thyristor with the second gate shown in Fig. 4, and is constructed by connecting a large number of unit elements shown in Fig. 4 in parallel. A main circuit is formed by the thyristor 11, a main power source 13, and a load 12, and a power source 14 with the positive electrode on the gate electrode 8 side is connected via a switch 16 between the cathode electrode 6 of the 8I thyristor 11 and the gate electrode pot, and a switch. A power supply 15 with the negative electrode on the gate electrode 8 side is connected in parallel via the switch 17, and the positive electrode is connected between the anode electrode 7 and the second gate electrode 20 of the 8I thyristor 11 with the anode electrode 7 side via the switch 16'. A control circuit is formed by connecting in parallel the power supply 14' and the power supply 15' whose negative electrode is on the anode electrode 7 side via a switch 17'.

To turn on the 8I thyristor 11, switch 17.
17' is opened and switches 16 and 16' are closed simultaneously.

At this time, the P+N-N" junction between the gate 4 and the cathode 1 and the PI'N junction between the anode 2 and the second gate electrode 20 are both forward biased, and the anode 2 is connected to the base region 3 of the central N"" layer. Holes are injected from the cathode 1, and electrons are injected from the cathode 1.

The carriers injected into the N-layer base region 3 are accelerated by the electric field of the main electrode 13, and electrons flow to the anode 2 and holes flow to the cathode 1, so that the SI thyristor 11 is rapidly turned on.

Next, for the 8I thyristor 11 in this state, switches 16 and 16' are opened and switches 17 .
17' at the same time, a P''N junction between the second gate electrode 20 and the anode 2 and an N junction between the cathode 1 and the gate 4 are formed.
+N−]” junctions are both reverse biased.

At this time, a depletion layer is formed in the channel 5 and its vicinity, and spreads to the base region 3 made of a single N layer.

Furthermore, since the P+N junction on the anode 2 side is reverse biased, electrons in the N layer of the buffer layer 10 are directed to the outside by the second gate electrode 20, and holes are transferred to the second gate electrode 2 of the anode 2.
The P+N junction reversely recovers and the base region 3
Injection of holes into the N layer immediately stops.

Most of the carriers existing in the base region 3 made of a single N layer in a conductive state are swept out through the gate 4 as the depletion layer in the channel 5 expands, so that after the depletion layer has sufficiently bottomed out and blocked the circuit voltage. The current flowing is only a current for sweeping out a few holes remaining on the anode 2 side of the N'''' layer of the base region 3 to the gate 4. That is, the effect of reducing the Tirumi flow is large.

During the period when the Tilmi current flows during turn-off, the anode voltage is generally restored to the circuit voltage, so if the Tilmi current is large, a large power loss occurs in the device. Therefore, in high-voltage, large-current devices, reduction of the Tilmi current has been a conventional problem, but this problem has been solved by the algate type 8I thyristor.

Another challenge when switching current using an 8I thyristor is handling the spike voltage that occurs between the anode and cathode of the 8I thyristor during turn-off due to the inductance of the circuit. Usually, a snubber circuit is connected between the anode and cathode of the 8I thyristor to prevent spike voltage from occurring.

Next, the operation of the snubber circuit will be explained. FIG. 6 is a connection diagram for explaining a configuration example of a snubber circuit, in which the same reference numerals as in FIG. A snubber diode, 23 a snubber capacitor, and 24 a snubber resistor.

In FIG. 6, off-gate currents are applied from the gate drive circuits 18 and 19 to the gate electrode 8 and second gate electrode 20 of the 8I thyristor, which is currently conducting, to turn off the 8I thyristor 11. At this time, the anode current of the 8I thyristor quickly becomes 0, and the circuit current is
→ Load 12 → Inductance 21 → Diode 22 → Capacitor 23 → Power supply 13.
to charge.

At this time, the voltage between the anode and cathode of the 8I thyristor 11 becomes the same as the voltage of the capacitor 23, so generation of a high spike voltage can be prevented. Due to the energy stored in the circuit's inductance 21, the voltage on the capacitor 23 will generally be higher than the voltage on the mains 13. When the 81 thyristor 11 is turned on, the charge stored in the capacitor 23 is discharged through the resistor 24 in preparation for the next turn off.

[Problem that the invention seeks to solve]

When a snubber circuit is actually configured as explained above, a reverse voltage equal to the circuit voltage is applied to the snubber diode 22 shown in FIG. This selection is a difficult problem because not only high voltage resistance is required, but also high-speed switching performance is required.

In addition, as explained earlier, the method of providing a second gate near the anode of the SI thyristor and sending a gate signal to control switching has a great effect on improving switching performance, but on the other hand, it requires complicated Two sets of functional gate drive circuits must be provided, and in particular, in the gate drive circuit that drives the second gate on the anode side, the anode potential changes at high frequency as the element switches lζ.
It was extremely difficult to construct circuits using high-voltage, large-current power elements.

[Purpose of the invention]

The present invention was made for the purpose of solving such problems,
A simple and practical method for driving a 1g2 gate of a dual-gate 8I thyristor and configuring a snubber circuit is provided.

[Summary of the invention]

When driving the gate of a self-extinguishing semiconductor, for example, a dual gate type 8I thyristor, which has two gates of opposite conductivity type, the present invention provides a method for connecting one gate and a main electrode of opposite conductivity type to the gate. A self-extinguishing device characterized in that a gate control power source is connected between the gate and the gate control power source through a switch, and a capacitor is connected between the other gate and the main electrode to which the gate control power source of the one gate is connected. This is a method for controlling shaped semiconductor devices.

For example, in a second gated SI thyristor, when turning off, the anode 2, which is the second emitter region,
The capacitor is charged by the main current flowing through the semiconductor junction between the gate region and the second gate region formed by the buffer lO to which the second gate electrode 20 is attached, and the first gate region of the self-extinguishing semiconductor element is charged. In addition to suppressing the rate of increase in voltage between the main electrode and the second main electrode and the occurrence of overvoltage, the capacitor is overcharged by the energy stored during energization in the inductance of the main circuit, and the second emitter is Embodiments of the Invention FIG. 1 shows a method of controlling a self-turn-off type semiconductor device according to the present invention. This is a circuit diagram illustrating one embodiment, taking an 8I thyristor with a second gate as an example of a self-extinguishing semiconductor element,
The same reference numerals as in FIG. 5 indicate parts having the same function, and 9
is a capacitor.

In FIG. 1, when switch 17 is opened and switch 16 is closed, the P+N-N" junction between gate 4 and cathode 1 is forward biased, and electrons from the N+ region of cathode 1 are transferred from the r layer of gate 4. Holes are injected as carriers into the N'''' layer in the channel 5, and the carrier density in the channel 5 increases significantly, resulting in a highly conductive state.

At this time, some of the electrons injected into the channel 5 from the N+ region of the cathode 1 are accelerated by the electric field of the main power source 13, move through the N'''' layer of the base region 3 with a low impurity concentration, and move through the N'''' layer of the base region 3 with a low impurity concentration, and are transferred to the anode 1. It is accumulated in the N first layer portion of the base region 3 immediately below the second layer. The electrons accumulated in this part promote the injection of holes from the anode 2 to the base region 3, and the holes injected into the base region 3 pass through the channel 5 and reach the cathode 1, and further injection of electrons. In this way, the base region 3 made of the N'''' layer with a low impurity concentration is filled with carriers at a high concentration and exhibits low resistance. This process is the turn-on of the 8I thyristor, and in the on steady state, the base region 3 of the 8I thyristor
The channel 5 is filled with electrons and holes, and the holes are accumulated in the two-layer gate 4.

Next, the operation when turning off the 8I thyristor 11 in such a state will be described.

In FIG. 1, when the switch 16 is opened and the switch 17 is closed, the P+N-N" junction between the gate 4 and the cathode 1 is reverse biased. At this time, the gate 4 consisting of two layers and the base region near the gate 4 The holes stacked in 3 N'''' layers are connected from the gate electrode 8 to the cathode 1 consisting of one layer.
Electrons in the N layer in the base region 3 near the cathode 1' are swept out from the cathode electrode 6 as a reverse current of the gate 4.

As a result, a depletion layer is formed in the N'''' layer of the base region 3 near the gate 4, and as the depletion layer grows, the channel 5 is completely depleted.
It will spread towards.

When the channel 5 is completely depleted, the flow of current from the anode 2 toward the cathode 1 will be blocked by the channel 5, and the cathode current will be zero.

As a result, the anode current flows through the N-type buffer layer 10, flows out from the second gate 20, and flows through the capacitor 9 connected between the second gate electrode 20 and the cathode electrode 6. As the voltage of capacitor 9 increases, base region 3
The depletion layer also grows toward the anode 2. Due to the energy stored in the inductance 211 during energization, even if the voltage of the capacitor 9 becomes equal to the voltage value of the power supply 13, the anode current does not immediately become O, and the capacitor 9
becomes overvoltage and shuts down.

At this time, there are many excess carriers remaining in the buffer layer 10 directly under P+# of the anode 2 without being swept out from the gate 4, but when the anode current stops, the capacitor 9 is overcharged. Therefore, in the next instant, a reverse recovery current flows through the P''N diode consisting of the buffer layer lO and the emitter layer of the anode 2, and the electrons existing in the N type buffer layer lO are transferred from the second gate electrode 20, and the holes are transferred to the anode electrode. 7. As a result, P+ of anode 2
The area around the N junction is also rapidly depleted.

By appropriately selecting the capacitance of the capacitor 9, the second gate described above can have the same effect as when the second gate drive circuit described above is used as far as the off-state is concerned. Further, regarding the function of absorbing the spike voltage generated between the anode 2 and cathode 1 of the SI thyristor 11 at the time of turn-off, the PN diode consisting of the P+i of the anode 2 and the N layer of the buffer layer 10 acts as a snubber diode, and the capacitor 9 acts as a snubber diode. Since it acts as a capacitor, there is no need to provide a separate snubber circuit.

The charge stored in the capacitor 9 is transferred to the 8I thyristor 11.
When turned on, the N layer of the buffer layer 10, the N layer of the base region 3, the N layer of the channel 5. It is discharged as an on-current of the SI transistor consisting of one layer of the cathode 1 in preparation for the next off-state.

The following explanation has been made using the 8I thyristor with a second gate as an example, for which the present applicant has applied for a patent, but other self-extinguishing type conductors with two types of gates having opposite conductivity types may also be used. It can be used in exactly the same way in the case of elements.

For example, Figure 2 shows Denial Gate S, which has already been published.
1 is a circuit connection diagram when the method of the present invention is applied to control an I thyristor, in which the same reference numerals as in FIG. 1, which has a second gate electrode 20' on the V layer surface of the
The operation of the SI thyristor 11' is exactly the same as that described above, so a detailed explanation will be omitted.

FIG. 3 is a circuit connection diagram of another embodiment in which the method of the present invention is applied to control a dual gate 8I thyristor, and the same reference numerals as in FIG. 2 indicate parts having the same functions. The difference from Figure 2 is the power supply 14, 15 and switch 16.
, 17(!:) is moved from between the gate 4 and the cathode electrode 6 to between the second gate electrode 20' and the anode electrode 2, and the gate drive circuit consisting of the second gate electrode 20' and the cathode electrode 6 is The operating principle is exactly the same as in the case of FIG. 2, that is, the case of FIG. 1, except that the capacitor 9 connected between the gate electrode 8 and the anode electrode 7 is moved between the gate electrode 8 and the anode electrode 7.

Furthermore, the present invention is applicable not only to the 8I thyristor but also to other self-extinguishing thyristors, such as GTO thyristors, as long as it is a self-extinguishing semiconductor device having two types of gates of opposite conductivity types. It is easy to understand that this is possible.

〔Effect of the invention〕

As explained above, 1. According to the present invention, when driving the gate of a self-extinguishing semiconductor device having two types of gates of opposite conductivity types, only one gate is driven in the same way as a conventional gate drive circuit. By simply connecting the gate control power supply for one gate and simply connecting a capacitor to the remaining gate, the same effect as using a gate drive circuit with a gate control power supply for both gates can be obtained. .

In addition, the semiconductor junction formed between the main circuit electrode on the side not connected to the gate drive circuit of the self-extinguishing semiconductor element to be driven and the gate electrode connected to the capacitor functions as a snubber diode, and Since the capacitor functions as a snubber capacitor, there is no need to provide a separate snubber circuit, thereby providing a simple and highly reliable control method for a self-extinguishing semiconductor device having two types of gates of mutually opposite conductivity types. It is extremely practical.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an embodiment of the method for controlling a self-extinguishing semiconductor device according to the present invention, and Figure 2 is a diagram showing the case where the method of the present invention is applied to the control of a dual-gate 8I thyristor that has already been published. 3 is a circuit diagram of another embodiment in which the method of the present invention is applied to the control of an 8I thyristor, and FIG. 4 is a circuit diagram of a unit element of a SI thyristor with a second gate. FIG. 5 is a schematic diagram showing the cross-sectional structure, and FIG. 5 is a circuit diagram for explaining the operation when opening and closing a DC circuit using the 8I thyristor with the second gate shown in FIG. FIG. 2 is a connection diagram for explaining an example of a circuit configuration. 1... cathode, 2... anode, 3...
・Song base area, 4...Gate, 5...
・Channel, 6...Cathode electrode, 7...
...Anode electrode, 8...Gate electrode, 9...
... Capacitor, 10 ... Buffer layer, 1
1.11'... Thyristor, 12...
Load, 13... Main power supply, 14, 14', 15
, 15'...Power supply, 16, 16', 17
, 17'... switch, 18.19...
...Gate drive circuit, 20...Second gate electrode, 21...Inductance, 22...
Diode, 23... Capacitor, 24...
·resistance.

Claims (1)

[Claims] When driving the gate of a self-extinguishing semiconductor device having two gates of opposite conductivity type, a gate control power supply is connected between one gate and a main electrode of opposite conductivity type via a switch. , and a capacitor is connected between the other gate and the main electrode to which the gate control power supply of the one gate is connected.