JPS6147573A - Timing generator - Google Patents

Abstract

PURPOSE:To obtain a high accuracy with a relatively simple construction, by using a fine delay circuit both for the generation of cycle and the delay setting to enable the generation of cycle and phase with a high resolution. CONSTITUTION:A reference clock at a terminal 13 is counted with a coarse delay device 16 based on a pulse A1 from a cycle generator 12 to obtain a pulse B3 delayed according to an upper delay data CDL of a delay setter 17. A fine delay data CDH of the delay setter 17 and a fine cycle data RD from the cycle generator 12 are added up with an adder 83 and the delay pulse B3 is delayed with a fine delay section 84 according to the addition output. The operation of a cycle generating section is performed with the cycle generator 12 and a fine delay circuit 18 while the delay of a set delay value is done with the coarse delay device 16 and the fine delay circuit 18. A delay is done with the coarse delay device 16 by the reference clock cycle T and the additional output results in a delay below the cycle T.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing generator that is used, for example, in an IC testing device and generates timing signals having various periods and phases.

``Prior Art'' As shown in FIG. 1, this type of conventional timing generator generates a reference clock signal from a period generator 12 at a terminal 13 (CK in FIG. ) and a pulse A2 whose period is m times the period T (m is a positive integer) and a pulse A2 whose period is p times the period T (p is a positive integer smaller than m). In FIG. 2, the period mT of pulse A1 is 8T and 9T alternately and 9,
The period pT of pulse A2 is 2T. The period generator 12 further outputs minute period data RD indicating a delay amount smaller than the period T in accordance with lower data of a weight equal to or less than the period T of the set period data and the generation state of the pulse A1.

The pulses A, , A2 and the minute period data RD are input to the minute delay circuit 14, and a delay of less than the period T is provided in the negative part of the pulses A, , A2 according to the minute period data RD,
They are output as pulses B1 and B2, respectively. In the example of FIG. 2, pulse A is delayed by one. Therefore, the period of pulse B is 8.5T in this example.

Pulse B1. B2 is input to the coarse delay unit 16 of the delay generating section 15. The higher delay data CDL of the delay data CD set in the delay setter 17 is input to the coarse delay device 16, and according to this data, pulse B1 is delayed in units of pulse B2 and output as pulse E. . In FIG. 2, the pulse E is delayed by 4T. This pulse E is input to the minute delay circuit 18, and the delay setter 17
A delay corresponding to the lower delay data CDH in the set delay data CD is given and outputted as a pulse F.

Period generator 12 was constructed as shown in FIG.

That is, cycle data indicating the cycle to be generated is set in the cycle setter 21. In the period data, when the weight is greater than or equal to 1, the count is nl, and when the weight is less than T, the count is 1 - B2. In FIG. 3, the weight of each bit is shown in the case of n+=7+n2=2. In this example, a value obtained by subtracting T from the cycle to be generated is set in the cycle setter 21. In the example of FIG. 2, the period to be generated is 8.5T, and correspondingly, 0011110 is set as shown in FIG.

The set-reset type flip-flop 22 and the n2-bit D-type frizzo-flop 23 receive the initialization signal 1N at the terminal 24.
It has been pre-reset by the iT. When the activation signal 5TART is applied to the terminal 25 as shown in FIG. 4, the clip-flop 22 is set and its Q output G1 becomes the fourth
As shown in the figure, the level becomes high, and the side ports 26 and 27 are opened by the output G1. Also, the start signal 5TART is OR
is applied to the gate 28, and its output S6 causes the gate 29 to
is opened, and the reference clock signal of terminal 13 is output from gate 29.
One of them is output as pulse A1. Also OR key
The output S6 of the counter 28 is input to the load terminal LO of the n1-bit down counter 31, and the upper bit nl of the period setter 21 is preset at the falling edge of the reference clock CK while the signal S6 is being applied. counter 3
The counting content Dl of 1 is 7 in this example as shown in Figure 1.
is output. Thereafter, the counter 31 is counted down at the falling edge of each clock CK.

The output S6 of the OR gate 28 is also supplied to the differentiating circuit 32, and the counter 33 is cleared by the output S7 of the differentiating circuit 32, and its output D4 becomes 0.

The counter 33 is for increasing the period of the pulse A2 by p times T. In this example, p=2, and the counter 33
Every time 2 bits of CK are counted from the reference clock, the AND gate 34 outputs a signal S8 of width T. This signal S
8 is applied to the gate 27, and the signal G1.8 is applied to the gate 27. S8. A coincidence output of the clock CK is obtained as a pulse A2.

The lower bit of B2 in the set cycle data of the cycle setter 21 is applied to the B2 bit adder 35 and added to the output of the clip-flop 23, and the added output is the data terminal of the flip-flop 23. Supplied to ID1. In this example, n2=2, and adder 35 is a 2-bit adder. The carry output CI of the adder 35 is inverted and given to the dart 36, and is given to the gate 9-37 without being inverted. In the initial state, the flip-flop 23 is reset,
Its output is 0, so the carry output c1 is 0 and the gate 36 is open. Further, the upper bit output d2 of the 2-bit output from the adder 35 is at a high level because the lower 2 bits of the set cycle data are 1.0 in this example. The flip 70 knob 23 takes in the output of the adder 35 at the falling edge of the output S5 of the dart 26, and outputs the output as minute cycle data RD of the cycle generator 12. The clip-flop 23 and the adder 35 constitute a cumulative addition circuit.

In this example, when the down counter 31 counts seven clocks CK and the count value DI becomes 0, an output sl is generated from the zero detection circuit 38, which passes through the gate 36, and the signal s
2 is further applied to the gate 26 through the KOR gate 39, and its output s5 is supplied to the OR gate 28, so one of the clocks CK is pulsed 8T away from the gate 29. A1 is output, and an output is generated from the differentiating circuit 32, the counter 33 is cleared, and the down counter 31 is preset with set cycle data. Key
At the falling edge of the output s5 of the input 26, the flip-flop 23 takes in the output of the adder 35, and the output of the 77°70 input 23 becomes da-1+d4=O, and its upper bit output d3 is at a high level. Therefore, the output of the adder 35 becomes 0, 0, the carry output cl becomes high level, and the output d2 of the adder 35 becomes low level.

The same thing is done in this state, but when the next down counter 31 reaches zero, the output S1 of the detection circuit 38 is
passes through the dart 37, producing an output S3, which is taken in by the next clock CK into a 5D flip-flop 41, whose output s4 is supplied to the dart 26, so that the pulse A1 is output from the gate 29 in the same way as before. However, this pulse Al is 9T from the previous pulse A1. Also, the input to the flip-flop 23 is performed, and its output d
3 becomes a low level, and as a result, the output d2 of the adder 35 becomes a high level and returns to the initial state. Therefore, the same thing is repeated, and the cycle of Noculus A1 repeats 8T and 9T,
The period of pulse A2 is 2T, and the minute period data RD are d3 = O, d4 = O (OT) and d3 = 1, d
4=O(0,5T) is repeated at cycles of 8T and 9T.

The minute delay circuit 14 in FIG. 1 is configured as shown in FIG. 5, for example. zorus A1 from the period generator 12. A
2 are converted into pulses A/, , and A/2 through delay circuits 42 and 43, respectively, and are supplied to gates 44, 45, 46, and 47, respectively. The amount of delay of the delay circuits 42 and 43 is the same, and this delay causes the minute cycle data RD of the series A/1 to change. While the period of pulse A1 is 8T, gates 44 and 46 are open when minute period data RD[d3=O,
Gates 45 and 47 are not closed, and gate 44.
The outputs of 46 are supplied to gates 51 and 52, 53 and 54 through OR gates 48 and 49, respectively, and
) 51.53 are fed to OR darts 55.56, respectively. In the above example, the data d4 is always O, the gates 52 and 54 are always open, and the darts 52 and 54 are always closed. Therefore, while d3=0, the pulses A/ and A'2 are respectively It is output as pulses B1 and B2 through gates 44, 48, 51, 55 and 46 degrees 49, 53, 5.6. During period 9T of pulse A1, d3 = 1 + d4 = O. Karake-h4
4, 46 are closed, 4514.7 is open 9, pulse A'l r A'2 is fed to 57.58, delayed respectively, and passed through gates 48, 51, 55 and Pulse BI+8 through K=l-49°53.56
It is output as 2. The pulse B1 at this time is delayed by 8.5T with respect to the previous pulse B1. The next cell 2A passes through gate 44. The same thing is repeated,
The pulse B10 period is 8.5T.

OR gate 55 through delay circuits 61 and 62 that provide delay
, 56.

An example of the coarse delay device 16 in FIG. 1 is shown in FIG.

Counter 63 is cleared by pulse B1 and pulse B
2 is delayed by a delay circuit 64 and counted as a pulse B/2 by a counter 63 as shown in FIG. 8, that is, the counter 63 starts counting after being cleared. The upper data CDL from the delay setter 17 is bl, b in this example.
2 pb3 + b4, 4 bits, and 4T in the figure
, only b3 is '1'' and the others are tt On. This data CDL and the count value D5 of the counter 63 are compared in the coincidence detection circuit 65, and as shown in FIG. 8, the count value D5 is 2, an output S9 is generated from the coincidence detection circuit 65, which opens the metro 6, and the pulse B'2 generated during this time is outputted as a delayed pulse E.

The minute delay circuit 18 in FIG. 1 is configured as shown in FIG. 9, for example. The minute delay data, which is the lower bit of the delay data set in the delay setter 17, is 3 bits b5.
+') 6, bl, these bits b 5 p
Dart 67 and 68 respectively for b 6 r bl
, 7'l and 72, 73 and 74 are reversely controlled to open and close. The delayed pulse E is supplied to the key drawer 68, and the outputs of the numbers 67, 71, and 73 are respectively OR'ed.
Supplied to doors 5, 76, 77, Ketro 8, 72.
Each output of 74 is delayed by T and supplied to OR darts 75, 76, and 77, respectively. The output of OR gate 75 is fed to Dart 71, 72, and the output of 0Rr-door 6 is fed to Dart 73°, T 74. If the minute delay data CDI is 7 delays, bs = Or b6 = 1 + b7 = O
and Ketoro 7, 72, . 73 is open,
Dart 68°71.74 is closed, 0rus E is gate 67°75.72.7 delay circuit 79, dart 76.
As shown in FIG. 8, the signal is delayed by 0.5T through 73°77 and is output as a pulse F. The dotted lines for pulses E and F in FIG. 8 indicate the pulse positions that occur when the set delay amount is O.

"Problems with the Prior Art" As described above, in the conventional timing generator, the period generating section 11 uses the minute delay circuit 14, and the delay generating section 15 also uses the minute delay circuit 18.
In order to generate the timing of various periods and phases with small change units, that is, to increase the resolution, it is necessary to increase the number of delay switching stages of the fine delay circuit 14 and 18. Since the delay degree at 16 is an integral multiple of the reference clock period T, which is 2T in the above example, the minute delay circuit 18
The number of delay switching stages in is greater than that in the minute delay circuit 14. In the minute delay circuit 14.18, it is difficult to accurately maintain the amount of delay of each of the T delay circuit, - delay circuit, and ■ delay circuit without being affected by environmental changes such as temperature changes or changes over time.

"Summary of the invention" The purpose of this invention is to be able to generate period and phase with high resolution.
Relatively simple configuration and cleanliness? We aim to provide a timing generator that has few deteriorating factors and can be expected to have high accuracy.

According to this invention, a pulse of mT period and minute period data smaller than period T, according to a set period are outputted by a period generator, and a coarse delay device using a counter is initialized with the output pulse, The coarse delay device counts the reference clock, and generates a delayed pulse delayed by nT with respect to the output pulse from the period generator according to data with a weight larger than the period T of the set delay amount, and Data with a weight smaller than the period of the delay amount (micro-delay data) and the micro-cycle data from the cycle generator are added in an adder, and a delay corresponding to the addition is added to the delay pulse in a micro-delay circuit. is given to obtain the output timing pulse.

Embodiment FIG. 10 shows an embodiment of the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals. A period generator 12 is used, which can be the same as that shown in FIG. 1 or FIG. only is used. This Noculus A1 is delayed by a coarse delay unit 16 using a counter in accordance with upper delay data CDL of a delay setter 17.

In this case, in this invention, the terminal 1 is
This is done by counting the reference clocks of 3 and obtains Zerus B3 delayed by mT (m is a positive integer including O) with respect to Cruz Al. The upper delay data CDL given from this delay setter 17 to the coarse delay unit 16 has a weight of 7.
This is the above data.

The adder 83 adds the minute delay data CDI % of the delay setter 17, that is, the data whose weight is smaller than T, and the minute period data RD from the period generator 12. The adder 8
The delay pulse B3 of the coarse delay device 16 is added by 1 to the addition output of 3.
is delayed by the minute delay section 84. In the minute delay section 84, when the carry output C3 is generated from the adder 83, the unit delay section 1
If pulse B3 is delayed by IT and supplied to the minute delay circuit 18, and there is no carry output C3, the delayed pulse B3 passes through the unit delay circuit 85 without being delayed and is supplied to the minute delay circuit 18. The minute delay circuit 18 has the same configuration as shown in FIG.
The delay amount is controlled 11] by the addition output TD of 3. However, the coarse delay circuit 1G performs a delay in units of the clock cycle T, and the addition output provides a delay of less than the cycle T, and the fine delay circuit 18 is used for the bits whose weight is T in FIG. Delay switching stage by b5, that is, key-1-67, 68
, 75, the delay circuit 78 is omitted, and the output G of the unit delay circuit 85 is supplied to the circuits 71 and 72.

FIG. 11 shows a concrete example of the coarse delay device 16 and the unit delay circuit 85. The coarse delay unit 16 has almost the same configuration as that shown in FIG. The pulse A1 is delayed by a certain width and is supplied to the clear terminal of the counter 63 as a pulse A1. The count value D 6 of the counter 63 and the upper bit of the delay data.

The bits b1 to b5 are compared in the coincidence detection circuit 65, and when they match, the output is sent to the bits 87 and 88 in the unit delay circuit 85.
The carry output C3 of the adder 83 in FIG.
If there is no carry output C3, gate 87 is opened, and if there is carry output C3, gate 88 is opened. The output of gate 87 is supplied to gate 6 through OR gate 89, and the output of gate 88 is supplied to D-type frizzo 70, 7'91.
The flip-flop 91 takes in the output of the key 1.88 at the base of the terminal 1. pretend,
The output of the buffer f91 is supplied to an OR gate 89. A reference clock CK is provided to the cell controller 6.

FIG. 12 shows an example of the operation of this embodiment when the set period is 8.5T1 and the set delay amount f is 4.5T, as in the description of the prior art. 2 in Figure 10 and reference clock C
K is supplied to the period generator 12, which operates in the same manner as in FIG. 3 to generate a pulse A1 which alternately repeats periods 8T and 9T.
is output, and the small cycle data RD is output with a period of 8 T.
Te d: +=o, d4=o (OT) d3 with period 9T
== 1, d4=O('0.5 T) is output.

The pulse A is delayed by the delay circuit 86 and turned into a pulse 1, and the counter 63 is cleared by the pulse IK, and the counter 63 starts counting the reference clock CK from 0. When the count value D6 reaches 4, the upper data CDL of the set delay amount (b, = 0).

b,,=O, b3=1, b4=Or b5=o
) is detected by the coincidence detection circuit 65, and the delay Noculus B3 is output.

The adder 83 adds the lower data of the set delay amount, that is, the minute delay data CDH (b6''1, b7=o), and the minute period data RD from the period generator 12, and the addition output TD is /''RusA1ノ8 T period ('lj:
ds=1+dG==Q, 9T period d5=0+d
When G = 0, the carry output C3 is 0.9 during the 8T period.
The period of T is 1. Therefore, during the 8T period of the pulse A1, the delayed pulse B3 passes through the keys 1-87 and 89.
1.66 as a pulse Sll. Noculus S
When Ketro 6 hears it, the reference clock CK
is output as pulse G. ) and Luz A, 9T of 8
Between Q, the delayed pulse B3 passes through the gate 88 and is delayed by the period T by the D-type flip-flop block 91.
1□toshiteke' ) 66 'x open<. Therefore/,
a Lus G delays every other pulse A1 by 5T and 6T/
ζ, and the period is 9T.

This pulse G is delayed by the output TD of the adder 83 in the minute delay circuit 18, but this output TD is K dG""1 + d6 = O and a5 = O as described above.

Since d6=0 is repeated alternately, the pulse G is 0 every other time.
．． It is delayed by 5T, and the period of the output pulse H of the minute delay circuit 18 is 8.5T.

If the set delay amount is zero, that is, %b7 is all O, and the set period is 8.5T, the lower 3 in Fig. 12 is set.
The output (TD) of the power calculator 83 is shown by adding 0 in the row.
, d5=O, d6=O, dG-1, d6-〇 are repeated, and pulse (G') 4j is each pulse A1 delayed by T, and pulse G is delayed every other pulse by the minute delay circuit 18. Full extension of 0.5Ta is ・prus (H), which is 8.5T
It becomes a periodic pulse. It is understood that /F pulse i() is delayed by 4.5T with respect to this pulse (1()), and the desired result is obtained.

In other words, the period generator 12 and the minute delay circuit 18
The operation of the period generator 11 in the conventional technique shown in the figure is performed, and the delay of the set delay amount is generated by the coarse delay unit 16 and the fine delay circuit 1.
8, the adder 83 adds minute period data RD to use the small delayed uterus 18 for both cycle generation and delay setting.
and the minute delay data CDH, the minute delay circuit 18 is controlled by the output, and the unit delay circuit 85 performs carry during the addition. This unit delay circuit 85 may also be configured as a one-stage delay switching stage having a T delay circuit within the minute delay circuit 18. In the period generator 12, depending on the set period, the pulse Al may generate different periods alternately as in the above example, or may generate a different period once in multiple times, or may always generate a constant period. It will be easily understood from the specific example shown in FIG. 3 that there are cases for each weight.

``Effects'' As described above, according to the present invention, compared to the conventional timing generator shown in FIG.
Therefore, high clearness can be obtained. Moreover, the conventional micro-delay circuit required delay control of 2T or less, but in the device of the present invention, it is only necessary to perform delay control of T or less, and the number of delay switching stages can be reduced accordingly. The stability is also good.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional timing generator;
2 is a time chart showing an example of its operation, FIG. 3 is a logic circuit diagram showing a specific example of the period generator 12 in FIG. 1, and FIG. 4 is a time chart for explaining its operation.
5 is a logic circuit diagram showing an example of the fine delay circuit 14 in FIG. 11, FIG. 6 is a time chart showing an example of the operation of FIG. 5, and FIG. 8g7 is a specific example of the coarse delay circuit 16 in FIG. 8 is a time chart showing an example of its operation, FIG. 9 is a logic circuit diagram showing a specific example of the minute delay circuit 18 in FIG. 1, and FIG. 10 is a timing chart according to the present invention. FIG. 11 is a logic circuit diagram showing a specific example of the coarse delay unit 1G and unit delay circuit 85 in FIG. 10, and FIG. 12 is a time chart showing an example of the operation of the present invention. Out. 12: Period generator, 13 Two reference clock input terminals, 16
: Coarse delay device, 17: Delay setter, 18: Fine delay circuit,
21: period setter, 31: blanker rank, 63: counter, 65 coincidence detection circuit, 83: adder, 84: minute delay means. Patent Applicant Takeda Riken Kogyo Co., Ltd. Representative of Nippon Telegraph and Telephone Public Corporation Taku Hanano Proceedings Amendment - Do (Voluntary) November 9, 1980

Claims (1)

[Claims] (1) The cycle to be generated is set, and a reference clock with a cycle T is input to generate an output pulse with a cycle mT (m is a positive integer) and to generate minute cycle data indicating a cycle smaller than the cycle T. It is initialized by an output period generator and an output pulse from the period generator, counts the reference clock of the period T, and generates the period according to data with a weight greater than the period T of the set delay amount. a coarse delay device that outputs a delayed pulse delayed by nT (n is a positive integer including 0) with respect to the output pulse from the device, and data with a weight smaller than the period T of the set delay amount and from the period generator. A timing generation device comprising: an adder for adding the minute period data of the adder; and minute delay means for giving a delay corresponding to the added value of the adder to the delay pulse from the coarse delay generator.