JPS6146509A - Voltage supply control circuit - Google Patents

Abstract

PURPOSE:To eliminate the unnecessary outflow of a current and to supply a sufficiently high voltage by interposing the 5th transistor (TR) as a current passage between the control terminal of the 1st TR and the 4th circuit point and outputting the voltage from the 1st circuit point. CONSTITUTION:When a control signal R/W is set to a 0 level, the gate of a TR15 is set to 0V, the source is set to 5V, and the gate potential of the TR15 is held -5V, so this TR15 does not turn on unless the threshold voltage is at >=5V. The threshold voltage of this TR15, however, is -3V, so it does not turn on. Therefore, the high voltage obtained at a circuit point 14 is never discharged through the TR15. Further, when the circuit point 14 is set to a high voltage, the output terminal of a CMOS inverter 25 is held at the 0 level, so the TR21 is still off and the voltage at a circuit point 17 is not discharged through this TR24. Namely, the high voltage is obtained at the circuit point 14 while a signal R/W is at the 0 level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage supply control circuit that controls supply of voltage according to a digital input signal.

[Technical background of the invention and its problems] Recently, non-volatile semiconductor memories (non-volatile semiconductor memories) that are equipped with floating gates and control gates and whose storage contents can be electrically rewritten have been developed.
E2 PROM) has become popular as an alternative to conventional ultraviolet erasable nonvolatile semiconductor memory.

Data rewriting in this memory is performed by injecting electrons into the floating gate through a thin oxide film by tunneling effect, or conversely by emitting electrons from the floating gate. To rewrite data using this tunnel current, 1. Although a higher voltage is required than when reading data, the current capacity of this high voltage may be small because it consumes little power. For this reason, a voltage booster circuit is provided within the same memory chip to internally generate a high voltage different from that used when reading data to write and erase data. Therefore, since a single power supply of, for example, 5 μm is required externally, it is very easy for the user to handle.

Examples of such E2 PROM memory cells are shown in FIGS. 5 through 8. FIG. 5 is a pattern plan view of this memory cell, and FIGS. 6 to 8 are cross-sectional views taken along lines AA', BB', and c-c' in FIG. 5, respectively. be. In the figure, 1 is a p-type silicon semiconductor substrate.

This substrate 1 is provided with an n+ type drain 2 and source 3, and a floating gate 5 is provided on the channel region between the drain 2 and source 3 with a thin gate oxide film 4 interposed therebetween. A control gate 7 is also overlaid thereon with a thin gate oxide film 6 interposed therebetween. Also, 8
1 is a rewriting region, which is constructed by extending the floating gate 5 through an extremely thin oxide film 9 on the n+ type layer on which the drain 2 extends.

The operating principle of this memory cell is as follows.

First, data writing is performed by keeping the drain 2 and source 3 at the reference potential (OV), applying a high voltage to the control gate 7, and raising the potential of the floating gate 5 by 1 through capacitive coupling. Electrons from the drain 2 are injected into the floating gate 5 via the oxide film 9.

For data erasing, the control gate 7 is kept at a reference potential, a high voltage is applied to the drain 2, and electrons from the floating gate 5 are emitted, contrary to the case of data writing.

In a state where electrons are injected into the floating gate 5, even if a read voltage of, for example, 5V is applied to the control gate 7,
Memory cells do not turn on because their thresholds are high. On the other hand, when no electrons are injected into the floating gate 5, the threshold value of the memory cell remains low, so when a read voltage is applied to the control gate 7, the memory cell is turned on. As a result, the memory cell becomes
1'', '0'' data is stored.

Such memory cells are arranged in a matrix in the row and column directions, for example, control gates are commonly connected in the row direction, and drains and sources are each commonly connected in the column direction to form a memory cell array.

In addition, in order to boost the power supply voltage inside the memory chip and obtain a high voltage for writing and erasing data, for example, the ninth
A voltage booster circuit as shown in the figure is used.

This circuit connects the load MOS from the power supply voltage Vc of 5V, for example.
The charge accumulated in the capacitor C1 via the transistor QR is applied to the lock signal φ1. as shown in FIG. Using φ2, the charge is transferred to the next capacitor (,2) via the MOS transistor Q1, and the charge accumulated in this capacitor C2 is transferred to the next capacitor C via the next MOS transistor Q2.
By sequentially repeating the operation of transferring to 3,
A high voltage Vo is obtained at the output end.

However, when such a voltage boosting circuit is combined with an address decoder to apply a boosted high voltage to a selected row of a memory cell array to rewrite data, the following problem arises. That is, there is no problem in itself that the output of the address decoder is at the ``1'' level and the boosted high voltage is supplied to the control gate of the selected row.

However, for the remaining unselected rows, the output of the address decoder is at the "0" level, that is, the output stage thereof is in the on state, so that current flows out from the voltage booster circuit.

Since the voltage booster circuit shown in FIG. 9 utilizes the charge stored in the capacitor, its current supply capacity is extremely small.

Therefore, if there is a current outflow as described above for unselected rows, the boosted voltage decreases, making it impossible to apply a sufficiently high voltage to the selected rows.

[Objective of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to eliminate wasteful current flow from a predetermined voltage to be supplied and to supply a voltage of a sufficiently high value. An object of the present invention is to provide a voltage supply control circuit that can control the voltage supply.

[Summary of the Invention] In order to achieve the above object, the voltage supply control circuit of the present invention supplies a signal corresponding to a digital input signal to a first circuit point, and supplies a predetermined voltage to a second circuit point. and supplying a clock signal to a third circuit point, inserting a current path of a first transistor between the first and second circuit points, and connecting a control terminal of the first transistor to the third circuit point.
A capacitor is inserted between the control terminal of the first transistor and the first circuit point, and a second transistor whose control terminal is coupled to the first circuit point is inserted between the control terminal of the first transistor and the first circuit point. A current path is inserted, and a voltage is output from the first circuit point.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a voltage supply control circuit according to the present invention. This circuit uses, for example, the boosted voltage Vn from the voltage booster circuit shown in FIG.
According to the logic level of the input signal IN, the supply is controlled to the control gate or drain of the memory cells shown in FIGS. 5 to 8. At this time, this voltage supply control circuit is used in conjunction with an address decoder in the E2PROM chip, the input signal IN becomes the decode output of the address decoder, and the output voltage is applied to the control gate of the selected row of the memory cell array. Alternatively, it becomes a write voltage applied to the drain.

In FIG. 1, an input signal IN, which is a decoded output of an address decoder, is supplied to a circuit point 11. Circuit point 1
2 (second circuit point) is supplied with the high voltage Vn boosted by the voltage booster circuit when data is written in the memory cell. Circuit point 13 (third circuit point) has a second
As shown in the timing chart in the figure, a clock signal φ3 is supplied which alternately repeats the power supply voltage 5■ and the reference voltage Ov. There is a depression type (hereinafter referred to as D) between circuit point 11 and circuit point 14 (first circuit point).
type) and an N-channel MOS transistor 15 (referred to as
A current path of a third transistor (transistor) is inserted between the source and drain. A control signal R/W is supplied to the control terminal or gate of the transistor 15, which is set to the "O" level when writing data in the memory cell and set to the "1" level when reading data. Ru.

Between the circuit point 12 and the circuit point 14, a source and drain of an enhancement type (hereinafter referred to as E type) N-channel MOS transistor 16 (first transistor) is inserted. The gate of a D-type N-channel MOS transistor 18' is connected to the circuit point 17 to which the gate of the transistor 16 is connected, and the source and drain of this transistor 18 are both connected to the circuit point 13. has been done. That is, the above M
OS transistor 18 is not used as a transistor but as a capacitor.

Between the circuit point 17 to which the gate of the transistor 16 is connected and the circuit point 14, a source and drain of an E-type N-channel MOS t-transistor 19 (second transistor) is inserted. There is.

The gate of this transistor 19 is connected to the circuit point 14. In addition, the circuit point 17 and the reference voltage Vs (
An E-type N-channel MOS transistor 21 is connected between the circuit point 20 (fourth circuit point) to which the voltage (OV) is supplied.
(fifth transistor) source.

The drain gap is inserted. The respective sources and drains of the circuit point 14 are inserted in series between the circuit point 22 to which the power supply voltage Vc (5■) is supplied and the circuit point 20 supplying the reference voltage v8, and the gates are common. An E-type P-channel MOS transistor 23 and an E-type N-channel MOS transistor 24 connected to C
An input terminal of a MOS inverter 25 (signal inversion circuit) is connected.

The output terminal of this CMOS inverter 25 is connected to the gate of the transistor 21. That is, the signal at the circuit point 14 is supplied to the gate of the transistor 21 via the CMOS inverter 25.

Further, the signal voltage generated at the circuit point 14 is outputted as a high voltage OUT to be applied to the control gate or drain of the memory cell when rewriting data in the memory cell.

Next, the operation of the voltage supply control circuit configured as described above will be explained using the timing chart of FIG. 2. In addition, in explaining the operation, we will use an E-type, N-channel MOS.
The threshold voltage of the transistor is 1V, and the threshold voltage of the D-type N-channel MOS transistor is -3V1E.
The following description assumes that the threshold voltage of a P-channel MOS transistor is 11.

First, when the control signal R/W is at the "0" level, that is, when data is written in a memory cell (not shown) to which the output voltage OUT from this circuit is supplied, the circuit point 12 receives the voltage from the voltage booster circuit. Boosted high voltage vH
is supplied. At this time, the input signal IN is 5■
That is, it is assumed that the decode output signal of the address decoder (not shown) is at the "1" level. At this time, the gate of the transistor 15 is set to OV and the source is set to 5■, so as shown in period 1Wlt1 of the timing chart of FIG. The voltage is set to approximately 3V. As a result, the gate of the transistor 19 is also set to approximately 3V, and the circuit point 17 is connected to the circuit via this transistor 19.
The threshold voltage of the transistor 19 is set to about 2■ which is lower than the voltage 3■ at the circuit point 14 by the threshold voltage 1■ of the transistor 19.

Next, as shown in period t2 of the timing chart in FIG.
7 voltage is level shifted from about 2■ to 6■. As a result, the gate of transistor 16 is biased to about 6V, and a voltage of about 5V appears at circuit point 14, which is lower than the gate voltage of transistor 16 by its threshold voltage. Next, when the clock signal φ3 drops to OV, the voltage at the circuit point 17 is lowered to about 4■, but the voltage at the circuit point 14 is reduced to about 5■ due to the various capacitances and load capacitances present here. will be retained. Thereafter, the voltages at the circuit points 17 and 14 are sequentially level-shifted as shown in FIG. 2 by the lock signal φ3. Finally, the voltage at circuit point 14 is set to a high voltage close to the high voltage VH supplied to circuit point 12.

By the way, when the control signal R/W is set to the O11 level, the gate of the transistor 15 and the Ov1 source are set to 5■, and the gate potential of the transistor 15 is set to 15■ when viewed from the source side. Therefore, this transistor 15 will not turn on unless the absolute value of the threshold voltage is 5V or more. However, this transistor 15
The threshold voltage of this transistor is -3■, so this transistor 15
is not turned on. The high voltage available at circuit point 14 is therefore not discharged via this transistor 15.

Furthermore, when the circuit point 14 is set to a high voltage,
Since the signal at the output terminal of the CMOS inverter 25 is at the 0'' level, the transistor 21 whose gate is supplied with this signal remains in the off state, and the voltage at the circuit point 17 becomes In other words, the high voltage can be stably obtained at the circuit point 14 while the control signal R/W is at the "O" level.

Also, at this time, the circuit point 12 to which the high voltage VH is supplied
The current outflow from the circuit point 14 is sufficient to compensate for the drop in the level of the high voltage obtained at the circuit point 14, and no steady current outflow occurs.

On the other hand, when the input signal IN is set to OVl during the period when the control signal R/W is at the "0" level, that is, the decoded output signal of the address decoder (not shown) is at the "0" level, the circuit point 14 is first connected through the transistor 15. It is set to the “'0” level. Then, the output signal of the CMOS inverter 25 is set to the °1" level and the transistor 21 is turned on. Therefore, even if the clock signal φ3 is supplied to the transistor 18, the circuit point 17 is turned on. Since the gate bias of the transistor 16 is also set to 0■, the circuit point 14 remains at the "O" level.At this time, the transistor 16 is cut off, so the high voltage V supplied to circuit point 12
There is almost no current outflow from n.

Next, when data is read in a memory cell (not shown) to which the output voltage OUT from this circuit is supplied, the control signal R/W is set to the '1' level. The boosted high voltage VH is not supplied and the clock signal φ3 is not supplied to the circuit point 13. Therefore, when a memory cell (not shown) is selected, that is, when the input signal IN is set to the "1" level (5
2) is supplied to the circuit point 11, the "1" level appears as it is at the circuit point 14 via the transistor 15. At this time, a voltage of about 4■ is applied to the circuit point 17 via the transistor 19. However, if the element size of the transistor 16 is made smaller to reduce its driving capability in advance, or if a voltage of 3 to 5 cm is supplied to the circuit point 12, the circuit point 14 is
voltage is not discharged to circuit point 12, and circuit point 1
There is no risk that the "1" level voltage of No. 4 will drop.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the voltage supply control circuit according to the present invention. In this example circuit,
CMOS inverter 25 and transistor 21 are removed from the embodiment circuit shown in FIG.
9 is connected to the circuit point 14 through the source and drain of an E-type N-channel MOS transistor 26, and the gate of this transistor 26 is connected to the circuit point 14. The source of a D-type N-channel MOS transistor 29 is connected between the circuit point 21 to which the gate of the transistor 19 is connected and the circuit point 28 to which the 5-inch power supply voltage Vc for data reading is supplied. , and between the trains, and a reset signal RESET is supplied to the gate of this transistor 29.

This will be explained using the timing chart. First, when data is written, the boosted high voltage VH is applied to the circuit point 12 as described above, and the clock signal φ3, which alternately repeats 5■ and OV, is applied to the circuit point 13. The gate is supplied with a control signal R/°0” level.
W is supplied respectively.

Further, the reset signal RESET is set to the "1" level after a certain period of time has elapsed since the end of data writing.

When the input signal IN is 5.times., a voltage of about 3 V appears at the circuit point 14 in the same manner as described above. At this time, transistor 2
The voltage at the circuit point 27 is also set to about 3. Therefore, if the clock signal φ3 is Ov, a voltage of about 2 cm lower than the gate voltage of the transistor 19 by its threshold voltage appears at the circuit point 17. Then the clock signal φ
When 3 becomes 5■, transistor 1 as a capacitor
8, the voltage at the circuit point 17, which has been set to about 2.2 cm, is level-shifted to about 6.0 cm. As a result, a voltage of about 5V lower than the gate voltage of the transistor 16 by its threshold voltage appears in the transistor 16. By repeating the above operations, as in the previous embodiment,
The voltages at circuit point 27, circuit point 17 and circuit point 14 are sequentially raised in level as shown in FIG. 4 by clock signal φ3. Finally, the voltage at the circuit point 14 is set to a high voltage close to the high voltage ■H supplied to the circuit point 12.

At this time, the reset signal RESET is kept at the "0" level, and a voltage of 5V is supplied from the circuit node 28 to one of the source and drain of the transistor 29, so the transistor 29 is turned off. ing. Therefore, from circuit point 27 and furthermore from circuit point 14 to circuit point 2.
8 does not occur, and the high voltage at circuit point 14 remains stable.

At this time, as in the above case, the current output from the circuit point 12 to which the high voltage vH is supplied is only necessary to compensate for the drop in the level of the high voltage obtained at the circuit point 14; No spillage occurs.

When data writing is completed, the control signal R/W becomes “1”
level, and the high voltage that had been output to circuit point 14 and the voltage at circuit point 17 are discharged through transistor 15. At the same time, the reset signal RESET is set to the 1'' level and the transistor 29 is turned on, thereby discharging the voltage at the circuit point 27 to 5.

Next, when data is read in a memory cell (not shown) to which the output voltage OUT from this circuit is supplied, the control signal R/W is set to the "1" level. Further, the reset signal RESET is kept at the "1" level.

At this time, the boosted high voltage VH is not supplied to the circuit point 12, and the clock signal φ is also not supplied to the circuit point 13.
3 is not supplied. Therefore, when a memory cell (not shown) is selected, that is, when a "1" level (5■) is supplied to the circuit point 11 as the input signal IN, the "1" level is supplied to the circuit point 14 via the transistor 15. appears as is. At this time, a voltage of approximately 5V appears at circuit point 27 via transistor 29, and furthermore, a voltage of approximately 5V appears at circuit point 27.
A voltage of approximately 4V appears through the transistor 19, but it is necessary to reduce the element size of the transistor 16 to reduce its driving capability in advance, or to apply a voltage of 3 to 5V to the circuit point 12. If the voltage at the circuit point 14 is supplied to the circuit point 1 through this transistor 16,
2, and there is no possibility that the 1'' level voltage at the circuit point 14 will drop.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, in each of the above embodiments, the present invention is applied to a circuit that controls the supply of high voltage used when writing data to a memory cell. It can be implemented in any circuit as long as it can be implemented accordingly.

[Effects of the Invention] As explained above, according to the present invention, a signal corresponding to a digital input signal is supplied to a first circuit point, a predetermined voltage is supplied to a second circuit point, and a signal corresponding to a digital input signal is supplied to a third circuit point. a first circuit point between the first and second circuit points;
A current path of a transistor is inserted, a capacitor is inserted between the control terminal of the first transistor and the third circuit point, and a current path between the control terminal of the first transistor and the first circuit point is inserted. A current path of a second transistor whose IJl[l terminal is coupled to the first circuit point is inserted between them,
Since the voltage is output from the first circuit point above,
It is possible to provide a voltage supply control circuit that can eliminate wasteful outflow of current from the predetermined voltage supplied to the second circuit point and supply a voltage of a sufficiently high value.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the voltage supply control circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit according to the embodiment, and FIG. 3 is a voltage supply control circuit according to the present invention. FIG. 4 is a timing chart for explaining the operation of the embodiment circuit of FIG. 3; FIG. 5 is a pattern plan view of a nonvolatile semiconductor memory; 6 is a sectional view of the memory in FIG. 5 taken along the line AA', FIG. 7 is a sectional view taken along the line BB' of the memory in FIG. 9 is a circuit diagram showing an example of a voltage boosting circuit, and FIG. 10 is a timing chart showing a clock signal used in the voltage boosting circuit shown in FIG. 9. be. 11, 17.20.22.27.28...Circuit point, 1
2...Second circuit point, 13...Third circuit point, 14
...First circuit point, 15...Depression type N-channel MOS transistor (third transistor), 16...Enhancement type N-channel MOS transistor
S transistor (first transistor), 18...depression type N-channel MOS transistor,
19... Enhancement type N-channel MOS transistor (second transistor), 21... Enhancement type N-channel MOS transistor (fifth transistor)
), 23... enhancement type transistor
Channel MOS l-transistor, 24...Enhancement type N-channel MOS transistor, 25
... CMOS inverter, 26... Enhancement type N-channel MOS transistor (fourth transistor), 29... Depression type N-channel MoS transistor (sixth transistor). Applicant's Representative Patent Attorney Takehiko Suzue Figure 1's2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 8 Figure 91! ! 1 Chest 10 Diagram φ1 φ2

Claims (9)

[Claims] (1) A first circuit point to which a signal corresponding to a digital input signal is supplied, a second circuit point to which a predetermined voltage is supplied,
A third circuit point to which a clock signal is supplied, a first transistor with a current path inserted between the first and second circuit points, and a control terminal of the first transistor and the third circuit point. The capacitance inserted between the circuit point and the first
a current path is inserted between a control terminal of the transistor and the first circuit point, a second transistor having a control terminal coupled to the first circuit point; A voltage supply control circuit characterized in that a voltage output point is . (2) The digital input signal is supplied to the first circuit point via a current path of a third transistor whose control terminal is supplied with a digital control signal. voltage supply control circuit. (3) The voltage supply control circuit according to claim 2, wherein the third transistor is a depletion type transistor. (4) The voltage supply control circuit according to claim 1, wherein the control terminal of the second transistor is connected to the first circuit point. (5) The voltage supply control circuit according to claim 1, wherein the control terminal of the second transistor is connected to the first circuit point via a current path of a fourth transistor. (6) The voltage supply control circuit according to claim 5, wherein the control terminal of the fourth transistor is connected to the first circuit point. (7) Between the control terminal of the first transistor and the fourth circuit point to which the reference voltage is supplied, there is a fifth transistor whose switch is controlled according to the signal at the first circuit point. The voltage supply control circuit according to claim 1, wherein a current path is inserted. (8) The voltage supply control circuit according to claim 7, wherein the control terminal of the fifth transistor is supplied with the signal of the first circuit point via a signal inversion circuit. (9) A fifth circuit point at which the control terminal of the second transistor is supplied with a voltage lower than the predetermined voltage via a current path of a sixth transistor whose control terminal is supplied with a digital control signal. A voltage supply control circuit according to claim 5, which is coupled to a voltage supply control circuit according to claim 5.