JPS6146498U - digital clock correction device - Google Patents
digital clock correction deviceInfo
- Publication number
- JPS6146498U JPS6146498U JP13172384U JP13172384U JPS6146498U JP S6146498 U JPS6146498 U JP S6146498U JP 13172384 U JP13172384 U JP 13172384U JP 13172384 U JP13172384 U JP 13172384U JP S6146498 U JPS6146498 U JP S6146498U
- Authority
- JP
- Japan
- Prior art keywords
- display
- watch
- digital
- time
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の一実施例に係るデジタル表示時計の
ブロック回路図。
第２図は、本考案の一実施例に係るデジタル表示時計の
外観図。
第３図は、第２図に示す時計の縦断面図。
第４図は、表宗部内の表示セグメント配置図。
第５図ａ ”−は、時計の載置状態を変えた場合の表示
形態を示す正面図。
２ ６ ａ， ２ ６ ｂ・・・・・・載置状態検出
スイッチ、２８・・・・・・表示部、３０・・・・・・
時表示セグメント群、３２・・・・・・分表示セグメン
｝Ｋｌ、４０・・・・・・基準信号発生器、５６・・・
・・・デコーダ、８０・・・・・・分修正回路、８２・
・・・・・時修正回路。FIG. 1 is a block circuit diagram of a digital display timepiece according to an embodiment of the present invention. FIG. 2 is an external view of a digital display timepiece according to an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of the timepiece shown in FIG. 2. Figure 4 is a layout diagram of display segments within the Omoteshu section. Fig. 5 a ''- is a front view showing the display form when the mounting state of the watch is changed. 2 6 a, 2 6 b...Placement state detection switch, 28...・Display section, 30...
Hour display segment group, 32...Minute display segment}Kl, 40...Reference signal generator, 56...
... Decoder, 80 ... Minute correction circuit, 82.
...Time correction circuit.
Claims (1)
より時刻の各桁をカウントするカウンタ群と、各カウン
タのカウント信号をデジタル表示信号に変換するデコー
ダ群と、前記デコーダからのデジタル表示信号により時
刻の各桁をデジタル表示する表示部と、複数の外部スイ
ッチと、前記各外部スイッチの操作により前記対応する
各カウンタのみを強制的に修正する修正回路と、を有す
るデジタル時計において、前記各外部スイッチが時計を
通常の載置状態と異なる少なくとも１つの外装面を底面
とする載置状態とすることによってオンオフ操作される
載置状態検出スイッチで構成されると共に前記表示部内
の各時刻桁を表示する表示素子が時計体の横方向及び縦
方向から見て同一形状となるように構成され、さらに前
記各デコーダ群が時計本を通常と異なる載置状態とした
時に修正されるべき時刻桁のみ常に正常方向を向いて表
示されるように表示信号を切換る表示信号変換回路を含
むことを特徴とするデジタル時計の修正装置。A reference signal generator that generates a reference signal, a counter group that counts each digit of time using the reference signal, a decoder group that converts the count signal of each counter into a digital display signal, and a digital display signal from the decoder. In a digital watch, the digital watch has a display unit that digitally displays each digit of the time, a plurality of external switches, and a correction circuit that forcibly corrects only each of the corresponding counters by operating each of the external switches. The switch is composed of a mounting state detection switch that is operated on and off by placing the watch in a mounting state with at least one exterior surface as the bottom surface, which is different from the normal mounting state, and displays each time digit in the display section. The display elements are configured so that they have the same shape when viewed from the horizontal and vertical directions of the watch body, and each of the decoder groups always displays only the time digits that should be corrected when the watch book is placed in a different state than normal. A correction device for a digital clock, comprising a display signal conversion circuit that switches a display signal so that the display is oriented in the normal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13172384U JPS6146498U (en) | 1984-08-29 | 1984-08-29 | digital clock correction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13172384U JPS6146498U (en) | 1984-08-29 | 1984-08-29 | digital clock correction device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6146498U true JPS6146498U (en) | 1986-03-28 |
| JPH0131987Y2 JPH0131987Y2 (en) | 1989-10-02 |
Family
ID=30690296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13172384U Granted JPS6146498U (en) | 1984-08-29 | 1984-08-29 | digital clock correction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6146498U (en) |
-
1984
- 1984-08-29 JP JP13172384U patent/JPS6146498U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0131987Y2 (en) | 1989-10-02 |
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