JPS6145661Y2 - - Google Patents

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Publication number
JPS6145661Y2
JPS6145661Y2 JP10172278U JP10172278U JPS6145661Y2 JP S6145661 Y2 JPS6145661 Y2 JP S6145661Y2 JP 10172278 U JP10172278 U JP 10172278U JP 10172278 U JP10172278 U JP 10172278U JP S6145661 Y2 JPS6145661 Y2 JP S6145661Y2
Authority
JP
Japan
Prior art keywords
circuit
signal
image signal
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10172278U
Other languages
Japanese (ja)
Other versions
JPS5518887U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP10172278U priority Critical patent/JPS6145661Y2/ja
Publication of JPS5518887U publication Critical patent/JPS5518887U/ja
Application granted granted Critical
Publication of JPS6145661Y2 publication Critical patent/JPS6145661Y2/ja
Expired legal-status Critical Current

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  • Image Input (AREA)
  • Facsimile Image Signal Circuits (AREA)

Description

【考案の詳細な説明】 本考案はフアクシミリ装置等に於いて原稿等を
読取走査して得たアナログ画信号を濃淡二値信号
に変換する画信号二値化回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal binarization circuit that converts an analog image signal obtained by reading and scanning a document or the like in a facsimile machine or the like into a binary tone signal.

従来の此種二値化回路では第1図図示の如くア
ナログ画信号Vを一定の基準レベルLと比較する
ことによつて二値信号Dに変換しているが、斯る
方法では画信号の濃淡の階調変化が比較的小さい
部分Nに対してはこれを充分に二値化できないと
云う欠点があつた。
In the conventional binarization circuit of this kind, the analog image signal V is converted into the binary signal D by comparing it with a fixed reference level L as shown in FIG. There is a drawback that it is not possible to sufficiently binarize the portion N in which the gradation change in gradation is relatively small.

このため、第2図図示の如く、アナログ画信号
Vを比較回路4の一入力として印加すると共に、
その画信号Vを微分回路1で微分したのち反転回
路2で反転して得た信号Hと上記画信号Vを積分
回路3で積分して得た信号Iをレベル調整用の抵
抗5,6をそれぞれ介したのち可変抵抗7で合成
し、その合成信号Cを上記比較回路4の他入力と
して印加することによつて、この比較回路4から
二値信号出力Dを得るようにすることが考れられ
る。
Therefore, as shown in FIG. 2, the analog image signal V is applied as one input to the comparator circuit 4, and
The image signal V is differentiated by a differentiating circuit 1 and then inverted by an inverting circuit 2 to obtain a signal H, and the image signal V is integrated by an integrating circuit 3 to obtain a signal I. It may be possible to obtain a binary signal output D from the comparator circuit 4 by combining the two signals through the variable resistor 7 and applying the composite signal C as another input to the comparator circuit 4. It will be done.

ここで、上記合成信号Cを比較回路4の比較基
準信号としたのは、階調変化が比較的小さく且つ
走査ライン方向で幅広の部分Mを積分波形を比較
基準レベルとして、また、階調変化が小さく且つ
走査ライン方向で幅狭の部分Nを微分波形を比較
基準レベルとして、それぞれ比較検出できるよう
にするためである。なお、図中の抵抗8,9は画
信号V及び合成信号Cのそれぞれレベル調整用の
ものである。
Here, the reason why the above-mentioned composite signal C is used as the comparison reference signal of the comparator circuit 4 is that the integral waveform of the part M where the gradation change is relatively small and wide in the scanning line direction is used as the comparison reference level, and the gradation change This is to allow the differential waveform of the portion N, which is small and narrow in the scanning line direction, to be comparatively detected using the differential waveform as a comparison reference level. Note that resistors 8 and 9 in the figure are for level adjustment of the image signal V and composite signal C, respectively.

斯る第2図の方法に依れば、上述の部分M,N
を共に二値信号として検出でできる訳であるが、
比較基準用の合成信号Cは積分回路のために立上
りが緩やかになるので、画信号Vの各1ライン
(1L)の初期に相当する前縁部(第2図bのT期
間)で階調変化が小さくて幅狭の部分N′が二値
信号として検出できないという不都合が生じる。
According to the method shown in FIG. 2, the above-mentioned parts M and N
Both can be detected as binary signals, but
The composite signal C for comparison reference has a gradual rise due to the integration circuit, so the gradation is adjusted at the leading edge (period T in Figure 2b) corresponding to the initial stage of each line (1L) of the image signal V. A disadvantage arises in that the narrow portion N' where the change is small cannot be detected as a binary signal.

そこで、本考案は斯る問題点を技術的に極めて
容易な手法によつて解決した画信号二値化回路を
提案するものであり、以下、その詳細を第3図に
従つて説明する。
Therefore, the present invention proposes an image signal binarization circuit that solves these problems using a technically extremely easy method, and the details thereof will be explained below with reference to FIG.

第3図aに於いて、フアクシミリの読取走査器
等から導出されたアナログ画信号Vはレベル調整
用の抵抗10を介して差動増幅回路11の一入力
として印加される。一方、この画信号Vの各1ラ
インの期間に亘つて、“ハイ”となる制御信号S
が微分回路12に印加され、この微分回路12の
出力Bがレベル調整用の可変抵抗13及び抵抗1
4を介して上記差動増幅回路11の他入力として
印加される。従つて、アナログ増幅器であるこの
差動増幅回路11の出力は第3図bに図示の如く
前縁の立上りが緩やかになつた画信号V′として
導出され、この信号V′がレベル調整用の抵抗1
5を介して比較回路16の一方の入力として印加
される。また、この信号V′は第2図の場合と同
様に一方では微分回路17と反転回路18の縦続
回路に印加され他方では積分回路19に印加さ
れ、その反転回路18の出力と積分回路19の出
力が抵抗20,21及び可変抵抗22で合成され
て信号Cとなり、この合成信号Cが抵抗23を介
して上記比較回路16の他方の入力として印加さ
れ、この比較回路16から二値信号Dを得るよう
になつている。
In FIG. 3a, an analog image signal V derived from a facsimile reading scanner or the like is applied as one input to a differential amplifier circuit 11 via a level adjustment resistor 10. On the other hand, the control signal S becomes "high" during the period of each line of the image signal V.
is applied to the differentiating circuit 12, and the output B of this differentiating circuit 12 is applied to the variable resistor 13 and the resistor 1 for level adjustment.
4 is applied as another input to the differential amplifier circuit 11. Therefore, the output of this differential amplifier circuit 11, which is an analog amplifier, is derived as an image signal V' whose leading edge has a gradual rise as shown in FIG. 3b, and this signal V' is used for level adjustment. resistance 1
5 as one input of the comparator circuit 16. Further, as in the case of FIG. The outputs are combined by the resistors 20 and 21 and the variable resistor 22 to form a signal C. This composite signal C is applied as the other input of the comparator circuit 16 through the resistor 23, and the binary signal D is output from the comparator circuit 16. I'm starting to get it.

この様に、本考案二値化回路では、フアクシミ
リの読取走査器等から導出されたアナログ画信号
をその各1ラインの初期に相当する前縁部の変化
が緩やかになるようにし、このようにされた画信
号の微分反転出力と積分出力を合成して得る信号
を比較基準信号として上記画信号を二値化するよ
うにしているので、アナログ画信号の上記前縁部
で階調変化が小さく且つ幅狭の部分に対してもそ
れを充分に二値化できることになる。また、画信
号の上記前縁部の変化を緩やかにする際に、入力
画信号とその画信号の各1ラインの期間に亘つて
“ハイ”となる信号の微分出力を差動増幅するよ
うにしているので、それを極めて簡単に実現でき
ると云う利点もある。
In this way, in the binarization circuit of the present invention, the analog image signal derived from a facsimile reading scanner etc. is processed so that the change in the leading edge corresponding to the initial stage of each line is gradual. Since the image signal is binarized using the signal obtained by combining the differential inversion output and the integral output of the analog image signal as a comparison reference signal, the gradation change is small at the leading edge of the analog image signal. Moreover, even narrow portions can be binarized sufficiently. Furthermore, when making the change in the leading edge of the image signal gradual, differential outputs of the input image signal and the signal that is "high" for each line of the image signal are differentially amplified. This has the advantage of being extremely easy to implement.

なお、第3図で画信号の各1ラインの期間に亘
つて“ハイ”となる信号Sを微分回路12で微分
して差動増幅回路11に印加する代りに、第4図
a,bに示すように、信号Sを反転回路25で反
転して、画信号の各1ラインの期間に亘つて“ロ
ー”となる信号S′を積分回路24で積分して、こ
の積分回路24からの信号B′を上記差動増幅回路
11に印加するようにしても、同様の効果が得ら
れる。
Note that instead of differentiating the signal S that is "high" during each line of the image signal in the differential circuit 12 in FIG. 3 and applying it to the differential amplifier circuit 11, the signal S shown in FIG. As shown, the signal S is inverted by the inverting circuit 25, and the signal S', which is "low" for each line of the image signal, is integrated by the integrating circuit 24, and the signal from the integrating circuit 24 is A similar effect can be obtained even if B' is applied to the differential amplifier circuit 11.

また、上記制御信号Sはフアクシミリの同期信
号等から容易に作成することができるのは申すま
でもない。
It goes without saying that the control signal S can be easily created from a facsimile synchronization signal or the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の画信号二値化回路を説明するた
めの信号波形図、第2図は此種二値化回路の先行
技術を示し、同図aはその概略構成を示すブロツ
ク図で、同図bはその動作説明波形図である。第
3図は本考案による画信号二値化回路の一実施例
を示し、同図aはその概略構成を示すブロツク図
で、同図bはその動作説明波形図、第4図は本考
案による画信号二値化回路の異なる実施例を示し
同図aはその概略構成を示すブロツク図で、同図
bはその動作説明波形図である。 12,17……微分回路、11……差動増幅回
路、18,25……反転回路、19,24……積
分回路、16……比較回路。
Fig. 1 is a signal waveform diagram for explaining a conventional image signal binarization circuit, Fig. 2 shows a prior art of this kind of binarization circuit, and Fig. 1a is a block diagram showing its schematic configuration. Figure b is a waveform diagram illustrating the operation. FIG. 3 shows an embodiment of the image signal binarization circuit according to the present invention, FIG. 3a is a block diagram showing its schematic configuration, FIG. Different embodiments of the image signal binarization circuit are shown, and FIG. 3A is a block diagram showing the schematic structure thereof, and FIG. 1B is a waveform diagram illustrating its operation. 12, 17... Differential circuit, 11... Differential amplifier circuit, 18, 25... Inverting circuit, 19, 24... Integrating circuit, 16... Comparing circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 原稿等を読取走査して得たアナログ画信号を濃
淡二値信号に変換するための回路であつて、上記
画信号の各1ライン分の期間に亘つて“ハイ”と
なる信号を微分する微分回路または上記各1ライ
ン分の期間に亘つて“ロー”となる信号を積分す
る積分回路と、上記画信号を一入力とすると共に
上記微分回路または積分回路からの信号を他入力
とする差動増幅回路と、この差動増幅回路の出力
を微分する微分回路と、この微分回路からの信号
を反転する反転回路と、上記差動増幅回路の出力
を積分する積分回路と、この積分回路からの信号
と上記反転回路からの信号とを合成する回路接続
と、上記差動増幅回路の出力を一入力とすると共
に、上記回路接続からの合成出力信号を他入力と
し、二値信号を出力する比較回路と、からなる画
信号二値化回路。
A circuit for converting an analog image signal obtained by reading and scanning a document, etc. into a binary signal of density and darkness, and a differential circuit that differentiates a signal that is "high" over a period of one line of the image signal. circuit or an integrating circuit that integrates a signal that becomes "low" over a period of one line, and a differential circuit that takes the image signal as one input and receives the signal from the differentiating circuit or integrating circuit as the other input. an amplifier circuit, a differentiation circuit that differentiates the output of this differential amplifier circuit, an inversion circuit that inverts the signal from this differentiation circuit, an integration circuit that integrates the output of the differential amplifier circuit, and a signal output from this integration circuit. Comparison of a circuit connection that combines the signal and the signal from the inverting circuit, and the output of the differential amplifier circuit as one input, and the combined output signal from the circuit connection as the other input, and outputs a binary signal. An image signal binarization circuit consisting of a circuit.
JP10172278U 1978-07-20 1978-07-20 Expired JPS6145661Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10172278U JPS6145661Y2 (en) 1978-07-20 1978-07-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10172278U JPS6145661Y2 (en) 1978-07-20 1978-07-20

Publications (2)

Publication Number Publication Date
JPS5518887U JPS5518887U (en) 1980-02-06
JPS6145661Y2 true JPS6145661Y2 (en) 1986-12-22

Family

ID=29040622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10172278U Expired JPS6145661Y2 (en) 1978-07-20 1978-07-20

Country Status (1)

Country Link
JP (1) JPS6145661Y2 (en)

Also Published As

Publication number Publication date
JPS5518887U (en) 1980-02-06

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