JPS6145435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A reproduced video signal obtained by a recording/reproducing device has a time error. As a method of correcting this time error, the reproduced video signal is converted into a digital signal using a clock pulse of a frequency corresponding to the frequency of the reproduced horizontal synchronizing signal and written to memory, and this is read out using a clock pulse of a constant frequency to generate an analog signal. There is a way to reconvert it.

In this case, an AFC circuit is configured to obtain a write clock pulse corresponding to the frequency of the reproduced horizontal synchronizing signal.

However, dropouts occur in the reproduced signal and the reproduced horizontal sync signal is missing, skew causes the period of the reproduced horizontal sync signal to suddenly become longer, or so-called guard band noise is mixed in as a pseudo horizontal sync signal, causing the reproduced horizontal sync signal to become distorted. If the cycle suddenly becomes shorter, the frequency of the output signal of the AFC circuit will be greatly disturbed.

The present invention provides an AFC circuit that can eliminate such drawbacks.

An example of the AFC circuit according to the present invention will be described below, taking as an example the case where a clock pulse for writing to the memory of the above-mentioned time error correction circuit is obtained.

In FIG. 1, 1 is a variable frequency oscillator whose oscillation center frequency is, for example, 12 times the subcarrier frequency, or about 43 MHz, 10 is the output terminal of variable frequency oscillator 1, and 2 is the oscillation pulse 1/6 of this variable frequency oscillator 1. Counter 3 divides the pulse CP from counter 2 into 1/455 to obtain a pulse CH whose frequency is the horizontal frequency and whose pulse width is equal to multiple counts.
This is a counter that forms a . For example, a 9-bit counter is used as the counter 3, and its initial load value is "57".
A pulse CH is obtained when 455 (i.e. ²⁹ - 57) CPs are counted.

4 is a variable delay circuit that obtains a pulse DH by delaying the leading edge of this pulse CH by a predetermined time, and is composed of a monostable multivibrator 5 and a NOR circuit 6, and is configured to maintain the metastable state of the monostable multivibrator 5. τ ₁ can be changed by a voltage E _C obtained from a control circuit described later.

Reference numeral 7 designates a trapezoidal wave signal forming circuit for forming a comparative trapezoidal wave signal SD from the output pulse DH of the variable delay circuit 4, 8 a monostable multivibrator for forming the sampling pulse SP, and 9 a sampling hold circuit.

11 is a window pulse forming circuit; 12 is a horizontal synchronizing signal from the reproduced video signal given to terminal 13;
This is a horizontal synchronization signal separation circuit that extracts PH.

Reference numeral 14 denotes a discrimination circuit, which includes a NAND circuit 15, JK flip-flop circuits 16 and 17, and a monostable multivibrator 18. Reference numeral 19 denotes a control circuit, which includes monostable multivibrators 20, 21, JK flip-flop circuits 22, 23, 24, 25, a NOR circuit 26, and a voltage supply circuit 27. The voltage supply circuit 27 includes a transistor 28, a charging/discharging capacitor 29 , resistors 30, 31, 32, 33, and diodes 34, 35, 36, 37.

38 is a starting circuit, which includes a counter 39, a NAND circuit 40, and a trigger type monostable multivibrator 4.
Consists of 1.

42 is an H select circuit, and NAND circuits 43, 4
Consists of 4 and 45.

46 is a load signal forming circuit.

A delayed pulse MA (FIG. 2B) is obtained from the monostable multivibrator 5 by the leading edge, that is, the falling edge, of the pulse CH (FIG. 2A) from the counter 3,
Therefore, from the NOR circuit 6, a pulse DH (C in the figure) delayed by the time τ ₁ for maintaining the metastable state of the monostable multivibrator 5 is obtained, and this pulse DH
A comparison trapezoidal wave signal SD (D in the same figure) is formed.

In the sampling hold circuit 9, the slope part of the comparison trapezoidal wave signal SD is the sampling pulse from the monostable multivibrator 8.
The oscillation frequency of the variable frequency oscillator 1 is controlled by the output voltage of the SP, and the frequency of the pulse CH obtained from the counter 3 is equal to the frequency of the horizontal synchronizing pulse PH. A pulse having a frequency 6×455 times the frequency of the horizontal synchronizing pulse PH is obtained.

Further, based on the counter information of the counter 3, the window pulse forming circuit ₁₁ generates window pulses W and ( Figure 3 B, C, Figure 4 B, C,
Figures 5B and 5C) are obtained. That is, the window pulse W is a constant count value from the falling edge of the horizontal period pulse CH obtained from the counter 3 (FIG. 3A, FIG. 4A, FIG. 5A), and therefore the pulse CP It is obtained at a position corresponding to a certain period of time.

The determining circuit 14 then determines the positional relationship between the window pulse W and the horizontal synchronizing pulse PH.

That is, the horizontal synchronizing pulse PH (Fig. 3D, Fig. 4D, Fig. 5D) is applied to the JK flip-flop circuit 16.
and 17 as the T input, and the window pulse W is supplied as the R input to the JK flip-flop circuit 16 via the NAND circuit 15, and this window pulse W is supplied as it is to the JK flip-flop circuit 17 as the R input. Ru.

As shown in FIGS. 3 and 4, when the leading edge, and thus the falling edge, of the horizontal synchronizing pulse PH does not fall within the width of the window pulse W, the output Q ₁ of the JK flip-flop circuit 16 (FIG. 3E, E) in Fig. 4 rises with the fall of the horizontal synchronizing pulse PH, and this rise triggers the monostable multivibrator 18, and one of its outputs.
M ₁ (Fig. 3 F, Fig. 4 F) is "1", the other output
₁ (Fig. 3 G, Fig. 4 G) becomes "0", and a constant width pulse NG is obtained.

At this time, the JK flip-flop circuit 17 is not triggered, so its output Q ₀ (Fig. 3H,
FIG. 4H) remains at "0", and output ₀ (FIGS. 3I and 4I) remains at "1".

As shown in FIG. 5, when the leading edge, that is, the falling edge of the horizontal synchronizing pulse PH comes within the width of the window pulse W, the JK flip-flop circuit 17 is triggered, and its outputs Q ₀ and ₀ (FIG. 5 E and F) are "1" and "0" from the leading edge of the horizontal synchronizing pulse PH to the trailing edge of the window pulse W, indicating that there is no skew, guard band noise, or dropout. can get.

At this time, the JK flip-flop circuit 16 is not triggered, so the output M ₁ (G in the figure) of the monostable multivibrator 18 remains at "0", and the output ₁ (H in the figure) remains at "1". keep it.

In the starting circuit 38, the counter 3
At step 9, when the rising edge of the pulse OK (FIG. 6A) from the discrimination circuit 14 is counted, for example, 15 times, the output CA of this counter 39 (FIG. 6B) becomes "1", and the pulse (FIG. 6D) If even one rising edge of is supplied, the output CA of this counter 39
becomes "0". And this output CA is "1"
When the pulse OK is obtained in the discrimination circuit 14 in the state of , the output SN of the NAND circuit 40 (C in the same figure)
However, it falls every time the pulse OK rises to "1", and this causes the monostable multivibrator 41
is triggered, its output, that is, the output IN of the starting circuit 38 (E in the same figure) becomes "1", and the output (F in the same figure) becomes "0". The time period during which the trigger type monostable multivibrator 41 of the starting circuit 38 maintains the monostable state is selected to be, for example, 100 horizontal periods. Therefore, if 100 or more pulses NG are continuously supplied to the discrimination circuit 14, that is, the pulses are OK.
If the period in which the voltage is not obtained continues for 100 horizontal periods or more, the output of the monostable multivibrator 41 is reversed,
Output IN becomes "0" and output becomes "1".

Therefore, in the starting circuit 38, when 15 rising pulses OK are successively supplied, its output IN becomes "1" and becomes "0", and 100 pulses NG are supplied to this starting circuit 38. Hold that state until the pulse NG is supplied.
It becomes "0" when 100 OK pulses are consecutively supplied, and this state is maintained until the next 15 consecutive OK pulses are supplied.

Therefore, when the power is turned on, the horizontal synchronizing pulse PH and the pulse CH from the counter 3 do not have a fixed phase relationship, and as shown in Figures 3 and 4, the leading edge of the horizontal synchronizing pulse PH is in the window. It is not within the width of pulse W. Therefore, at this time, the discrimination circuit 14
In this case, pulse NG is obtained continuously for more than 100 horizontal periods, and the output IN of the starting circuit 38 (J in Fig. 3, J in Fig. 4) is "0", and the output IN (K in Fig. 3, K in Fig. 4) is "0". 1”. Then, the pulse PH is gated from the H select circuit 42 through the NAND circuits 44 and 45, and this is obtained as the output pulse SO (L in Fig. 3, L in Fig. 4). The vibrator is triggered and the sampling pulse SP
(Fig. 3 M, Fig. 4 M) are obtained.

In this case, regardless of the value of the control voltage E _C of the control circuit 19 that controls the time τ ₁ for maintaining the metastable state of the monostable multivibrator 5 of the variable delay circuit 4, the trapezoidal wave signal SD is sampled with the sampling pulse SP. is controlled so that the oscillation frequency of the variable frequency oscillator 1 is kept constant.

However, since the sampling SP is not within the pulse width of the window pulse W, the output of the starting circuit 38
The states of IN and IN remain unchanged; IN is "0" and IN is "1".

Then, as shown in Figure 3, the horizontal synchronization pulse PH
When the leading edge of comes in front of the window pulse W,
The output ₃ (N in FIG. 3) of the JK flip-flop circuit 23 of the control circuit 19 becomes "0" from the leading edge of the horizontal synchronizing pulse PH to the trailing edge of the pulse CH. At this time, the output Q ₂ of the JK flip-flop circuit 22 (O in FIG. 3) and the output Q ₄ of the JK flip-flop circuit 24
(P in the same figure) and the output Q ₅ of the JK flip-flop circuit 25 (Q in the same figure) both become "0". Then, in the "0" section of the output _Q3 of the JK flip-flop circuit 23, the diode 37 is turned on, current flows through the capacitor 29 as shown by arrow A, and the voltage of the capacitor 29 with the polarity shown in FIG. 1 increases. , the power supply voltage E _C for the monostable multivibrator 5 of the variable delay circuit 4 decreases.

Further, when the leading edge of the horizontal synchronizing pulse PH comes after the window pulse W as shown in FIG. 4, the JK flip-flop circuit 24 of the control circuit 19 is triggered by the leading edge of the window pulse.
Since the output Q ₄ (N in Figure 4) is "1",
The JK flip-flop circuit 25 is triggered and its output _Q5 becomes "1" in the interval from the falling edge of the horizontal synchronizing pulse PH to the rising edge of the pulse CH, and in this interval the diode 34 of the voltage supply circuit 27 is turned on. A current flows through the capacitor 29 in the opposite direction to arrow A, the voltage of the capacitor 29 with the polarity shown in the figure decreases, and the voltage E _C increases.

At this time, the output Q ₂ (P in FIG. 4) of the JK flip-flop circuit 22 remains "0", and the output Q ₂ (Q in the same figure) of the JK flip-flop circuit 23 remains "0".
Due to the output ₄ of the JK flip-flop circuit 24, it does not become "0".

The output voltage E _C of the control circuit 19 causes the falling edge of the horizontal synchronizing pulse PH to fall within the width of the window pulse W.

That is, as shown in FIG. 2E, the horizontal synchronization pulse
When the fall of PH comes before the window pulse W, the voltage E _C decreases as described above, and as a result, the time τ ₁ for maintaining the metastable state of the monostable multivibrator 5 of the variable delay circuit 4 increases. As a result, the width of the output pulse MA becomes wider as shown by the broken line in FIG. 2B, and the fall of the delayed pulse DH is also delayed as shown by the broken line in FIG. 2C. The generation position of SD is also delayed as shown by the broken line in D of the figure, and the sampling position of the control voltage for the variable frequency oscillator 1 comes to be within the pulse width of the window pulse W, as shown by the cross mark in the figure. Therefore, relatively horizontal sync pulse
The falling edge of PH falls within the pulse width of window pulse W.

In addition, as shown in Figure 2F, the horizontal synchronization pulse
When the fall of PH comes after the window pulse W, the voltage E _C increases as described above, so that the time τ ₁ for the monostable multivibrator 5 of the variable delay circuit 4 to maintain the metastable state increases. As a result, the width of the output pulse MA becomes narrower as shown by the dashed line in Figure 2B, and therefore the delayed pulse
The fall of DH also advances as shown by the dashed line in Figure C, and as a result, the generation position of the trapezoidal wave signal SD also advances as shown by the dashed line in Figure D, and the control voltage for the variable frequency oscillator 1 increases. The sampling position comes to be within the width of the window pulse W, as indicated by the x mark in the figure. Therefore the horizontal sync pulse
The falling edge of PH falls within the pulse width of window pulse W.

In this way, when the falling edge of the horizontal synchronizing pulse PH comes within the width of the window pulse W,
As shown in FIG. 5, a pulse OK is obtained from the JK flip-flop circuit 17 of the discrimination circuit 14, and the rising edge of the pulse OK triggers the monostable multivibrator 20 of the control circuit 19, which is the same as the window pulse W. A pulse MB (M in Fig. 2) with a pulse width τ ₂ is obtained, and the monostable multivibrator 21 is triggered by the rising edge of the window pulse W, from which a pulse MC (N in the Fig. 2) is obtained. , the output Q ₂ (O in the figure) of the JK flip-flop circuit 22 becomes "1" from the trailing edge of the window pulse W to the trailing edge of the pulse MB.

Since the pulse width of the window pulse W and the time of "1" of the output MB of the monostable multivibrator 20 are both τ ₂ , the leading edge or falling edge of the horizontal synchronizing pulse PH is the window as shown in FIG. When it comes before the center of the pulse width of pulse W,
The pulse's "0" time becomes longer than the "1" time of the output _Q2 of the JK flip-flop circuit 22, and the voltage E _C (Fig. 5P) eventually decreases, causing the output pulse MA of the monostable multivibrator 5 to decrease. The pulse width τ ₁ of is made wide. Conversely, when the leading edge of the horizontal synchronizing pulse PH is behind the center of the pulse width of the window pulse W, the time for output _Q2 to be "0" is longer than the time for pulse OK to be "1", The voltage E _C is increased and the pulse width τ ₁ of the output pulse MA is made narrower.

In this way, the leading edge of the horizontal synchronizing pulse PH is at the center of the pulse width of the window pulse W, so that the "1" time of the pulse OK and the "0" time of the output Q ₂ are equal. So, the output pulse
The pulse width τ ₁ of MA thus controls the position of the trapezoidal wave signal SD with respect to the pulse CH.

In this way, when the leading edge of the horizontal synchronizing pulse PH comes to be at the center of the pulse width of the window pulse W, 15 or more pulses OK and OK are successively obtained from the discrimination circuit 14, and the starting circuit 38
The outputs IN and are inverted, and the output IN (I in FIG. 5) becomes "1" and the output (J in the same figure) becomes "0".

At this time, a pulse OK is obtained from the H select circuit 42 through the NAND circuits 43 and 45 as its output SO (K in the figure), and at the fall of the output, the sampling pulse SP (L in the figure) is sent from the monostable multivibrator 8. is obtained. As a result, the slope portion of the trapezoidal wave signal SD is sampled in the sampling and hold circuit 9, and the oscillation frequency of the variable frequency oscillator 1 is controlled by the output voltage thereof.

Then, pulse OK to the startup circuit 38 like this.
If 15 or more are supplied in succession, this starting circuit 3
When the outputs IN and 8 are in the "1" and "0" states, the starting circuit 38 is difficult to reverse from this state as described above.

At this time, if the interval of the horizontal synchronizing pulse PH is disturbed due to skew or guard band noise, the leading edge of the horizontal synchronizing pulse PH will follow the window pulse W and will not fall within the pulse width of the pulse WG, as shown in Fig. 3. And as shown in FIG. 4, the outputs Q _{0 and 0} of the JK flip-flop circuit 16 of the discriminator circuit 14 do not show OK pulses, and the outputs M ₁ and ₁ of the monostable multivibrator 18 become "1" and "0". ” and a pulse NG indicating that skew or guard band noise has occurred is obtained.

At this time, since no pulse is obtained and the output of the starting circuit 38 is "0", the output SO of the H select circuit 42 does not fall to "0", and therefore sampling is performed from the monostable multivibrator 5. Pulse SP cannot be obtained. Further, since the pulse OK is not obtained and the output Q ₂ of the control circuit 22 does not become "1", the power supply voltage E _C for the monostable multivibrator 5 does not change.

At this time, since the output of the starting circuit 38 is "0", the load signal forming circuit 46 outputs a load pulse LD due to the rise of the pulse NG from the monostable multivibrator 18 of the discrimination circuit 14.
As a result, the counter 3 is forced to be loaded, and the counter 3 is preset to a count value corresponding to the rising edge of the pulse NG at the center of the window pulse W. Therefore, the seventh
As shown in Figures A to F, the delayed pulse DH of the output pulse CH of the counter 3, the comparison trapezoidal wave signal SD based on this, and the window pulse W have a count value at the time corresponding to the center of the window pulse W. It will transition to this loading point. In other words, where skew occurs and the interval between horizontal synchronizing pulses PH increases, the pulses will change accordingly.
CH, its delayed pulse DH, trapezoidal wave signal SD and window pulse W also become delayed in time,
Also, guard band noise causes horizontal sync pulse
Even if the PH interval is disturbed, after that, the horizontal synchronization pulse PH, pulse CH, delayed pulse DH, and trapezoidal wave signal
The temporal relationship with SD and window pulse W is not disturbed.

Therefore, even if there is skew or guard band noise, the output voltage of the sampling and holding circuit 9 does not change, and it maintains the value when the previous horizontal synchronizing pulse PH was obtained at normal intervals, and the output voltage of the variable frequency oscillator 1
The oscillation frequency of is not disturbed.

In addition, the dropout allows the horizontal sync pulse to be
When PH disappears, there is no leading edge of the horizontal synchronizing pulse PH within the pulse width of the window pulse W, so in the discrimination circuit 14, the pulse OK and OK cannot be obtained from the JK flip-flop circuit 17, and the monostable multivibrator 18 also pulse
NG, cannot be obtained. Therefore, since the output IN of the starting circuit 38 is "1" and "0", the output SO of the H select circuit 42 does not fall, and the sampling pulse SP is output from the monostable multivibrator 8.
is not obtained, and the load signal forming circuit 42
Therefore, the load signal LD is not obtained, and the counter 3 is not forced to be loaded.

Therefore, the output voltage of the sampling and holding circuit 9 does not change even due to dropout, and maintains the value when the previous horizontal synchronizing pulse PH was normally obtained, and the oscillation frequency of the variable frequency oscillator 1 is
It's not disturbed after all.

As described above, the frequency control circuit of the present invention determines whether the synchronization signal is in a normal state and prevents the control voltage for the variable frequency oscillator from changing when it is not normal. At the sync signal where the interval is not regular, a counter or preset is used to count the output pulses of the variable frequency oscillator and obtain the pulses for phase comparison with the sync signal. There is no possibility that the frequency of the intended output pulse will be disturbed.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the circuit of the present invention, and FIGS. 2 to 7 are waveform diagrams for explaining the same. 1 is a variable frequency oscillator, 2 and 3 are counters,
4 is a variable delay circuit, 7 is a trapezoidal wave signal forming circuit, 8
9 is a sampling pulse forming circuit, 9 is a sampling hold circuit, 11 is a window pulse forming circuit, 12 is a horizontal synchronizing signal separating circuit, 14 is a discrimination circuit, 19 is a control circuit, 38 is a starting circuit, 42 is H
The select circuit 46 is a load signal forming circuit.

Claims (1)

[Claims] 1. A variable frequency oscillator, a counter that divides the output of the variable frequency oscillator, a trapezoidal signal forming circuit that forms a trapezoidal wave signal from the output of this counter, and a sampling of the slope portion of the trapezoidal wave signal based on a synchronization signal. sampled by pulse,
a sampling hold circuit that controls the oscillation frequency of the variable frequency oscillator using the sampling voltage; a window pulse forming circuit that forms a window pulse of a constant width based on the output of the counter; and a position of the window pulse and the synchronization signal. and a control circuit that generates a control voltage that determines the position of the trapezoidal wave signal with respect to the output of the counter, and the determining circuit determines that the synchronization signal is within the width of the window pulse. When this is detected, the position of the trapezoidal wave signal with respect to the output of the counter is controlled by the control voltage so that the synchronization signal comes to a predetermined point within the width of the window pulse, and the discrimination circuit A frequency control circuit configured to prevent the sampling pulse from being obtained when it is detected that the synchronization signal is not within the width of the window pulse.