JPS6032366B2 - frequency control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A reproduced video signal obtained by a green image reproducer has a time error.

As a method to correct this time error, the reproduced video signal is converted into a digital signal using a clock pulse of a frequency corresponding to the frequency of the reproduced horizontal synchronization signal, and written to the memory, and this is read out using a clock pulse of a constant frequency. There is a method of reconverting it to an analog signal. in this case,
An AFC circuit is configured to obtain a write gate clock pulse corresponding to the frequency of the reproduced horizontal synchronizing signal. However, dropouts occur in the playback signal and the playback horizontal synchronization signal is missing, the period of the playback horizontal synchronization signal suddenly becomes longer due to skew, and so-called guard band noise is mixed in as a pseudo horizontal synchronization signal, causing the playback horizontal synchronization signal to be lost. If the period of the signal suddenly becomes short, there is a problem in that the frequency of the output signal of the AFC circuit is greatly disturbed.

The present invention provides an AF that can eliminate such drawbacks.
This provides a C circuit.

An example of the AFC circuit according to the present invention will be described below, taking as an example the case where a clock pulse for writing to the memory of the time error correction circuit as described above is obtained.

In FIG. 1, 1 is a variable frequency oscillator whose oscillation center frequency is, for example, 12 times the subcarrier frequency, or about 43 MHz, and 2 is a variable frequency oscillator whose oscillation pulse is 1/6
A counter 3 divides the frequency of the pulse CP from the counter 2 into 1/455 to form a pulse CH of a horizontal frequency.

For example, a 12-bit counter is used as the counter 3, and its initial load value is "3641".
A pulse CH is obtained when 455 (ie, 2-3641) pulses CP are counted. 4 is a trapezoidal wave signal forming circuit for forming a comparative trapezoidal wave signal SD from this pulse CH; 5 is a monostable multipiper for forming a sampling pulse SP; 6 is a sampling hold circuit;
7 is a memory, and 8 is a gate circuit.

Reference numeral 9 denotes a window pulse forming circuit, which is composed of two monostable multipipulators 10 and 11, and the time period 7 during which the former's metastable state is maintained can be changed by a voltage Ec obtained from a control circuit, which will be described later.

Reference numeral 12 denotes a horizontal simultaneous signal separation circuit for extracting a horizontal synchronizing signal PH from the reproduced video signal applied to the terminal 13.

Reference numeral 14 denotes a discrimination circuit, which includes a NAND circuit 15, monostable multivibrators 6 and 17, a JK flip-flop circuit 18, and a NAND circuit 19.

20 is a control circuit, monostable multipipulator 21, J
K flip-flop circuits 22, 23, NAND circuits 24~
27 and a voltage supply circuit 28, the voltage supply circuit 28 has a transistor 29, a charging capacitor 30, a resistor 31, and diodes 32 and 33.

34 is a write signal forming circuit, which is composed of a monostable multipipe layer 35 and D flip-flop circuits 36 and 37.

Reference numeral 38 denotes a starting circuit, which includes a counter 39, a NAND circuit 40, and a retrigger type monostable multipipulator 41.

Due to the pulse CH obtained from the counter 3 (FIG. 2A), the monostable multipipelator 10 of the window pulse forming circuit 9 generates 7. Pulse MA (B in the same figure)
) is obtained, and by this pulse MA, 72 window pulses W and W (C and D in the same figure) of mutually opposite polarity are obtained from the monostable multipipelator 11 in a constant pulse. Then, the determination circuit 14 determines the positional relationship between the window halus W and the horizontal synchronizing pulse PH.

That is, as will be described later, the output state of the starting circuit 38 (FIG. 2E)
) is "1", a pulse obtained by inverting the polarity of the window pulse W, that is, a pulse WG (F in the same figure), which is the same as the window pulse W, is obtained from the NAND circuit 15, and a horizontal synchronizing pulse PH (G ) makes the monostable multipipulator 16
A pulse MB (H in the same figure) among the constant pulses is obtained from
From 7, the pulse MC in the constant pulse (Fig. 1) is obtained,
The output pulse WG of the NAND circuit 15 is used as the J input of the JK flip-flop circuit 18, the horizontal synchronizing pulse PH is used as the T input, and the monostable multipipulator 17 is used as the R input.
output pulses MC are respectively connected. Therefore,
As shown in FIG. 2, when the front or falling edge of the horizontal synchronizing pulse PH is within the window pulse W or pulse WG, the JK flip-flop circuit 18
The Q output OK (J in the same figure) is "0" from the front green of the horizontal synchronizing pulse PH to the front green of the pulse MC, and a pulse indicating that no skew, guard band noise, dropout, etc. has occurred is obtained.

Then, due to the fall of this output PK, a sampling pulse SP (K in the same figure) is generated from the monostable multipipulator 5.
is obtained, and in the sampling and holding circuit 6, the oblique part of the comparison trapezoidal wave signal SD (Y in the same figure) formed by the pulse CH (A in FIG. 5) is sampled and held by the sampling pulse SP, and the output voltage is The oscillation frequency of the variable frequency oscillator 1 is controlled so that the frequency of the pulse CH obtained from the counter 3 is equal to the frequency of the horizontal synchronizing pulse PH, that is, 6×45 of the frequency of the horizontal synchronizing pulse PH reproduced by the variable frequency oscillator 1. A pulse of the frequency of fang moss is obtained.

In this case, when the control voltage for the variable frequency oscillator 1 changes, the phase difference (lock phase) between the pulse CH obtained from the counter 3 and the horizontal synchronizing pulse PH and therefore the sampling pulse SP also changes, as shown by B and Z in FIG. from,
The position of the window pulse W also needs to be changed accordingly.

The control circuit 20' is for changing the position of the window pulse W in accordance with the control of the variable frequency oscillator 1 when the leading edge of the horizontal synchronizing pulse PH comes within the pulse of the window pulse W. That is, when the output OK of the JK flip-flop circuit 18 of the discrimination circuit 14 falls, the output MD of the monostable multipipulator 21 (M in FIG. 2) becomes "1" for the above-mentioned fixed time 72 after this fall. , On the other hand, the Q output JA (N in the figure) of the JK flip-flop circuit 22 turns green after the window pulse W.
0” to “1”, JK flip-flop circuit 2
3's Q output JB (0 in the same figure) remains "0", therefore, D○ (P in the same figure) of the NAND circuit 24 changes from green after the window pulse W to the output M of the monostable multipipulator 21.
Until the fall of D, it becomes OJ, and the NAND circuit 25
The output NA (Q in the same figure) is the leading edge of the horizontal synchronizing pulse PH.
In other words, from the rising edge of the output MD of the monostable multipipulator 21 to the trailing edge of the window pulse W becomes "0", and the output NB of the NAND circuit 26 (R in the figure) remains "1", so the NAND circuit Output of 27 Output of 27 UP (S in the same figure)
) is from the front green of the horizontal synchronizing pulse PH to the wind pulse W
It becomes "1" up to the trailing edge of. Then, in the "1" section of the output UP of the NAND circuit 27, the diode 32 of the voltage supply circuit 28 is turned on, and a current flows as shown by the arrow 42 across the capacitor 30, changing the polarity of the capacitor 30 as shown in the diagram. As the voltage decreases, the power supply voltage Ec for the monostable multipipulator of the window pulse forming circuit 9 decreases, and in the "0" section of the output DO of the NAND circuit 24, the diode 33 is turned on and the capacitor 301, a current flows in the opposite direction to the arrow 42, and the sacrificial voltage of the capacitor 30 in the diagram rises, causing the voltage Ec to rise. window pulse W
during the pulse and the output MD of the monostable multivibrator 21
Since the times of "1" in both are 72, as shown in Fig. 2, when the front green of the horizontal synchronizing pulse PH and therefore the rising edge of the output MD comes before the center of the window pulse W, it is a NAND circuit. The time for the output UP of the NAND circuit 27 to be "1" becomes longer than the time for the output DO of the NAND circuit 24 to be "0", and the voltage Ec (T in FIG. The pulse ↑ of the output pulse MA is made small.

Conversely, the green before the horizontal synchronizing pulse PH is the wind pulse W.
When it comes after the center of the pulse of the output DO,
The time for 0 is longer than the time for output UP to be 1,
The voltage Ec is lowered and the pulse 7 of the output pulse MA is made to be larger. In this way, Figure 3 A to S
As shown in FIG.
Therefore, the position of the pulse ↑ of the output pulse MA with respect to the pulse CH of the window pulse W is controlled so that the time of "1" of P is equal to the time of "0" of the output DO. In this way, the leading edge of the horizontal synchronizing pulse PH exists within the pulse of the window pulse W, and one output OK of the discrimination circuit 14 becomes "0", so that the NAND circuit 2
When the output UP of 7 becomes "1", the write signal forming circuit 34 obtains a constant pulse ME (U in FIG. 3) from the monostable multipipelator 35 and supplies it to the counter 3. The first pulse of this pulse ME among the pulses CP to be reduced (V in the same figure) causes ○
The output DA (W in the figure) of the flip-flop circuit 36 rises, and the next pulse causes the output ST (× in the figure) of the flip-flop circuit 37 to rise, and this output ST, which is slightly delayed from the front green of the horizontal synchronizing pulse PH, rises. Upon rising, the current count value of the counter 3 is written into the memory 7.

In Fig. 6, the point marked "STOREJ" indicates that this writing has been performed. When the interval of horizontal synchronizing pulses PH is disturbed due to skew or guard band noise, as shown in Fig. 4 A to G, , the front green of the horizontal synchronizing pulse PH is the window pulse W, therefore the pulse WG
J of the discrimination circuit 14.
The Q output OK (J in the same figure) of the K flip-flop circuit 18 does not become "0", and the output MB (H in the same figure) of the monostable multipipulator 16 becomes "1" based on the horizontal synchronizing pulse PH.
The output of the NAND circuit 19 is NG in the section where
) becomes "0", and a pulse indicating that skew or guard band noise has occurred is obtained.

And at this time, since the output OK does not become "0",
Sampling pulse S from monostable multipipelator 5
P cannot be obtained.

Also, since the output OK does not become "0", the control circuit 20
Output MD of the monostable multipipulator 21 (M in the same figure)
remains "0", the output UP of the NAND circuit 27 remains "1", the output DO of the O-Hand circuit 24 remains "1", and the power supply voltage Ec for the monostable multipipulator 10 does not change. However, at this time, the output is NG.
) rises a little later than the previous green of the horizontal synchronizing pulse PH, so that the count value written in the memory 7 when the previous horizontal synchronizing pulse PH was obtained at a normal interval is retrieved from the gate circuit 8. , counter 3 is forced. The counter 3 is preset to the retrieved count value. Therefore, as shown as "LOAD" in FIG. 6, the output pulse CH of the counter 3 and the comparison trapezoidal wave signal SD and window pulse W based thereon are in the same state as they were at the time of the previous write at this load. will begin to move to . That is, where a skew occurs and the interval between the horizontal synchronizing pulses PH increases, the pulse CH, trapezoidal wave signal SD, and window pulse W also become delayed in time accordingly, and guard band noise causes the horizontal synchronizing pulse to Even if the PH interval is disturbed, after that, the horizontal synchronizing pulse PH and pulse C
H, the temporal relationship between the trapezoidal wave signal SD and the window pulse W is not disturbed. Therefore, the output voltage of the sampling and holding circuit 6 does not change even due to skew or guard band noise, and maintains the value when the previous horizontal synchronizing pulse PH was obtained at normal intervals, and the oscillation frequency of the variable frequency oscillator 1 is disturbed. do not have.

Furthermore, when the horizontal synchronizing pulse PH disappears due to dropout, since there is no leading edge of the horizontal synchronizing pulse PH within the pulse of the window pulse W, the discriminating circuit 14
The Q output OK of the K flip-flop circuit 18 does not become "0", and the output NO of the NAND circuit 19 also does not become "0".

Therefore, the sampling pulse SP cannot be obtained from the monostable multipipelator 5, and the counter 3 is not forced to be loaded as shown in FIG. Therefore, even if the dropout occurs, the output voltage of the sampling and hold circuit 6 does not change, and the previous horizontal synchronizing pulse PH
The value that is normally obtained is maintained, and the oscillation frequency of the variable frequency oscillator 1 is not disturbed.

In addition, in the starting circuit 38, a 4-bit counter 39 is used, and the output NG of the discriminating circuit 14 is "0".
Then, the count value is reset to ``1'', and the output CA, which counts 15 (i.e. 2 - 1) consecutive 0s of output OK, becomes ``1'', and the retrigger type monostable multipipulator is activated. The time for maintaining the metastable state of 41 is set to, for example, 100 fire cycles.

Immediately after the power is turned on, the monostable multipipulator 4
1's output IN is "0", therefore, in the discrimination circuit 14, the output WG of the NAND circuit 15 is always "1", and the J input of the JK flip-flop circuit 18 is always "1", and the output of the circuit 18 is always "1" for each horizontal synchronizing pulse PH. OK becomes "0", and in the control circuit 20, the output UP of the NAND circuit 27 becomes "1" or the output 00 of the NAND circuit 24 becomes "0", and the power supply voltage Ec for one monostable multipipulator is controlled. As a result, the front green of the horizontal synchronizing pulse PH is rapidly drawn into the window pulse W.

Then, if the output OK of the discrimination circuit 14 becomes "0" 15 times in a row without the output NG of the discrimination circuit 14 becoming "0", the output CA of the counter 39 becomes "1", and the output CA of this output CA becomes "1". In this state, each time the output OK becomes "0", the output NC of the NAND circuit 40 becomes "1", the monostable multipipulator 41 is triggered, and its output IN becomes "1". Therefore, as described above, the same pulse as the window pulse W is obtained from the NAND circuit 15 of the discrimination circuit 14, and the above-described operation is performed. As mentioned above, even if the output NG of the discriminator circuit 14 becomes "0", the monostable multipipulator 4
The output IN of 1 does not become "0" immediately, but becomes "0" only when the output OK does not become "0" during the 100K normal period. As described above, the frequency control circuit of the present invention determines whether the synchronization signal is in a normal state and prevents the control voltage for the variable frequency oscillator from changing when it is not normal. At the sync signal that does not have a regular interval, we preset the counter to count the output pulses of the variable frequency oscillator and obtain the pulses whose phase is compared with the sync signal. This prevents the frequency of the output pulse from being disturbed.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the circuit of the present invention, and FIGS. 2 to 6 are waveform diagrams for explaining the same. 1 is a variable frequency oscillator, 2 and 3 are counters, 4 is a trapezoidal signal forming circuit, 6 is a sampling hold circuit, 7
8 is a memory, 8 is a gate circuit, 9 is a window pulse forming circuit, 12 is a horizontal synchronizing signal separating circuit, 14 is a discrimination circuit, 20' is a control circuit, and 34 is a write signal forming circuit. Figure Sphere Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A variable frequency oscillator, a counter that divides the output of the variable frequency oscillator, and a phase comparison circuit that compares the phases of the output of the counter and a synchronization signal and controls the oscillation frequency of the variable frequency oscillator based on the comparison output. a window pulse forming circuit that forms a window pulse of a constant width based on the output of the counter; a determination circuit that determines the positional relationship between the window pulse and the synchronization signal; and a position of the window pulse with respect to the output of the counter. a control circuit that generates a control voltage that determines a control voltage, and when the discrimination circuit detects that the synchronization signal is within the width of the window pulse, the synchronization signal is within the width of the window pulse. When the position of the window pulse relative to the output of the counter is controlled by the control voltage so that it reaches a predetermined point, and the discrimination circuit detects that the synchronization signal is not within the width of the window pulse. , a frequency control circuit configured to stop the phase comparison operation in the phase comparison circuit.