JPS6145388B2 - - Google Patents
Info
- Publication number
- JPS6145388B2 JPS6145388B2 JP16566782A JP16566782A JPS6145388B2 JP S6145388 B2 JPS6145388 B2 JP S6145388B2 JP 16566782 A JP16566782 A JP 16566782A JP 16566782 A JP16566782 A JP 16566782A JP S6145388 B2 JPS6145388 B2 JP S6145388B2
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- wiring
- cutting
- ion implantation
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- -1 argon ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910001430 chromium ion Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法、例えばヒユー
ズ読出し専用メモリ（ヒユーズROM）の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, a method of manufacturing a fuse read-only memory (fuse ROM).
(2) 技術の背景
ヒユーズROMは素子製造後に任意の内容を記
憶させることができる読出し専用メモリで、例え
ば冗長構成を有するRAM（Random Access
Memory）において用いられる。(2) Background of technology Fuse ROM is a read-only memory that can store arbitrary contents after device manufacturing.
Memory).
冗長構成におけるメモリの形成（プログラミン
グ）は、ROMを構成するトランジスタ間の配線
を記憶内容および使用する冗長回路に応じて切断
し、記憶される二値情報に対応した出力電圧を与
える如く回路を構成することによつて行われる。 Memory formation (programming) in a redundant configuration involves cutting the wiring between the transistors that make up the ROM according to the memory content and the redundant circuit to be used, and configuring the circuit to provide an output voltage corresponding to the binary information to be stored. It is done by doing.
第１図はヒユーズROMを構成するトランジス
タ回路の一部を示す概略図で、同図を参照すると
例えばMOS電解効果トランジスタ（FET）１の
ゲートＧはワード線４に、他方ソースＳおよびド
レインＤはビツト線２に接続されている。 FIG. 1 is a schematic diagram showing a part of a transistor circuit constituting a fuse ROM. Referring to the figure, for example, the gate G of a MOS field effect transistor (FET) 1 is connected to the word line 4, while the source S and drain D are connected to the word line 4. Connected to bit line 2.
一方、ヒユーズ３はビツト線２中トランジスタ
１のドレイン電極近くに設けられ、上記配線切断
は当該ヒユーズ３を焼き切つてビツト線との導通
を断つ方法で行われる。 On the other hand, the fuse 3 is provided in the bit line 2 near the drain electrode of the transistor 1, and the wiring is cut by burning out the fuse 3 to cut off the conduction with the bit line.
第２図は従来のヒユーズROMにおける上記ヒ
ユーズ部分を示す平面図で、同図において、２１
はヒユーズを形成する多結晶（ポリ）シリコン
（以下にはヒユーズポリシリコンという）、２２は
アルミニウム（Al）配線、２３はコンタクトホ
ールを示す。これら配線層の上にはいずれも燐シ
リケートガラス（PSG）の層間絶縁膜と保護膜
（パツシベーシヨン膜）とが形成されている。 FIG. 2 is a plan view showing the above-mentioned fuse portion in a conventional fuse ROM.
Reference numeral 22 indicates polycrystalline silicon (hereinafter referred to as fuse polysilicon) forming a fuse, 22 indicates an aluminum (Al) wiring, and 23 indicates a contact hole. An interlayer insulating film and a protective film (passivation film) made of phosphorous silicate glass (PSG) are formed on these wiring layers.
(3) 従来技術と問題点
従来プログラミングにおける配線切断は、第２
図に示すアルミニウム配線２２，２２の間に過電
流を流してヒユーズポリシリコン２１を焼き切る
方法で行われる。(3) Conventional technology and problems Wiring cutting in conventional programming is
This is done by passing an overcurrent between the aluminum wires 22 and 22 shown in the figure to burn out the fuse polysilicon 21.
しかし、上述の方法においては焼き切れたポリ
シリコンが周辺に飛び散り、この飛び散つたポリ
シリコンが素子表面に付着して短絡等の原因とな
り、また切断時に大電圧を加えるため素子へ悪影
響を及ぼし、消費電力が大きく、更には上記ヒユ
ーズ切断作業が繁雑であるなどの問題点がある。 However, in the above-mentioned method, the burned out polysilicon scatters around the device, and this scattered polysilicon adheres to the surface of the device, causing short circuits, etc. Also, since a large voltage is applied during cutting, it has an adverse effect on the device. There are problems such as high power consumption and complicated cutting of the fuse.
(4) 発明の目的
本発明は上記従来の問題点に鑑み、ヒユーズ
ROMの製造方法において、ヒユーズ切断による
素子特性劣化をまねくことなく、かつ容易に配線
を切断しうる方法の提供を目的とする。(4) Purpose of the invention In view of the above-mentioned conventional problems, the present invention provides a fuse
The purpose of the present invention is to provide a method for manufacturing a ROM that allows wiring to be easily cut without causing deterioration of element characteristics due to fuse cutting.
(5) 発明の構成
そしてこの目的は本発明の方法によれば、絶縁
膜上にヒユーズが設けられた半導体装置を製造す
る方法において、該ヒユーズの切断すべき箇所に
該ヒユーズを構成する物質に比べて自己活性化エ
ネルギーの異なる物質を導入することを特徴とす
る半導体装置の製造方法を提供することによつて
達成される。(5) Structure of the Invention According to the method of the present invention, in a method for manufacturing a semiconductor device in which a fuse is provided on an insulating film, a material constituting the fuse is cut at a location where the fuse is to be cut. This is achieved by providing a method for manufacturing a semiconductor device, which is characterized by introducing substances with different self-activation energies.
(6) 発明の実施例 以下、図面によつて本発明実施例を詳説する。(6) Examples of the invention Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.
エレクトロマイグレーシヨン
（electromigration）は、例えばアルミニウム
（Al）配線に直流電流（電流密度105〜106A/cm3）
を流した場合に、アルミニウム原子が輸送される
現象で、当該アルミニウム原子が移動した後には
ボイドが発生し、条件によつては断線に至ること
が経験されている。 Electromigration is a process in which direct current (current density 10 5 to 10 6 A/cm 3 ) is applied to aluminum (Al) wiring, for example.
This is a phenomenon in which aluminum atoms are transported when a wire is passed through the wire, and after the aluminum atoms move, voids are generated, and depending on the conditions, it has been experienced that this can lead to wire breakage.
エレクトロマイグレーシヨンは、主として配線
金属の結晶粒が大きいほど、またその大きさが急
激に変化する場所で起りやすく、更に配線の幅と
長さに依存することが知られている。 It is known that electromigration is more likely to occur as the crystal grains of the wiring metal become larger or where the size changes rapidly, and that it also depends on the width and length of the wiring.
第３図は本発明の１つの実施例を説明するため
のヒユーズROMの一部平面図で、同図を参照す
ると、アルミニウム配線３１（第１図のビツト線
２に当る配線）に同じアルミニウムではあるが配
線幅が狭い（6000Å〜１μｍ）ヒユーズ３２を通
常の技術で形成する。 FIG. 3 is a partial plan view of a fuse ROM for explaining one embodiment of the present invention. Referring to the same figure, it can be seen that the aluminum wiring 31 (corresponding to the bit line 2 in FIG. 1) is made of the same aluminum wire. However, a fuse 32 having a narrow wiring width (6000 Å to 1 μm) is formed using a conventional technique.
次いでイオン注入法により例えば銅（Cu）も
しくはクロム（Cr）をエネルギー数10KeV、ド
ーズ量1013から1015cm-2の範囲で、上記ヒユーズ
３２のうち切断を必要としないヒユーズに注入す
る。上述した銅もしくはクロムのイオン注入は、
エレクトロマイグレーシヨンを起り難くする効果
があるため、配線切断に選択性をもたせることが
できる。 Next, by ion implantation, copper (Cu) or chromium (Cr), for example, is injected at an energy level of 10 KeV and a dose in the range of 10 13 to 10 15 cm -2 into the fuses 32 that do not require cutting. The copper or chromium ion implantation mentioned above is
Since it has the effect of making electromigration less likely to occur, it is possible to provide selectivity in wiring cutting.
次いでヒユーズに適宜選定された値の電流を流
しエレクトロマイグレーシヨンを起させる。この
とき上記イオン注入を行わなかつたヒユーズは第
３図ｂに符号３３で示す如く切断されるが、イオ
ン注入を行なつたヒユーズは同図ａに示す如くも
とのままの状態を保つ。 Next, a suitably selected value of current is applied to the fuse to cause electromigration. At this time, the fuses for which the ion implantation was not performed are cut off as shown by reference numeral 33 in FIG. 3B, while the fuses for which the ions were implanted remain in their original state as shown in FIG. 3A.
かくして、イオン注入によつて記憶内容および
使用する冗長回路に応じた回路配線を完了する。
なお上述したイオン注入は同図ａに破線３４で示
すスポツト形の領域に行う。これは、配線３１お
よびヒユーズ３２の周囲が絶縁物であり、この絶
縁物に前記銅やクロムを注入しても素子特性には
何等悪影響を与えることがないからで、この結果
イオン注入の制御が容易となる効果がある。 Thus, by ion implantation, circuit wiring according to the memory contents and the redundant circuit to be used is completed.
The above-mentioned ion implantation is performed in a spot-shaped region indicated by a broken line 34 in FIG. This is because the area around the wiring 31 and the fuse 32 is an insulating material, and even if the copper or chromium is implanted into this insulating material, it will not have any adverse effect on the device characteristics.As a result, the control of ion implantation will be difficult. This has the effect of making it easier.
また当該エレクトロマイグレーシヨンを利用し
た切断個所は整つた形状のものであり、従来技術
のように切断時に破片が周囲に飛び散ることがな
いため、周辺回路の汚染または破損防止に効果が
ある。 In addition, the cut points using electromigration have a regular shape, and unlike the prior art, debris does not scatter around when cutting, which is effective in preventing contamination or damage to peripheral circuits.
一方、エレクトロマイグレーシヨンを起させる
のに必要な消費電力は従来のポリシリコンのヒユ
ーズの場合に比べて少なく、素子特性に影響を与
えることがない。 On the other hand, the power consumption required to cause electromigration is lower than in the case of conventional polysilicon fuses, and device characteristics are not affected.
ところで、上記ヒユーズ３２の幅は、本実施例
の値に限るものでなく、配線の他の部分に悪影響
を与えることなく、かつ少ない消費電力でエレク
トロマイグレーシヨンによる切断が容易に起る如
く選定する。 By the way, the width of the fuse 32 is not limited to the value of this embodiment, but should be selected so that it can be easily cut due to electromigration without adversely affecting other parts of the wiring and with low power consumption. .
再び、第３図を参照して本発明の他の実施例を
説明する。 Another embodiment of the present invention will be described with reference to FIG. 3 again.
本実施例は切断すべきヒユーズ３２にアルゴン
（Ar）をイオン注入するもので、当該アルゴンイ
オン注入はエレクトロマイグレーシヨンを起りや
すくすることに効果がある。イオン注入の注入条
件は第１の実施例と同様であるが、注入領域はマ
スクによつて指定する。なお該マスクは記憶内容
および冗長回路構成に応じて形成する。 In this embodiment, argon (Ar) ions are implanted into the fuse 32 to be cut, and the argon ion implantation is effective in making electromigration more likely to occur. The conditions for ion implantation are the same as in the first embodiment, but the implantation region is designated by a mask. Note that the mask is formed depending on the memory contents and redundant circuit configuration.
上記イオン注入後はヒユーズ３２に電流を流
す。このときの電流値はエレクトロマイグレーシ
ヨンによつてアルゴンイオン注入を行なつたヒユ
ーズが切断し、そうでないヒユーズが切断しない
ような値に適宜選定する。かくしてヒユーズ
ROMのプログラミングが完了する。 After the ion implantation, a current is passed through the fuse 32. The current value at this time is appropriately selected to such a value that fuses into which argon ions have been implanted are blown by electromigration, but other fuses are not blown. Thus the fuse
ROM programming is complete.
なお上記通電時における消費電力は、第１の実
施例と同様、従来技術に比べて少なく省エネルギ
ーに効果がある。 Note that the power consumption during the above-mentioned energization is lower than that of the prior art, as in the first embodiment, and is effective in energy saving.
ところで、上述した実施例における注入イオン
の種類は前記銅、クロム、アルゴンに限ることは
なく、アルミニウム配線におけるエレクトロマイ
グレーシヨンを起りやすくするか、もしくは制御
するかの目的に応じて適宜選定する。この選定は
一般的には、そのイオンの自己活性化エネルギー
と配線金属のそれとの大小関係に従つてなすこと
ができる。すなわち、上記自己活性化エネルギー
の大小は、エレクトロマイグレーシヨン等の輸送
現象におけるその原子の動きやすさに相当し、本
実施例における銅およびクロムの自己活性化エネ
ルギーは、配線金属であるアルミニウムより小さ
いため、アルミニウム原子の移動を制御する効果
がある。 By the way, the type of implanted ions in the above-described embodiments is not limited to the copper, chromium, and argon, and is appropriately selected depending on the purpose of facilitating or controlling electromigration in the aluminum wiring. This selection can generally be made according to the magnitude relationship between the self-activation energy of the ion and that of the wiring metal. In other words, the magnitude of the self-activation energy described above corresponds to the ease of movement of the atoms in transport phenomena such as electromigration, and the self-activation energy of copper and chromium in this example is smaller than that of aluminum, which is the wiring metal. Therefore, it has the effect of controlling the movement of aluminum atoms.
(7) 発明の効果
以上詳細に説明した如く、本発明の方法によれ
ば、切断面積が小なるヒユーズが提供され、ヒユ
ーズROMのプログラミングにおいて、従来技術
に比べ消費電力が少なくてすみ、切断形状が整つ
たものであり、またイオン注入マスクを１枚だけ
従来技術に追加することによりヒユーズ切断に選
択性をもたせることができ、更にはヒユーズ
ROM製造のマスタースライス化にも応用できる
ため、半導体装置の信頼性および歩留りの改善に
効果大である。(7) Effects of the Invention As explained in detail above, according to the method of the present invention, a fuse with a small cutting area is provided, and when programming a fuse ROM, power consumption is lower than that of the conventional technology, and the cutting shape can be reduced. In addition, by adding only one ion implantation mask to the conventional technology, it is possible to provide selectivity in fuse cutting, and furthermore, by adding only one ion implantation mask to the conventional technology, it is possible to
Since it can also be applied to master slicing in ROM manufacturing, it is highly effective in improving the reliability and yield of semiconductor devices.
第１図はヒユーズROMにおける回路要部の
図、第２図は従来技術におけるポリシリコンヒユ
ーズを示すヒユーズROM要部の平面図、第３図
は本発明の実施例を説明するためのアルミニウム
配線要部の平面図である。
１……MOS FET、２……ビツト線、３……ヒ
ユーズ、４……ワード線、２１……ヒユーズポリ
シリコン、２２，３１……アルミニウム配線、２
３……コンタクトホール、３２……ヒユーズアル
ミニウム、３３……切断個所、３４……イオン注
入領域。
Fig. 1 is a diagram of the main part of the fuse ROM circuit, Fig. 2 is a plan view of the main part of the fuse ROM showing a polysilicon fuse in the prior art, and Fig. 3 is an outline of the aluminum wiring for explaining the embodiment of the present invention. FIG. 1...MOS FET, 2...Bit line, 3...Fuse, 4...Word line, 21...Fuse polysilicon, 22, 31...Aluminum wiring, 2
3... Contact hole, 32... Fuse aluminum, 33... Cutting location, 34... Ion implantation region.
Claims (1)
を製造する方法において、該ヒユーズの切断すべ
き箇所に該ヒユーズを構成する物質に比べて自己
活性化エネルギーの異なる物質を導入することを
特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a fuse is provided on an insulating film, characterized in that a substance having a different self-activation energy than the substance constituting the fuse is introduced into a location where the fuse is to be cut. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57165667A JPS5955061A (en) | 1982-09-22 | 1982-09-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57165667A JPS5955061A (en) | 1982-09-22 | 1982-09-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5955061A JPS5955061A (en) | 1984-03-29 |
| JPS6145388B2 true JPS6145388B2 (en) | 1986-10-07 |
Family
ID=15816724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57165667A Granted JPS5955061A (en) | 1982-09-22 | 1982-09-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5955061A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10344391A1 (en) * | 2003-09-25 | 2005-05-12 | Infineon Technologies Ag | Arrangement for connection in integrated MOS structures |
| KR100979367B1 (en) | 2008-03-19 | 2010-08-31 | 주식회사 하이닉스반도체 | Method for forming the fuse of semiconductor device |
-
1982
- 1982-09-22 JP JP57165667A patent/JPS5955061A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5955061A (en) | 1984-03-29 |
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