JPS6144255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flaw detection digital signal processing method for detecting flaws on the surface of an object such as a slab.

If there are flaws on the slab surface, the steel plate formed by rolling will have flaws that spread in the rolling direction.
This will reduce the quality of the steel plate. Therefore, it is necessary to detect flaws on the surface of the slab and remove them using a flaw removing device such as a scarf remover before rolling. As a flaw removing device, a structure is adopted in which, for example, a gas burner is used to melt and flatten the flawed portion.

In order to detect defects on the surface of a slab as described above, for example, as shown in FIG. Additional configurations are being considered. Note that 1a and 1b indicate flaws on the slab surface, and 2a indicates infrared line scanner 2.
shows the instantaneous field of view.

The scanning range of infrared line scanner 2 is slab 1
Since the slab 1 is conveyed in a direction perpendicular to the scanning direction, the entire surface of the slab 1 can be scanned by selecting the scanning speed corresponding to the conveyance speed. I can do it. The scanning output signal has a level corresponding to the temperature of the slab 1, and includes flaw signals having widths and levels corresponding to the flaws 1a and 1b.

When slab 1 is formed and transported,
It is at a high temperature in a red-hot state, and the scanning output signal from the infrared line scanner 2 has a level corresponding to its surface temperature, for example, as shown in FIG. 2a. That is, if there are no flaws on the surface of the slab 1, the waveform will be approximately flat as shown in the first period, and if there is a flaw, the waveform will be a, b, c, etc. in the second and third periods depending on the condition of the flaw. The waveform includes flaw signals as shown in D and E.

The period between the rising edge and the falling edge of the scanning output signal indicates the width of the slab 1, and the slab width signal shown in FIG. 2b is formed from the scanning output signal. Further, scanning is performed in synchronization with the synchronizing signal shown in FIG. 2c, and the high level section of this synchronizing signal indicates the scanning range. The aforementioned scanning output signal, slab width signal and synchronization signal are applied from the infrared line scanner 2 to the signal processing device 3 to extract the flaw signal.

Various means for extracting flaw signals have already been proposed, but no sufficient means has yet existed. For example, there is known a method of extracting the flaw signal by passing the scanning output signal through a high-pass filter, taking advantage of the fact that the flaw signal contains a higher frequency component than the background signal component. In such a means, the scanning output signal is, for example, as shown in FIG. 3a, flaw signals a1, a2,
a3, the output of the high-pass filter is the third
The result is shown in Figure b. That is, the waveform is obtained by differentiating the scanning output signal. Therefore, signals b1 and b4 are obtained at the rising and falling edges of the scanning output signal, and signals b1 and b4 are obtained corresponding to the flaw signals a1, a2, and a3, respectively.
1', b2, b3, b3' are obtained. flaw signal a1
It is difficult to separate the signal b1' from the signal b1 because the signal b1' corresponding to the signal b1' is considered to be a part of the signal b1. This indicates that extraction of the flaw signal a1 is impossible. Furthermore, for the flaw signal a3 corresponding to a wide flaw, the signals b3 and b
3', making it impossible to accurately detect the size and polarity of the flaw.

Another method is to pass the scanning output signal through a low-pass filter, extract the background signal component excluding the flaw signal, as shown in FIG. It is also known to extract a flaw signal by delaying the signal as shown in FIG. 3d and determining the difference between the signals shown in FIG. 3c and d. In this case, the background signal component obtained through the low-pass filter is the flaw signal a1, a
2 and a3, the background signal waveform will not be faithful, and the rise and fall will be gradual. Therefore, by calculating the difference between the signals in FIG. 3c and d, the signal shown in FIG. 3e is obtained. That is, the flaw signal a1,
Signals c2', c4, and c7 are obtained corresponding to a2 and a3, but signals c1 and c10 are obtained at the rising and falling edges of the scanning output signal, and furthermore, the level of the background signal component is affected by the flaw signal. Signals c2, c3, c5, c6, c due to changes in response to
8, c9 is obtained.

In this case as well, the signal c2' corresponding to the flaw signal a1 is considered to be a part of the signal c2, so that it cannot be detected accurately. Also signal c
1 and c10 can be removed using the slab width signal, but the shaded signals cannot be removed and are therefore regarded as flaw signals. That is, there is a drawback that the false flaw signal is mixed into the real flaw signal and extracted.

It is also known to image the slab surface with an infrared or visible light television camera and perform the same signal processing as described above for each scanning line of the video signal, but in this case, the same problems as described above occur. occurs,
It was not possible to accurately detect flaws including flaws at the ends of the slab.

The present invention eliminates the above-mentioned conventional drawbacks, and makes it possible to extract faithful background signal components from the scanning output signal through digital processing, thereby accurately extracting flaw signals near the rising edge of the scanning output signal and other flaw signals. The purpose is to Examples will be described in detail below.

FIG. 4 is a block diagram of an embodiment of the present invention, in which 10 is an input terminal for converting an analog scanning output signal from an infrared line scanner into a digital signal by an AD converter (not shown) and inputting the digital signal;
stores a digital signal over n periods, and n
12 and 16 are average calculation circuits, 13 is an average section selection circuit, 14 is a flaw signal component determination circuit, 1
5 is a switching control circuit, 17 is a subtraction circuit, 18, 20
1 is a separation circuit, 19 and 21 are flaw signal output circuits including digital high-pass filters, 22 is a delay circuit that delays the synchronization signal in accordance with the signal processing delay time of each part, 23 is an input terminal for the slab width signal, and 24 is a 25 is a high temperature flaw signal output terminal, 26 is a low temperature flaw signal output terminal, and 27 is a synchronization signal output terminal.

The multiplex storage device 11 stores the instantaneous value of the scanning output signal, which is sampled at a period t by an AD converter (not shown) and whose sampling value is converted into a k-bit digital signal, over n periods.
It has a configuration that can output the stored contents for n periods in parallel, and can be configured by a charge transfer device (CCD) or a shift register.
It can also be constructed using random access memory.

The average calculation circuit 12 adds n input signals of k bits and performs a 1/n calculation to obtain the average value of the k bit configuration of the scanning output signal in a wide average interval over n periods and outputs the average value. multiple storage device 1
1 and the output of the average section selection circuit 13 are selected in response to a signal from the switching control circuit 15 to perform the above-mentioned average value calculation. Furthermore, the average calculation circuit 16 adds m (m<<n) outputs of k bits among the n outputs of k bits of the multiplex storage device 11 around the center To of the n period, and calculates the sum of 1/m. It performs calculations and outputs the average value of a k-bit structure in a narrow average interval over m periods.

The defect signal component determination circuit 14 digitizes the signal from the infrared line scanner using an AD converter (not shown) and applies the signal to the input terminal 10, and the average of the wide average interval or narrow average interval via the average interval selection circuit 13. It compares the value output and determines whether the difference is within a specified value, and applies the determination result to the switching control circuit 15. The switching control circuit 15 is
When the judgment output of the defect signal component judgment circuit 14 indicates that it is within the specified value, the average value is calculated by the average calculation circuit 12 for the n outputs of the multiplex storage device 11, and when it is not within the specified value, the input signal at that time is Instead of the output of the corresponding multiplex storage device 11, the average value output via the average interval selection circuit 13 is selected and added to the average calculation circuit 12. That is, if a judgment result that is not within the specified value is obtained consecutively, the average value output via the average section selection circuit 13 is used as the average value output by the individual average calculation circuit 12 instead of the latest storage content of the multiple storage device 11. The (n-) outputs of the multiplex storage device 11 are applied to the average calculation circuit 12, and the average value for n periods is calculated.

Further, the switching control circuit 15 is connected to the flaw signal component determination circuit 1.
4, and has a function of controlling the average interval selection circuit 13 according to the plurality of determination outputs. Depending on the slab width signal applied to the terminal 23 and the control signal from the switching control circuit 15, either the average value output of the wide average interval by the average calculation circuit 12 or the average value output of the narrow average interval by the average calculation circuit 16 is output. Select and output.

The output of the average interval selection circuit 13 indicates the background signal component excluding the flaw signal, and the difference between it and the stored content corresponding to the center T ₀ of the n period of the multiple storage device 11 is calculated in the subtraction circuit 17. Ru. That is, the difference between the average value over n periods or m periods and the instantaneous value at the center T ₀ is determined.

The specified value in the flaw signal component determination circuit 14 is set in consideration of fluctuations in the background signal component, and if there is no flaw in the center of the slab, the instantaneous value of the scanning output signal and the The differences between the average value and the average value are all within the specified value, so the average calculation circuit 12 uses
The average value within the period will be calculated. This average value and the stored contents of the multiplex storage device 11 at the center T ₀ of the n period are added to the subtraction circuit 17 . If there is no flaw signal, the output of the subtraction circuit 17 will be at or near the atmosphere.

If there is a flaw in the central part of the slab, for example, if a scanning output signal including flaw signals 51 to 54 is obtained as shown in FIG. Therefore, the defect signal component judgment circuit 14 adds the judgment result that is not within the specified value to the switching control circuit 15 and stores it in correspondence with the stored contents of the instantaneous value in the multiple storage device 11. , instead of the instantaneous value greater than the specified value, the average value via the average interval selection circuit 13 is added to the average calculation circuit 12 to calculate the average value for n periods.
Since such calculations are performed on the scanning output signals input as time passes, the average value output follows the gradual changes in the background signal component shown in analog form, as shown by the dotted line 55.

Note that if the cycle of change is shorter than the average interval (an interval corresponding to n cycles), it may become as indicated by 55', for example. Furthermore, a chain line 56 shows an example in which a background signal component is obtained by the conventional example, and it can be seen that the fidelity is significantly inferior to that of the background signal component indicated by a dotted line 55 obtained by the present invention.

In the subtraction circuit 17, the background signal component (the average value output of k bits of the output of the average section selection circuit 13) and the scanning output signal (the center of n cycles of the multiplex storage device 11) are used.
(instantaneous value of k bits at _T0 ) is calculated, and a flaw signal shown in analog form in FIG. 5b is extracted. From this flaw signal, a positive high-temperature flaw signal and a negative low-temperature flaw signal are separated. In that case, it is possible to separate based on the atmosphere, but the shaded part is cut off and a part of the positive polarity flaw signal 54 is lost and does not indicate the true level. Separate the positive polarity flaw signal based on the value (-E), and separate the negative polarity flaw signal based on an appropriate positive value (+E), and remove the DC component through a digital high-pass filter. It outputs a high-temperature flaw signal and a low-temperature flaw signal, and FIG. 5c shows the high-temperature flaw signal in analog form.

Next, processing of the scanning output signal at the end of the slab will be described with reference to FIGS. 6 and 7. Figure 6 shows the rising part of the scanning output signal, and the horizontal sides of the squares 61 to 66 are wide average intervals;
The vertical side is the specified value mentioned above, the black circle in the center and the short horizontal line are the average value and the narrow average interval, the 〇 and × marks indicate the judgment results of each instantaneous value within the average interval, the 〇 mark is within the specified value,
The x mark indicates a determination result outside the specified value, 67 is a wide average section signal, 68 is a slab width signal, and 69 is a wide average section switching signal.

Since the scanning output signals other than the slab width are at a substantially constant low level, all determination results in the flaw signal component determination circuit 14 are 0, as shown in 61. In 62, the judgment result of the first instantaneous value becomes ×, and in the rising portion of the scanning output signal, × increases sequentially from the beginning as in 63 and 64, and in 65, the first instantaneous value becomes ×. Since the value is within the specified value with respect to the average value, it is 0, and at 66, it shifts to a flat portion, so all the values are 0.

In the switching control circuit 15, the judgment output of the defect signal component judgment circuit 14 is accumulated, and the wide average interval signal 67 is set to "0" due to the x at the beginning, and all When it becomes 0, the wide average section signal 67 is set to "1". Further, when the wide average section signal 67 becomes "1" after the slab width signal 68 becomes "1", the wide average section switching signal 69 becomes "1" and remains "1" until the slab width signal 68 becomes "0". ” will continue. This wide average section switching signal 69 is generated by setting a flip-flop under the AND condition of the slab width signal 68 and the wide average section signal 67, and resetting it when the slab width signal 68 is "0", and using the set output. can be formed.

The average section selection circuit 13 selects the average value of the narrow average section because when the slab width signal 68 is "0", the wide average section switching signal 69 is "0" even if the wide average section signal 67 is "1". Average calculation circuit 1 that calculates
6 is selected, and even if the slab width signal 68 becomes "1", if the wide average section signal 67 is "0", the wide average section switching signal 69 is also "0", so the average of the narrow average section When the output of the average calculation circuit 16 that calculates the value is selected and the wide average section signal 67 becomes "1", the wide average section switching signal 69 changes to the slab width signal 68.
is "1" until it becomes "0", so that the output of the average calculation circuit 12 that calculates the average value of the wide average interval is selected.

Therefore, in the part where the signal level suddenly changes at the rising edge of the scanning output signal, the average value of the narrow average interval is output, and the background signal component follows the rising edge of the scanning output signal without causing any overshoot. It will be output as Furthermore, when transitioning from a rising edge to a flat portion, the average value of the wide average section by the average arithmetic circuit 12 and the average value of the narrow average section by the average arithmetic circuit 16 are approximately equal, so that a smooth output waveform can be obtained.

In this way, since it is possible to obtain a background signal component that almost faithfully follows the rising edge of the scanning output signal, it is possible to reliably extract flaw signals near the edges of the slab.

Figure 7 shows the falling part of the scanning output signal, and in 71, since it is a flat part, the judgment results are all 0, but in 72 and 73, the × increases sequentially from the beginning. do. Therefore, the wide average section signal 67 becomes "0" due to the x at the beginning, but the slab width signal 68 and the wide average section switching signal 6
Since 9 is "1", the output of the average calculation circuit 12 is selected. Then, when the slab width signal 68 becomes "0", the wide average section switching signal 69
When becomes "0", the output of the average calculation circuit 16 is selected and the average value of the narrow average interval is output, so in the case of the average value of the wide average interval, it becomes as shown in the dotted line, but when it becomes sharp as shown in the solid line, It can be output as a background signal component that follows the falling edge.

FIG. 8 is a block diagram of an embodiment of the multiple storage device and the average calculation circuit of FIG.
2h is a changeover switch, 83a to 83d, 84a,
84b, 85, 87a-87d, 88a, 88
b, 89 is a full adder, and 86 is a shift register. In this embodiment, the average interval of the scanning output signal is 64
The scanning output signal is obtained by converting the instantaneous value at the sampling point into a k-bit digital signal and adding it to the shift register 81 as described above. . Since the shift register 81 calculates the average value for 64 sampling points, it is sufficient to have 64 k-bit memories, but in this embodiment, an adding means as described later is used. By adopting k bits from 0 to 5758
It is sufficient to have 1 memory. Also, 0, 8, 16, 24, 33, 41, 49, 57 of shift register 81
The contents of No. 32 are applied to the changeover switches 82a to 82h, and the contents of No. 32 are added to the subtraction circuit 17 as the instantaneous value of the center _T0 of the n period.

The changeover switches 82a to 82h are the changeover control circuit 1.
The full adder 8
This is in addition to 3a-83d.

Full adder 83a to 83d, 84a, 84b,
85, 87a-87d, 88a, 88b, 89
is a full adder with two inputs of k bits each, but by assuming that the output is shifted to the upper side by k bits excluding the minimum value bit (LSB), that is, by 1 bit, the value is 1/2 of the addition result. is added to the next stage. Therefore, full adders 83a to 83
The addition outputs by d, 84a, 84b, 85 are 0, 8, 16, 24, 33, 41,
This is 1/8 of the sum of the eight outputs No. 49 and No. 57, that is, the average value of the eight outputs.

The output of the full adder 85 is added to a shift register 86, and the eight outputs are stored by sequentially shifting to numbers A to H, and these eight outputs are added to the full adders 87a to 87d. full adder 8
The addition outputs from 7a to 87d, 88a, 88b, and 89 are also 1/8 of the sum of the eight outputs numbered A to H of the shift register 86, that is, the average value of the eight outputs.
In the end, the output of Full Adder 89 is the sum of 64 outputs.
The average value of 1/64, that is, 64 cycles is applied to the average section selection circuit 13.

Assuming that the scanning output signal shown in FIG. 9 is sampled according to the clock and converted into a digital signal, at time _t0 , among clock numbers 1 to 64, clock numbers 65, 57, 49, 41, 32, twenty four,
The digital signals of the instantaneous values of the scanning output signals corresponding to 0, 8, 16, 8 of the shift register 81 are
Output from numbers 24, 33, 41, 49, and 57. In the full adders 83a to 83h, 0 and 8, 16 and 24, 33 and 41, 49 and 57 of the shift register 81, respectively.
The outputs of each number are added, the average value of each two outputs is added to the next full adder 84a, 84b, the average value output from each full adder 84a, 84b is added to the full adder 85, and the average value output is shifted. is added to register 86.

At time t _-1 one clock ago, the instantaneous digital signals of the scanning output signals corresponding to clock numbers 64, 56, 48, 40, 31, 23, 15, and 7 are transferred to 0 and 8 of the shift register 81. , 16, 24, 33, 41, 49, 57
The average value of the eight outputs is added from the full adder 85 to the shift register 86. Similarly, at time t _-7 , the clock number is
Digital signals of the instantaneous values of the scanning output signals corresponding to 58, 50, 42, 33, 25, 17, 9, and 1 are added from the shift register 81 to the full adders 83a to 83d, and the average value of the eight outputs is added to the shift register 81. Added to 86. Therefore, the shift register 86 has t ₀
Eight average values at ~t _-7 are accumulated.

Since the eight stored contents of the shift register 86 are added by full adders 87a to 87d, 88a, 88b, and 89 and the average value is output, this corresponds to clock number 33 among clock numbers 1 to 65. This means that the average value of 64 digital signals, excluding the instantaneous value digital signals, has been determined. Note that the center T ₀ of the 64 cycles is clock number 32, 33.
However, as mentioned above, since the average value of numbers 1 to 65 is taken, the center _T0 is number 33, so that the instantaneous value corresponding to clock number 33 can be added to the subtraction circuit 17. Thereby, when the instantaneous value corresponding to clock number 33 indicates the maximum value or minimum value of the scanning output signal, that value is not used for calculating the average value, so there is an advantage that it becomes close to the true average value.

FIG. 10 shows the clock numbers at the output point of the shift register 81 from time t ₂ to t _-7 , and A to H on the horizontal line indicate the clock numbers at the output point of the shift register 81 from time t ₀ to t ₂ . This indicates that the contents of A to H are stored as the average value of the output points of the shift register 81 at t ₂ to t ₀ to t _-7 immediately above. That is, G of the shift register 86 at t ₀
clock numbers 2, 10, 18 at time t _-6 ,
This indicates that the average value of instantaneous values corresponding to 26, 35, 43, 51, and 59 is stored, and this content will be shifted to H at time _t1 .

In the above explanation, the instantaneous value of the scanning output signal is within the specified value with respect to the average value, and the average value is calculated using the output of the shift register 81. If a judgment signal indicating that the value is not within the value is obtained, when the instantaneous value is output from the shift register 81,
Instead of the instantaneous value, the average value from the average interval selection circuit 13 is selected by the changeover switch and added to the full adder.

FIG. 11 is a block diagram of the main part when calculating the average value of 64 outputs from the multiple storage device using 63 full adders A1 to A63. Full adder A1~A3
2, and add it to the next stage full adders A33 to A48, excluding the least bit (LSB) as described above,
Thereafter, the average value of 64 instantaneous values is outputted from the full adder A63 in the same manner. This configuration requires 63 full adders, whereas the embodiment shown in FIG. 8 requires only 14 full adders, making the previously described embodiment economical.

Also, using only one full adder, add the contents of shift registers 0 and 1 that store i instantaneous values, add the addition output and the contents of shift register 2, and do the same in the same way. Find the addition result of 1/i
It is possible to calculate the average value by Therefore, there is a drawback that a full adder with a large number of bits must be used. In addition, i switching switches are required to switch between the instantaneous value and the average value based on the judgment results of the instantaneous values and add and average them, and even if one full adder is sufficient, overall it is impractical. becomes.

On the other hand, in the embodiment shown in FIG. 8, the calculation time is almost the same as that shown in FIG. 11, and there is an advantage that the number of full adders and the number of changeover switches can be significantly reduced.

Further, in the embodiment described above, the case where the means for calculating the average value of the wide average interval is configured using a full adder has been explained, but the average calculation circuit 16 as the means for calculating the average value of the narrow average interval can also be configured. , is configured by a full adder, and in this case, all you have to do is find the average value of, for example, 16 consecutive outputs centering on number 32 of the shift register 81.
Can be configured with 7 full adders. In that case, average calculation circuit 1 that calculates the average value of the wide average interval
Since the calculation time is different from that in step 2, it is preferable to provide a delay means such as a shift register to match the time relationship of the average value output.

As explained above, the present invention converts an analog scanning output signal into a digital signal, calculates the background signal component, and calculates the difference between the background signal component and the digital scanning output signal to extract a flaw signal. The average value of the wide average interval is the instantaneous value of the scanning output signal when it is not within the specified value with respect to the average value of the immediately preceding wide average interval or narrow average interval. Instead, it is determined using the value used for calculating the average value as the average value selected just before or the instantaneous value one cycle before, so it is possible to obtain a background signal component that is not affected by the flaw signal. Furthermore, since the average value of the narrow average interval is used near the rise or fall of the scanning output signal, it is possible to obtain a background signal component that faithfully follows even a steep rise or fall. Therefore, since the background signal component can be accurately obtained for defects at the edges of objects, they can be detected reliably.

In addition, by configuring the average calculation circuit for calculating the average value of the wide average interval using full adders and shift registers, high-speed calculation is possible with a small number of full adders, which has the advantage of being an economical configuration. Since it performs digital signal processing, it has a configuration that is not affected by noise and the like and can be easily integrated into an integrated circuit.

The present invention can be applied not only to the detection of flaws on the surface of slabs, but also to the detection of flaws on the surface of other objects, and can be applied not only to the detection of scanning output signals from an infrared line scanner, but also to the detection of scanning output signals from, for example, a television camera. It can also be applied in cases where

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a means for detecting flaws on the slab surface, Figs. 2 a to c are explanatory diagrams of examples of scanning output signals, slab width signals, and synchronization signals, and Figs. 3 a to e are illustrations of conventional flaw detection operations. FIG. 4 is a block diagram of an embodiment of the present invention; FIGS. 5 a to c, FIGS. 6 and 7 are explanatory diagrams of the operation of the flat portion, rising portion, and falling portion of the scanning output signal; FIG. 8 is a block diagram of an embodiment of the multiple storage device and the average calculation circuit of the present invention, FIG. 9 is an explanatory diagram of the relationship between the scanning output signal, the clock number, and the output of the shift register, and FIG. 10 is the shift register. FIG. 11 is a block diagram of an average calculation circuit composed only of full adders. 11 is a multiple storage device, 12 and 16 are average calculation circuits, 13 is an average section selection circuit, 14 is a flaw signal component determination circuit, 15 is a switching control circuit, 17 is a subtraction circuit, 18 and 20 are separation circuits, 19, 21 is a flaw signal output circuit, 22 is a delay circuit, 81 is a shift register, 82a to 82h are changeover switches, 83a to 8
3d, 84a, 84b, 85, 87a-87d,
88a, 88b, 89 are full adders, and 86 is a shift register.

Claims (1)

[Scope of Claims] 1. In a method of extracting a background signal component from a scanning output signal of an object surface and determining a difference between the background signal component and the scanning output signal to extract a flaw signal, the scanning output signal a multiplex storage device into which an instantaneous value converted into a digital signal is input, and sequentially stores a plurality of the digital signals over a plurality of sampling periods (hereinafter simply referred to as periods); and the scanning data stored in the multiplex storage device. means for calculating the average value of a plurality of digital signals corresponding to instantaneous values at each sampling point in an interval over a predetermined plurality of periods of the output signal (hereinafter referred to as wide average interval); an average of a plurality of digital signals stored in the multiplex storage device corresponding to instantaneous values at each sampling point in an interval over a predetermined plurality of periods less than the wide average interval centered at the center (hereinafter referred to as narrow average interval); and selecting means for selecting one of the outputs of the means for determining the average value and outputting it as the background signal component, and the means for determining the average value of the wide average section includes the means for determining the average value of the wide average section. When the instantaneous value of the scanning input signal input to the storage device is not within a specified value with respect to the immediately preceding selected average value, the selected average value or one period before it is substituted for the instantaneous value. It has a configuration in which the average value of a wide average interval is calculated using a multi-stage full adder and a shift register provided in an intermediate stage, using the value used for calculating the average value as the instantaneous value of the scan output signal, In the vicinity, the selection means selects the output of the means for calculating the average value of the narrow average interval, and in the flat part of the scanning output signal, selects the output for calculating the average value of the wide average interval. , a flaw detection digital signal processing method characterized in that the output of the selection means is used as a background signal component and the difference between it and an instantaneous value corresponding to the center of a wide average section of the digital signal stored in the multiple storage device is determined. .