JPS5930218B2 - Flaw detection signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flaw detection signal processing device for removing signals other than flaws such as scale and water droplets in a method for detecting flaws on the surface of an object such as a slab.

If flaws exist on the surface of the slab, the steel plate formed by rolling will have flaws that spread in the rolling direction, degrading the quality of the steel plate.

Therefore, it is necessary to detect flaws on the surface of the slab and remove them using a flaw removing device such as a scarfure before rolling. As -91 of this flaw removing device, a structure can be adopted in which the flaw is melted and flattened using a gas burner. In order to detect the flaws on the surface of the slab as described above, for example, as shown in FIG. A configuration added to device 3 is being considered.

Note that 1a and Ib indicate flaws on the slab surface, and 2a indicates the instantaneous field of view of the infrared line scanner 2o. The scanning range of the infrared line scanner 2 is set to be wider than the width of the slab 1, and the slab 1 is transported in a direction perpendicular to the scanning direction, so the scanning speed must be selected in accordance with the transport speed. Accordingly, the entire surface of the slab 1 can be scanned.

The scanning output signal has a level corresponding to the temperature of the slab 1, and includes flaw signals with widths and levels corresponding to the flaws 1a and lb, and false flaw signals corresponding to scales, water droplets, and the like. 10 When the slab 1 is formed and transported, it is at a high temperature in a red-hot state, and the scanning output signal from the infrared line scanner 2 is at a level corresponding to the surface temperature. It will be as shown below.

That is, if there are no flaws on the surface of the slab 1, the waveform will be approximately flat as shown in the first period, and if there is a flaw, the waveform will be approximately flat in the second and third periods depending on the condition of the flaw. The waveform includes flaw signals as shown by 1, C, 2, and E. The period between the rising edge and the falling edge of the scanning output signal indicates the width of the slab 1, and the slab width signal shown in FIG. 2b is formed from the scanning output signal.

Further, scanning is performed in synchronization with the synchronization signal shown in FIG. 2c,
The high level section of this synchronization signal indicates the scanning range. The aforementioned scanning output signal, slab width signal and synchronization signal are applied from the infrared line scanner 2 to the signal processing device 3 to extract the flaw signal. Although various methods for extracting flaw signals have been proposed, no sufficient means has yet existed.

For example, there is known a method of extracting the flaw signal by passing the scanning output signal through a high-pass filter, taking advantage of the fact that the flaw signal contains a higher frequency component than the background signal component. In such a method, the output of the high-pass filter is obtained at the rising edge and falling edge of the scanning output signal, and it is impossible to separate and extract the flaw signal that exists near the rising edge and the falling edge of the scanning output signal. Also, since an output corresponding to a differential waveform is obtained for a wide flaw signal, it is not possible to accurately detect the size of the flaw and whether it is a high temperature flaw or a low temperature flaw.1-
) There are drawbacks. There is also known means for extracting the flaw signal by passing the scanning output signal through a low-pass filter to extract the background signal component from which the flaw signal has been removed, and determining the difference between this background signal component and the scanning output signal.

Even in this method, since the background signal component has a slower rise and fall than the rise and fall of the scanning output signal, it is difficult to extract the flaw signal included in the vicinity of the rise and fall of the scanning output signal. In addition, since the level of the background signal component fluctuates under the influence of the flaw signal, the flaw signal obtained by the difference will include a false flaw signal.
There was a drawback that it was not possible to separate the true flaw signal from the false flaw signal. Furthermore, in the forming process or rolling process of the slab 1, cooling water is used, and although most of the water droplets on the slab surface evaporate, some may remain and be transported to the scanning range of the infrared line scanner 2. many.

Since this water droplet has a lower temperature than the surface temperature of the slab 1, it is included in the scanning output signal as a low temperature flaw signal.
However, since this is not an actual flaw, it is necessary to remove it before detecting the flaw. The present invention provides water droplets as described above,
The purpose of this method is to remove false flaw signals similar to low-temperature flaw signals caused by scale, etc., so that only true flaw signals can be extracted.

Examples will be described in detail below. FIG. 3 is a block diagram for separating and extracting a high-temperature flaw signal and a low-temperature flaw signal from a scan output signal according to an embodiment of the present invention, and 10 is an input terminal 11 for a scan output signal from an infrared line scanner. 12 and 16 are average calculation circuits, 13 is an average section selection circuit, 14 is a defect signal component determination circuit, 15 is a switching control circuit, 17 is a subtraction circuit, 18,20
1 is a separation circuit, 19 and 21 are flaw signal output circuits including a high-pass filter and a detection circuit, 22 is a delay circuit that delays the synchronization signal in accordance with the signal processing delay time of each part, and 23 is an input terminal for the slab width signal. , 24 is a synchronization signal input terminal, 2
5 is a high temperature flaw signal output terminal, 26 is a low temperature flaw signal output terminal,
27 is a synchronization signal output terminal.

The multiple storage device 11 samples the scanning output signal at a period t, stores the sampled value over n periods,
It has a configuration that can simultaneously output the stored contents over n periods or less. For example, by a combination of n capacitors and switching elements, the instantaneous value is output through the switching element that switches sequentially every period t. is stored in a capacitor, or a configuration in which n delay elements with a delay time t are connected in series and the output of each delay element can be derived, or a charge transfer device (CCD) is used to sequentially shift and store the sampled values. In the case of digitalization, a configuration using a shift register or a random access memory can be adopted.

The average calculation circuit 12 adds n input signals and calculates 1/n
is calculated and outputs a moving average value of a wide average interval over n periods, and the n outputs of the multiplex storage device 11 and the output of the average interval selection circuit 13 are connected to the signal from the switching control circuit 15. Accordingly, the above-mentioned average value calculation is performed by selecting one as will be described in detail later. That is, as will be described later, if the difference between the scanning signal and the signal from the average section selection circuit 13 is within a specified value, the average calculation circuit 12 selects the signal from the multiple storage device 11.
The average (moving average) value for n periods is calculated from the n outputs of , and if it is not within the specified value, the average value from the average interval selection circuit 13 is used instead of the output of the multiplex storage device 11 corresponding to that point. to find the average value. This suppresses fluctuations in the average value (which becomes a background signal) due to large flaw signals. Moreover, the average calculation circuit 16
Among the outputs, m(m
＜(n) Add the outputs and perform the 1/total operation,
The moving average value of the narrow average interval over m periods is output. The flaw signal component determination circuit 14 compares the signal from the infrared line scanner applied to the manual terminal 10 and the average value output via the average section selection circuit 13, and determines whether the difference is within a specified value. Then, the determination result is applied to the switching control circuit 15.

The specified value indicates a range within which the influence of the difference on the average output is allowable. The switching control circuit 15 causes the average calculation circuit 12 to calculate an average value for the n outputs of the multiple storage device 11 when the judgment output of the flaw signal component judgment circuit 14 indicates that it is within a specified value, and when it is not within the specified value, Instead of the output of the multiplex storage device 11 corresponding to the input signal at that moment,
The average value output via the average interval selection circuit 13 is selected and added to the average calculation circuit 12. That is, if a determination result that is not within the specified value is obtained k times in a row, the multiple storage device 11
Instead of the latest k stored contents, the average value output via the average interval selection circuit 13 is added to the k average calculation circuit 12, and the (n-k) outputs of the multiple storage device 11 are It is added to the average calculation circuit 12, and the average value for n periods is calculated. Here, the average value output via the average interval selection circuit refers to the narrow average signal or wide average signal selected by the average interval selection circuit 13.

The switching control circuit 15 also includes a storage means for storing a plurality of latest judgment outputs from the flaw signal component judgment circuit 14.
It has a function of detecting the start and end of a sudden change according to the plurality of judgment outputs and controlling the average section selection circuit 13. The average section selection circuit 13 detects the slab width applied to the input terminal 23. According to the signal and the control signal from the switching control circuit 15, the average value output of the wide average section is output by the average calculation circuit 12 during the slab surface scanning period other than the rising and falling edges of the slab, and the average value output of the wide average section is output by the average calculation circuit 16 during periods other than the above. Select and output the average value output of the narrow average interval. The output of the average section selection circuit 13 indicates the background signal component excluding the flaw signal, and is sent to the subtraction circuit 17 in the multiple storage device 1.
The difference from the stored content corresponding to the center TO of n cycles of 1 is calculated.

That is, the difference between the average value over n periods or m periods and the instantaneous value at the center TO is determined. The specified value in the flaw signal component determination circuit 14 is set in consideration of fluctuations in the background signal component, and if there is no flaw in the center of the slab, the instantaneous value of the scanning output signal and the The differences from the average value are all within the specified value, so the average calculation circuit 12 uses the n outputs of the multiple storage device 11 to calculate the average value within n cycles.

This average value and the stored contents at the center TO of the n period of the multiple storage device 11 are added to the subtraction circuit 17. If there is no flaw signal, the output of the subtraction circuit 17 will be zero or near zero. Here, when the difference determined by the comparison in the defect signal component determination circuit is within the specified value range or not within the specified value, and the specified value has the following meaning.

In other words, the specified value means that when performing a moving average, if the difference between the input value and the previous average value exceeds that value, the background signal obtained by the average value including that input value is acceptable. This is a value that would cause an error greater than that of the actual value. The defect signal component determination circuit 14 calculates the difference between the input scanning signal and the average value output from the average section selection circuit 13, and determines whether the difference is within the above-mentioned specified value.

In other words, it is determined whether or not the input scanning signal, if used as it is for average calculation, is a signal that would cause an error greater than allowable in the background signal obtained as a result. When a part of the scanning output signal is as shown in FIG. 4a, high temperature flaw signals 41 and 42 and low temperature flaw signals 43 to 47
is not within the specified value centered on the previous average value, so the determination result is stored in the switching control circuit 15 in correspondence with the stored contents of the instantaneous value in the multiple storage device 11, Instead of the instantaneous value greater than the specified value, the average value via the average interval selection circuit 13 is added to the average calculation circuit 12 to calculate the average value for n periods.

Since such calculations are performed on the scanning output signals input as time passes, the average value output is indicated by the dotted line 48.
It will be as shown below. Since the above-mentioned average value output indicates the background signal component, the arithmetic circuit 17 calculates the difference between the background signal component and the scanning output signal (in this case, the storage content at the center TO of the n period of the multiplex storage device 11). is calculated, and the output shown in FIG. 4b is obtained.

The positive polarity signal of this output is separated by the separation circuit 18 and outputted from the flaw signal output circuit 19 as a high temperature flaw signal, and the negative polarity signal is separated by the separation circuit 20 and outputted from the flaw signal output circuit 21 as a low temperature flaw signal. Output. The signal processing in each block shown in the block diagram of FIG. 3, and the relationships, operations, and functions between the blocks have been described in detail above, and can be summarized as follows.

That is, the multiple storage device 11 sequentially stores scanning signals of the past n cycles, the average calculation circuit 12 calculates a wide average from the stored values, the average calculation circuit 16 similarly calculates a narrow average, and the average section selection circuit calculates a narrow average. 13 detects the rising and falling portions due to the slab from the signal from the switching control circuit 15 indicating a sudden change in the scanning signal and the slab width signal, and calculates a narrow average for these portions and a relatively flat portion in between. Output the wide average. The flaw signal component determination circuit 14 determines whether the instantaneous value of the scanning signal is within a specified value from the immediately preceding average value (output of the average interval selection circuit 13). The average value from the average interval selection circuit 13 is sent to the average calculation circuit 12 in place of the value stored in the multiple storage device 11 corresponding to the moment when the instantaneous value is not within the specified value. is used to obtain a wide average, and the average section selection circuit 13 is notified of the start and end of a sudden change in the scanning signal. As a result, the output of the average interval selection circuit 13 becomes a background signal, and the subtraction circuit 17
is subtracted from the scanning signal by , and a flaw signal is output.

This flaw signal is divided into positive and negative signals and separated into a high temperature flaw signal and a low temperature flaw signal. The positive polarity signal and the negative polarity signal can be separated based on 0V, but since the background signal component may not be in a completely ideal state, the positive polarity signal is separated based on -EV, Negative polarity signals are separated based on ten jo.

Next, when the DC component is removed through a high-pass filter, the negative polarity signal becomes, for example, as shown in FIG. 4c. This is a low-temperature flaw signal, which includes false flaw signals due to water droplets and scale, as described above. Signals due to water droplets or scale almost always have narrower pulse widths and are lower temperature than true low temperature flaw signals.

Therefore, it is possible to remove the false defect signal through a low-pass filter, but this would cause distortion and delay in the entire signal waveform.
There is a risk that errors will occur in subsequent signal processing. Therefore, the present invention eliminates the false flaw signal by utilizing the fact that the pulse width is narrower than that of the real flaw signal. FIG. 5 is a block diagram of an embodiment of the present invention, where 50 is an input terminal connected to the low-temperature flaw signal output terminal 26 mentioned above, and 51 is a low level when the amplitude of the negative polarity signal is above a certain level; 52 is a trigger circuit that outputs a trigger pulse when the determination signal changes from high level to low level; 53 is a trigger circuit that outputs a high level determination signal when the determination signal changes from low level to high level. Trigger circuit 54 is a counter that outputs a trigger pulse when
It counts down according to the clock, and when the count reaches zero, it outputs a BORO-1 signal.

Note that it is also possible to use a configuration in which the clock is up-counted by the trigger pulse and a carry-off signal is output at the count of N. Further, 55 is a counter control circuit, 56 is a multiple storage device including N storage elements such as a shift register,
57 is a trigger circuit that outputs a stop trigger pulse when the judgment signal delayed by the multiple storage device 56 changes from low level to high level; 58 is a stop trigger pulse that is set and controls the counter control circuit 55; 59 and 61 are gate circuits; 60 is a delay circuit;
62 is a clock generation circuit, and 63 is an output terminal. 6th
Figures a to t are operation explanatory diagrams, in which the signals a of each part in Figure
-t shows an example of a waveform corresponding to t.

When the signal a applied to the input terminal 50 is shown in FIG.
The amplitude of is determined and a determination signal b is output as shown in FIG. 6b. The trigger circuit 52 outputs a trigger pulse c as shown in FIG. 6c at the falling edge of the determination signal b, and the trigger circuit 53 outputs a trigger valve d as shown in FIG. 6d at the rising edge of the determination signal b. In signal a, narrow signals Sl, S3 to S5 . S7 to SlO are false flaw signals due to water droplets and scale, and a wide signal S2. If S6 is a true low-temperature defect signal, the counter 54 that is preset by the trigger pulse c and counts down by the clock is controlled by the counter control circuit 5 by the trigger pulse d or the boro-1 signal f.
5, the count content e becomes as shown in FIG. 6e, and the false defect signals Sl,
For S3 to S5 and S7 to SlO, the counter is set so that it is not counted down to zero, and the true low-temperature defect signal S
For ZS6, the count is down to zero, and a BORO-1 signal f is outputted as shown in FIG. 6f.

Also, the multiple storage device 56 stores the judgment signal b, and the counter 5
It is output after a delay time corresponding to the time for counting down to zero after 4 is preset, and the delayed judgment signal g is as shown in FIG. 6g.

The trigger circuit 57 outputs a stop trigger pulse h as shown in FIG. 6h at the rising edge of the determination signal g. Since the flip-flop 58 is set by the flop signal f applied via the counter control circuit 55 and reset by the stop trigger pulse h, its set output signal 1 becomes as shown in FIG. 59 as a control signal. Output signal j of gate circuit 59
is at a high level when the set output signal 1 of the flip-flop 58 is at a high level, and at a level according to the judgment signal g when the set output signal 1 is at a low level.
It is added to the gate circuit 61 as shown in FIG.

The delay circuit 60 is for matching the phase of the input signal a with the phase of the signal j, and the delayed input signal k is applied to the gate circuit 61 as shown in FIG. 6k.

Since this gate circuit 61 allows the delayed input signal k to pass when the signal j is at a high level and blocks it when it is at a low level, the output signal t of the gate circuit 61 is free from false defects, as shown in FIG. The signal is removed and a true low temperature flaw signal S2
, S6.

This true low-temperature flaw signal is subjected to subsequent signal processing to determine the size and position of the flaw, and based on the results, the flaws on the slab surface are removed. When a gas burner is used as the removal means as described above, the flaw can be removed by automating local melting in accordance with the size of the flaw at the determined position. The same applies to high temperature defects. As explained above, in the present invention, since the width of the false flaw signal due to water droplets, scale, etc. included in the low-temperature flaw signal is narrower than the width of the true low-temperature flaw signal, the width of the judgment signal whose amplitude is determined at a constant level is A counter determines whether the width is equal to or greater than a predetermined width, and only the signal determined to be equal to or greater than the predetermined width is allowed to pass.
This method removes false flaw signals of a predetermined width or less, and can output only true low-temperature flaw signals without distorting the waveform of the low-temperature flaw signal extracted from the scanning output signal.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the means for detecting flaws on the slab surface, Figure 2 a-
c is an explanatory diagram of an example of a scanning output signal, a slab width signal, and a synchronizing signal; FIG. 3 is a block diagram for extracting a high temperature flaw signal and a low temperature flaw signal from the scanning output signal of the embodiment of the present invention;
4a to 4c are diagrams for explaining the operation of FIG. FIG. 5 is an explanatory diagram of an example of signal waveforms at each part in FIG. 5; 11 and 56 are multiple storage devices, 12 and 16 are average calculation circuits, 13 is an average section selection circuit, 14 is a flaw signal component determination circuit, 15 is a switching control circuit, 17 is a subtraction circuit, 18 and 20 are separation circuits, 19 , 21 is a flaw signal output circuit, 22 is a delay circuit, 51 is an amplitude determination circuit, 52, 53, 57 are trigger circuits, 54 is a counter, 55 is a counter control circuit, 58 is a flip-flop, 59, 61 are gate circuits, 60 is a delay circuit, and 62 is a clock generation circuit.

Claims (1)

[Claims] 1. Extract a background signal component from the scanning output signal of the object surface, find the difference between the background signal component and the scanning output signal to extract a flaw signal, and separate the flaw signal into a high temperature flaw signal and a low temperature flaw signal. In the flaw detection signal processing device, there is provided an amplitude determination circuit for the low temperature flaw signal, a counter for determining whether the width of the signal determined by the amplitude determination circuit is greater than or equal to a predetermined width, and a What is claimed is: 1. A flaw detection signal processing device comprising a gate circuit that allows only a signal passing through, and which removes narrow false flaw signals caused by water droplets, scale, etc., and outputs only a true low-temperature flaw signal from the gate circuit.