JPS614255A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS614255A
JPS614255A JP12446084A JP12446084A JPS614255A JP S614255 A JPS614255 A JP S614255A JP 12446084 A JP12446084 A JP 12446084A JP 12446084 A JP12446084 A JP 12446084A JP S614255 A JPS614255 A JP S614255A
Authority
JP
Japan
Prior art keywords
chip
heat
heat sink
chip carriers
fiber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12446084A
Other languages
Japanese (ja)
Other versions
JPH0326543B2 (en
Inventor
Toshihiko Watari
渡里 俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12446084A priority Critical patent/JPS614255A/en
Publication of JPS614255A publication Critical patent/JPS614255A/en
Publication of JPH0326543B2 publication Critical patent/JPH0326543B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To improve heat conducting characteristics from an IC chip to a heat sink, by inserting heat connectors, in which heat conducting fiber is implanted in resilient sheets, between chip carriers and the heat sink under the compressed state. CONSTITUTION:Many chip carriers 3 are connected and arranged on a wiring substrate 1 through a solder bonding part 2. Heat connectors 5, in which heat conducting fiber is implanted in resilient sheets, are inserted between the chip carriers 3 and a heat sink 4 under the state the heat conducting fiber is compressed to the degree the fiber is bent. The heat conductor 5 is formed by embedding many beryllium copper thin wires 18, which are the conducting fiber, in silicone rubber 17, which is a relatively soft insulating material. The connector form an excellent heat conducting path between a chip carrier cap 16 and the heat sink 4. Since the heat sink 4 and the chip carriers 3 are not fixed, stress of expansion and contraction due to temperature difference is not applied between the chip carriers 3 and the wiring substrate 1. Therefore, the connection of the chip carriers 3 and the wiring substrate 1 can be ensured.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は高密度集積回路・母ツケージに関し、特に複数
個のICチップを高密度に搭載するのに適、した集積回
路ノ9ツケージに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a high-density integrated circuit/mother package, and particularly to an integrated circuit package suitable for mounting a plurality of IC chips at high density.

〔従来技術〕[Prior art]

近年のコンピュータ紘高性能化、高密度化に向って著し
い改善がなされている。これは主としてLCチッゾの高
集積化技術の進歩に負うところが大きく、高速論理回路
ICチップの集積度は、数年前には数百ゲート/チップ
であったものが、最近では1000〜2000ゲート/
チツゾのものまで実現されるにいたっている。ICチッ
プの高集積化は、シリコン基板上に能動受動素子を高密
度に形成し、かつこれらの素子間を微細な配線で結合で
きる微細加工技術の改良と共に、これらの素子の形成プ
ロセス技術の改良によるf−)、りたり消費電力の低減
によって達成されていると言える。
In recent years, significant improvements have been made toward higher performance and higher density computers. This is largely due to the progress of LC Chizzo's high integration technology, and the density of high-speed logic circuit IC chips has increased from a few hundred gates/chip a few years ago to 1000-2000 gates/chip in recent years.
Even Chituzo's work has come to fruition. High integration of IC chips requires improvements in microfabrication technology that allows active and passive elements to be formed at high density on a silicon substrate and connections between these elements with fine wiring, as well as improvements in process technology for forming these elements. f-), it can be said that this has been achieved by reducing power consumption.

しかしながらこのような高集積化の実現に伴い。However, with the realization of such high integration.

高速度論理回路チップあたシの消費電力は、従来に比べ
むしろ上昇する傾向にある。この理由は。
The power consumption of high-speed logic circuit chips tends to be higher than in the past. The reason for this is.

ダート回路の高密度化によシアダート回路間の接続配線
長を可能な限シ短縮して配線fよって消耗する信号伝搬
スピード及び駆動エネルギーを最小にとどめようとする
設計技術者の当然の試みによるものである。従ってこれ
らのICチップを実装するパッケージ構造においては、
高電力のICチップが発生する熱を如何に効果的に放散
させるかが重要な技術課題となる。このような技術の1
例は特開昭57−134953号公報においてみること
ができる。すなわちその実施例によれば、ICチップの
発生する熱をファイバーガラスと熱硬化性プラスチック
樹脂からなるプリフォームを介してヒートシンクに伝達
し放散する方法である。しかしながら、このようなプラ
スチック樹脂の熱伝導特性は0.005 w/インチ・
℃のオーダであり。
This was a natural attempt by design engineers to minimize the signal propagation speed and drive energy consumed by the wiring f by shortening the length of the connection wiring between the shear dirt circuits as much as possible by increasing the density of the dirt circuits. It is. Therefore, in the package structure in which these IC chips are mounted,
An important technical issue is how to effectively dissipate the heat generated by high-power IC chips. One of these technologies
An example can be found in JP-A-57-134953. That is, according to the embodiment, the heat generated by the IC chip is transmitted to the heat sink through a preform made of fiber glass and thermosetting plastic resin, and is dissipated. However, the thermal conductivity of such plastic resins is 0.005 w/in.
It is on the order of °C.

無機材料に比べると−1柘悪い。例えばアルミナのよう
な金属酸化物の熱伝導率は0.7W/インチ・℃のオー
ダであり、銅の如き金属の場合は10W/インチ・℃の
オーダである。したがってこのような構造の場合、プラ
スチック樹脂の熱伝導特性によってICチップの冷却能
力の限界が決定されることになり、ICチップの側熱特
性およびヒートシンクの温度差による伸縮の機械的スト
レスの両面からみて、よシ高消費電力すなわち高発熱の
ICチップを搭載することが困難となる。
-1 point worse than inorganic materials. For example, the thermal conductivity of metal oxides such as alumina is on the order of 0.7 W/in.°C, and for metals such as copper is on the order of 10 W/in.°C. Therefore, in the case of such a structure, the limit of the cooling capacity of the IC chip is determined by the thermal conductivity characteristics of the plastic resin, and the limit of the cooling capacity of the IC chip is determined from both the side thermal characteristics of the IC chip and the mechanical stress of expansion and contraction due to the temperature difference of the heat sink. This makes it difficult to mount an IC chip that consumes a lot of power, that is, generates a lot of heat.

〔発明の目的〕[Purpose of the invention]

したがって9本発明の目的は、ICチップからヒートシ
ンクまでの熱伝導特性を向上させ、かつICチップの搭
載された配線基板とヒートシンクの温度差による熱伸縮
の機械的ストレスをも緩和させることがそきる集積回路
・母ソケージを提供することにある。
Therefore, it is an object of the present invention to improve the heat conduction characteristics from the IC chip to the heat sink, and to also alleviate the mechanical stress caused by thermal expansion and contraction due to the temperature difference between the wiring board on which the IC chip is mounted and the heat sink. Our goal is to provide integrated circuits and motherboards.

〔発明の構成〕[Structure of the invention]

本発明によれば、内部上面にICチップを接着して収容
するチップキャリアを配線基板上に複数個設け、上部に
ヒートシンクを配置して前記ICチップからの発熱を放
散するようにした・ぐツケージ構造において、前記チッ
プキャリアとヒートシンクの間に2弾力性を持つシート
に導熱性の繊維を植え込んだ構成の熱コネクタが加圧状
態で挿入されていることを特徴とする集積回路パッケー
ジが得られる。
According to the present invention, a plurality of chip carriers for accommodating IC chips bonded to the inner upper surface thereof are provided on a wiring board, and a heat sink is arranged on the upper part to dissipate heat generated from the IC chips. In the structure, an integrated circuit package is obtained, characterized in that a thermal connector having a structure in which thermally conductive fibers are embedded in a sheet having elasticity is inserted between the chip carrier and the heat sink under pressure.

次に図面を参照して詳細に説明する。Next, a detailed explanation will be given with reference to the drawings.

以下余白 〔実施例〕 第1図は本発明の一実施例の構成を示す図であり、配線
基板1の上には平田接着部2を介して多数のチップキャ
リア3が接続配置されておシ、これらのチップキャリア
3とヒートシンク4との間には弾力性シートに導熱性樽
維を植え込んだ構造の熱コネクタ5が図にあられして々
いが導熱性繊維が若干折れ曲る程度に押圧された状態で
挿入されている。
The following margins [Example] FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, in which a large number of chip carriers 3 are connected and arranged on a wiring board 1 via Hirata adhesive parts 2. Between the chip carrier 3 and the heat sink 4, there is a thermal connector 5 having a structure in which thermally conductive barrel fibers are embedded in an elastic sheet, as shown in the figure, and the thermal connector 5 is pressed to the extent that the thermally conductive fibers are slightly bent. It has been inserted in the same state.

第2図は第1図の一部を拡大して示した図であって、チ
ップキャリア3において、ICチップ11は先に述べた
ように高集積度の発熱量の大きいチップであシ、そのI
Cリード12はゼンデイング/−Pツド13を介してチ
ップキャリアサブストレー、 ト14に接続され、かつ
本体は熱伝導性のチップ接着剤15(例えば銀入シエデ
キシ)によってチップキャリアキャップ16に接着され
ている。チップキャリアキャップ16は特に熱伝導特性
の良好な材料例えばべIJ IJア(Bed)が用いら
れている。
FIG. 2 is a partially enlarged view of FIG. I
The C lead 12 is connected to a chip carrier substrate 14 via a bending/-P lead 13, and the main body is bonded to a chip carrier cap 16 with a thermally conductive chip adhesive 15 (for example, silver-filled adhesive). There is. The chip carrier cap 16 is made of a material having particularly good thermal conductivity, such as Bed.

チップキャリアキャップ16とヒートシンク4との間に
挿入されだ熱コネクタ5は比較的柔軟な絶縁物であるシ
リコンラバー17に導熱繊維であるベリリウム銅細線1
8を多数理め込んで形成されていて、チップキャリアキ
ャップ16とヒート7ンク4の間の良好な熱伝導経路を
構成する。図でベリリウム銅細線18は成るものは屈曲
し成るものは曲線のままであるが、これは単に種々の状
態があることを模型的に示したにすぎず、解放すればす
べての細線はほぼ垂直に向くものである。従ってICチ
ップ11が発生した熱はチップ接着剤15、チップキャ
リアキャップ16.熱コネクタ5、ヒートシンク4の経
路で放散される。
The thermal connector 5 inserted between the chip carrier cap 16 and the heat sink 4 is made of silicon rubber 17, which is a relatively flexible insulator, and beryllium copper thin wire 1, which is a thermal conductive fiber.
8, and constitutes a good heat conduction path between the chip carrier cap 16 and the heat tank 4. In the figure, some of the beryllium copper thin wires 18 are bent and others remain curved, but this is merely a model to show that there are various states; when released, all the thin wires become almost vertical. It is suitable for Therefore, the heat generated by the IC chip 11 is transferred to the chip adhesive 15, the chip carrier cap 16. The heat is dissipated through the path of the heat connector 5 and the heat sink 4.

一方ICチップ11への給電及び入出力信号の供給や取
シ出しは、 I ’Cリード12.ピンディングツやラ
ド13.チツプキヤリアサブストレート14内の配線(
図示せず)、チップキャリア端子19゜半田接着剤、配
線基板端子21(19,20,21で平田接触部2を形
成する)および配線基板1内の電源配線と信号配線を順
次接続した系統で行なわれる。これによシICチップ1
1は他のチップキャリア内のICチップとの信号のやり
とりが可能となる。
On the other hand, power is supplied to the IC chip 11 and input/output signals are supplied and taken out through the I'C lead 12. Pindingtu and Rad 13. Wiring inside chip carrier substrate 14 (
(not shown), chip carrier terminal 19° solder adhesive, wiring board terminal 21 (19, 20, 21 form Hirata contact part 2), and power wiring and signal wiring in wiring board 1 are connected in sequence. It is done. This IC chip 1
1 enables signal exchange with IC chips in other chip carriers.

ここで第1図に戻って2本発明の集積回路パフケージは
前記のよう々構成のICチップ11を配線基板3上に高
密度に実装したものであるが、熱コネクタ5はこのよう
表高密度ノやノケージにおいて非常に優れた特徴を発揮
するものである。すなわち、第1図に示すように配線基
板1上に複数個のチップキャリア3を配し、これらの発
生する熱を共通のヒートシンク4によって放散させよう
とする場合、ヒートシンク4をチップキャリア3に固着
してしまうと、配線基板1とヒートシンク4との熱膨張
係数の差によシチノデキャリア3と配線基板1の間の平
田接着部2にすシはがし力が働き、接着がはがれてしま
うおそれがあるが2本発明のように熱コネクタ5を介し
てチップキャリア3とヒートシンク4を接続した場合は
、ヒートシ、    714′!″f y 7”e −
y !J 7°&dE1i1!ltl[In7>Ip 
Returning to FIG. 1, the integrated circuit puff cage of the present invention has the IC chips 11 configured as described above mounted on the wiring board 3 at high density. It exhibits very excellent characteristics in no and no cages. That is, when a plurality of chip carriers 3 are arranged on a wiring board 1 as shown in FIG. 1 and the heat generated by these chips is to be dissipated by a common heat sink 4, it is necessary to fix the heat sink 4 to the chip carrier 3. If this happens, the difference in thermal expansion coefficient between the wiring board 1 and the heat sink 4 will cause a peeling force to act on the Hirata adhesive part 2 between the cytinode carrier 3 and the wiring board 1, and there is a risk that the adhesive will peel off. However, when the chip carrier 3 and the heat sink 4 are connected via the thermal connector 5 as in the present invention, the heat sink 714'! "f y 7"e -
Y! J 7°&dE1i1! ltl[In7>Ip
.

チップキャリア3と配線基板1との間にストレスが加わ
ることがなく、従ってチップキャリア3と配線基板1の
接続が確実に行なわれる。
No stress is applied between the chip carrier 3 and the wiring board 1, so that the connection between the chip carrier 3 and the wiring board 1 is ensured.

さらに熱コネクタ5をヒートシンク4とチップキャリア
2との間に挿入した場合、単に放熱経路の一部を形成す
るだけでなく、導熱性繊維の弾力性によりヒートシンク
4とチップキャリア3の間のギャップのバラツキを十分
に吸収し、配線基板1とヒートシンク4との間の熱膨張
によるチップキャリア3の位置ずれを充分に吸収するこ
とができる。
Furthermore, when the thermal connector 5 is inserted between the heat sink 4 and the chip carrier 2, it not only forms part of the heat dissipation path, but also reduces the gap between the heat sink 4 and the chip carrier 3 due to the elasticity of the heat conductive fibers. It is possible to sufficiently absorb variations and to sufficiently absorb displacement of the chip carrier 3 due to thermal expansion between the wiring board 1 and the heat sink 4.

力お以上の説明において柔軟な絶縁基板および導熱性繊
維材としておのおの一例を上げて示したが、他の材料で
あってもよいことはいうまでも力い。又導熱性繊維はふ
つう長さ1.5〜3mm直径0.2 an程度のものが
適当であるがこれに限定されるものではなく、要は繊維
が斜めに又は屈曲してほぼ全数がヒートシンク4とチッ
プキャリアキャップ16の両方に適度の圧力で接するよ
うにすればよい。
In the above explanation, examples have been given as the flexible insulating substrate and the heat conductive fiber material, but it goes without saying that other materials may be used. In addition, it is appropriate that the heat conductive fibers have a length of 1.5 to 3 mm and a diameter of about 0.2 ann, but are not limited to this. and the chip carrier cap 16 with appropriate pressure.

〔発明の効果〕〔Effect of the invention〕

以上説明したように1本発明はチップキャリアキャップ
とヒートシンクとの間に熱コネクタを挿入した構造とす
ることにより、放熱特性の極めて良好な而も内部ストレ
スのない高密度集積回路パッケージを実現できる。
As explained above, the present invention has a structure in which a thermal connector is inserted between a chip carrier cap and a heat sink, thereby realizing a high-density integrated circuit package with extremely good heat dissipation characteristics and no internal stress.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例である集積回路t42ケージの
構成を示す断面図、第2図は第1図の一部を拡大して示
した図である。 記号の説明=1は配線基板、2は平田接着部。 3はチップキャリア、4はヒートシンク、5は熱コネク
タ、11はICチップ、16はチップキャリアキャップ
、17はシリコンラバー、18はベリリウム銅線をそれ
ぞれあられしている。 り 矛2図
FIG. 1 is a sectional view showing the structure of an integrated circuit T42 cage according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a part of FIG. 1. Explanation of symbols = 1 is the wiring board, 2 is the Hirata adhesive part. 3 is a chip carrier, 4 is a heat sink, 5 is a thermal connector, 11 is an IC chip, 16 is a chip carrier cap, 17 is silicon rubber, and 18 is a beryllium copper wire. Illustration of spear 2

Claims (1)

【特許請求の範囲】[Claims] 1、内部上面にICチップを接着して収容するチップキ
ャリアを配線基板上に複数個設け、上部にヒートシンク
を配置して前記ICチップからの発熱を放散するように
したパッケージ構造において、前記チップキャリアとヒ
ートシンクの間に、弾力性を持つシートに導熱性の繊維
を植え込んだ構成の熱コネクタが加圧状態で挿入されて
いることを特徴とする集積回路パッケージ。
1. In a package structure in which a plurality of chip carriers each having an IC chip adhered to and housed on an internal upper surface thereof are provided on a wiring board, and a heat sink is disposed on the upper part to dissipate heat generated from the IC chip, the chip carrier An integrated circuit package characterized in that a thermal connector made of an elastic sheet with thermally conductive fibers is inserted under pressure between a heat sink and a heat sink.
JP12446084A 1984-06-19 1984-06-19 Package for integrated circuit Granted JPS614255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12446084A JPS614255A (en) 1984-06-19 1984-06-19 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12446084A JPS614255A (en) 1984-06-19 1984-06-19 Package for integrated circuit

Publications (2)

Publication Number Publication Date
JPS614255A true JPS614255A (en) 1986-01-10
JPH0326543B2 JPH0326543B2 (en) 1991-04-11

Family

ID=14886066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12446084A Granted JPS614255A (en) 1984-06-19 1984-06-19 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS614255A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02501178A (en) * 1988-03-01 1990-04-19 ディジタル イクイプメント コーポレーション Method and apparatus for packaging and cooling integrated circuit chips
US5184211A (en) * 1988-03-01 1993-02-02 Digital Equipment Corporation Apparatus for packaging and cooling integrated circuit chips
USH1699H (en) * 1995-10-31 1997-12-02 The United States Of America As Represented By The Secretary Of The Navy Thermal bond system
US7608324B2 (en) 2001-05-30 2009-10-27 Honeywell International Inc. Interface materials and methods of production and use thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02501178A (en) * 1988-03-01 1990-04-19 ディジタル イクイプメント コーポレーション Method and apparatus for packaging and cooling integrated circuit chips
US5184211A (en) * 1988-03-01 1993-02-02 Digital Equipment Corporation Apparatus for packaging and cooling integrated circuit chips
USH1699H (en) * 1995-10-31 1997-12-02 The United States Of America As Represented By The Secretary Of The Navy Thermal bond system
US7608324B2 (en) 2001-05-30 2009-10-27 Honeywell International Inc. Interface materials and methods of production and use thereof

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