JPS6217871B2 - - Google Patents

Info

Publication number
JPS6217871B2
JPS6217871B2 JP3169181A JP3169181A JPS6217871B2 JP S6217871 B2 JPS6217871 B2 JP S6217871B2 JP 3169181 A JP3169181 A JP 3169181A JP 3169181 A JP3169181 A JP 3169181A JP S6217871 B2 JPS6217871 B2 JP S6217871B2
Authority
JP
Japan
Prior art keywords
chip
multilayer wiring
wiring board
chips
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3169181A
Other languages
Japanese (ja)
Other versions
JPS57147255A (en
Inventor
Toshihiko Watari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3169181A priority Critical patent/JPS57147255A/en
Publication of JPS57147255A publication Critical patent/JPS57147255A/en
Publication of JPS6217871B2 publication Critical patent/JPS6217871B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4338Pistons, e.g. spring-loaded members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 本発明は高密度LSI(Large Scule Integr―
ation)パツケージに関し、特に複数個のIC
(Integrated Circuit)チツプを高密度に搭載可能
で、かつ、放熱特性の良好なマルチチツプLSIパ
ツケージに関する。
[Detailed Description of the Invention] The present invention is a high-density LSI (Large Scule Integration)
ation) Regarding package, especially for multiple ICs.
(Integrated Circuit) Pertains to a multi-chip LSI package that can mount chips at high density and has good heat dissipation characteristics.

近年、コンピユータの高性能化および小型化の
要求がますます高まり、このためICチツプの集
積度は、数年前には数百ゲート/チツプであつた
ものが最近では1000ゲート/チツプのものまで実
現されるにいたつている。それとともに、ICチ
ツプのチツプあたり消費電力も向上し、2〜
4W/チツプの電力を消費するものが一般的とな
りつつある。
In recent years, demands for higher performance and smaller computers have been increasing, and as a result, the density of IC chips has increased from a few hundred gates/chip a few years ago to 1000 gates/chip in recent years. It is on the verge of being realized. At the same time, the power consumption per IC chip has improved, and
Devices that consume 4W/chip power are becoming common.

これは、集積度の向上によりゲートあたりの消
費電力は減少しているにもかかわらずチツプあた
りのゲート数が増大することによりチツプあたり
の消費電力はむしろわずかながら増加することに
よるものである。
This is because, although the power consumption per gate is decreasing due to an increase in the degree of integration, the power consumption per chip increases slightly due to the increase in the number of gates per chip.

ところで、これらのICチツプを搭載する従来
のLSIパツケージはプリント板上にケース入りの
単独チツプを半田付等の手段により取りつけたカ
ードタイプのものが多く用いられていたが最近で
は小型化および高性能化の要求から複数個のIC
チツプをチツプキヤリアとよぼれる小型のケース
により基板上に搭載しかつ基板内に多層の信号配
線を施したマルチチツプパツケージが使用される
ようになつてきている。
By the way, the conventional LSI package that mounts these IC chips is often a card type, in which a single chip in a case is attached to a printed board by means such as soldering, but recently it has become smaller and has higher performance. Multiple ICs due to demand for
Multi-chip packages, in which chips are mounted on a board using a small case called a chip carrier, and multilayer signal wiring is provided within the board, are coming into use.

このような、マルチチツプパツケージを実現す
るときの課題は、第1にはいかにICチツプをパ
ツケージ上に多数個、すなわち高密度に搭載する
かであり、第2には、これらの高集積度の多端子
のICチツプ間の配線を高密度に形成するかであ
り、第3にはこれらの高集積度かつ高消費電力の
ICチツプの発生する熱をいかにして効率よく放
散させるかにある。
The challenges when realizing such a multi-chip package are, firstly, how to mount a large number of IC chips on the package, that is, at high density, and secondly, how to mount these highly integrated chips on the package. The third challenge is to form high-density wiring between multi-terminal IC chips.
The problem lies in how to efficiently dissipate the heat generated by IC chips.

これらの課題を果すことができればマルチチツ
プパツケージの形状の小型化が可能となり従つて
配線長が短くなることによる動作速度の向上すな
わち高性能化や実現でき同時に回路の高密度化も
実現できる。
If these issues can be achieved, it will be possible to reduce the size of the multi-chip package, thereby increasing the operating speed by shortening the wiring length, i.e., achieving higher performance, and at the same time achieving higher circuit density.

本発明の目的は、上述の欠点を除去した効率的
放熱を可能とし小型化をはかつた高性能および高
密度のマルチチツプLSIパツケージを提供するこ
とにある。
An object of the present invention is to provide a high-performance, high-density multi-chip LSI package that eliminates the above-mentioned drawbacks, enables efficient heat dissipation, and is miniaturized.

本発明のパツケージは、少なくとも1つのボン
デイングパツドを有する多層配線基板と、 前記ボンデイングパツドに接続されるICリー
ドをもつ少なくとも1つのICチツプと、 それぞれが良熱伝導性材料により形成され前記
ICチツプを搭載しこの搭載面の四隅に設けられ
前記多層配線基板に固定された少なくとも4つの
突起を有する複数のチツプキヤリアと、 これらのチツプキヤリアのそれぞれに対応して
設けられかつこれらキヤリアのそれぞれのICチ
ツプ搭載面とは反対側の面に設けられた複数のヒ
ートシンクと、 これらヒートシンクのそれぞれを前記チツプキ
ヤリアの前記反対側の面に固定するよう保持する
保持機構とを有する。
The package of the present invention comprises: a multilayer wiring board having at least one bonding pad; and at least one IC chip having an IC lead connected to the bonding pad, each of which is made of a material with good thermal conductivity;
A plurality of chip carriers each having at least four protrusions on which IC chips are mounted, which are provided at the four corners of the mounting surface and fixed to the multilayer wiring board; It has a plurality of heat sinks provided on a surface opposite to the chip mounting surface, and a holding mechanism that holds each of these heat sinks so as to be fixed to the opposite surface of the chip carrier.

次に本発明について図面を参照して詳細に説明
する。
Next, the present invention will be explained in detail with reference to the drawings.

第1図を参照すると、本発明の一実施例は多層
配線基板8、この基板8の下面に取り付けられた
入出力端子9、前記多層配線基板8の上面に取り
付けられたICリード3を有する複数のICチツプ
1、これらICチツプ1のICリード3を取り付け
るため前記基板8に設けられたボンデイングパツ
ド4、これらのICチツプ1のそれぞれを取り付
けかつ前記基板8に取り付けられる複数のチツプ
キヤリア2、これらチツプキヤリア2に密着する
ように位置付けられる吸熱体5―2を一端に設け
他端に放熱フイン5―1を設けたヒートシンク
5、このヒートシンク5を保持する保持機構7、
およびこの保持機構7と前記ヒートシンク5の吸
熱体5―2との間に挿入されるバネ6から構成さ
れている。
Referring to FIG. 1, one embodiment of the present invention includes a multilayer wiring board 8, an input/output terminal 9 attached to the bottom surface of the board 8, and a plurality of IC leads 3 attached to the top surface of the multilayer wiring board 8. IC chips 1, bonding pads 4 provided on the substrate 8 for attaching the IC leads 3 of these IC chips 1, a plurality of chip carriers 2 to which each of these IC chips 1 is attached and attached to the substrate 8, these A heat sink 5 having a heat absorbing body 5-2 positioned in close contact with the chip carrier 2 at one end and a heat dissipating fin 5-1 at the other end, a holding mechanism 7 for holding this heat sink 5,
and a spring 6 inserted between this holding mechanism 7 and the heat absorbing body 5-2 of the heat sink 5.

前記多層配線基板8は最近よく用いられて周知
のグリーンシート積層型セラミツク基板を使用す
れば、内層に多層の配線を収容することができる
ので最ものぞましい。しかし、基板8はグリーン
シート積層型セラミツク基板が必要不可欠の条件
ではなく、例えば、セラミツク基板上に厚膜ペー
スト印刷法により配線層および絶縁層を形成した
多層配線基板であつてもよく、また同様にセラミ
ツク基板上に有機絶縁層と多層の配線層を形成し
た有機絶縁多層配線基板であつてもよい。すなわ
ち多層配線基板8がどのような技術で製造された
ものであろうと本発明のマルチチツプLSIパツケ
ージを構成する多層配線基板8として使用するこ
とができる。
As the multilayer wiring board 8, it is most preferable to use a green sheet laminated ceramic board, which has recently been widely used and is well known, since multilayer wiring can be accommodated in the inner layer. However, the substrate 8 is not necessarily a green sheet laminated ceramic substrate; for example, it may be a multilayer wiring substrate in which a wiring layer and an insulating layer are formed on a ceramic substrate by a thick film paste printing method. Alternatively, it may be an organic insulating multilayer wiring board in which an organic insulating layer and multilayer wiring layers are formed on a ceramic substrate. That is, no matter what technology the multilayer wiring board 8 is manufactured with, it can be used as the multilayer wiring board 8 constituting the multichip LSI package of the present invention.

第2図を参照すると、前記チツプキヤリア2は
ICチツプ1が多層配線基板8に対しICチツプ内
の配線、トランジスタ等が形成されている面を表
すなわちフエースとするときにフエースダウンに
なるようにチツプキヤリア2にダイボンデイング
されている。前記ICチツプ1の周辺に設けられ
たICリード3はチツプキヤリア2との接続はな
く、多層配線基板8上のボンデイングパツド4に
直接ボンデイング接続される。またチツプキヤリ
ア2は四隅に突起2―1を有している。この突起
2―1は、チツプキヤリア2を多層配線基板8に
接着保持するとともに、ICチツプ1の機械的保
護、ICリード3の位置決めおよび機械的保護の
ために必要な空間をチツプキヤリア2と多層配線
基板8の表面との間に確保するために設けられて
いる。
Referring to FIG. 2, the chip carrier 2 is
The IC chip 1 is die-bonded to the chip carrier 2 so that the surface on which wiring, transistors, etc. in the IC chip are formed with respect to the multilayer wiring board 8 is placed face down. The IC leads 3 provided around the IC chip 1 are not connected to the chip carrier 2, but are directly bonded to bonding pads 4 on the multilayer wiring board 8. The chip carrier 2 also has protrusions 2-1 at the four corners. This protrusion 2-1 adheres and holds the chip carrier 2 to the multilayer wiring board 8, and also provides space necessary for mechanical protection of the IC chip 1, positioning and mechanical protection of the IC leads 3 between the chip carrier 2 and the multilayer wiring board. 8.

第3図を参照すると、ヒートシンク5は放熱フ
イン5―1、これを取りつけた支柱5―3および
吸熱体5―2からなり、放熱フイン5―1と吸熱
体5―2は支柱5―3を介してネジ止め接続され
ている。ネジ止め接続の際、放熱フイン5―1が
取りつけられた支柱5―3は保持機構7に設けら
れたヒートシンク取付穴7―1にさし込まれ下側
からバネ6をはさみ込まれて吸熱体5―2がネジ
止めされる。この組み立て後の断面は第1図に示
すとおりでありバネ6の弾力により吸熱体5―2
が確実にチツプキヤリア2に接触するように工夫
されている。前記保持機構7は第1図に示すよう
に、複数個のヒートシンク5を保持しそれぞれの
ヒートシンク5に取りつけられたバネ6の弾力で
多層配線基板8上の全てのチツプキヤリア2にそ
れぞれヒートシンクの吸熱体が均一に接触するよ
うに基板8に対して取りつけられている。本発明
の一実施例では以上の説明のように吸熱体5―2
をチツプキヤリア2に確実に接触させるためにバ
ネ6を用いた例を説明したが、他の実施例として
ヒートシンク取付穴7―1の内壁に雌ネジタップ
を設けかつ放熱フイン5―1の取りつけられた支
柱5―3の周囲にも雄ネジタツプを設けて支柱5
―3をねじ込むことによりネジの圧力で吸熱体5
―2をチツプキヤリア2に接触させてもよい。も
ちろんこの場合支柱5―3をねじ込むときには吸
熱体5―2はすでに5―3にねじ止めされている
必要がある。
Referring to FIG. 3, the heat sink 5 consists of a heat dissipation fin 5-1, a support post 5-3 to which the heat sink 5-1 is attached, and a heat absorber 5-2. Connected via screws. When connecting with screws, the column 5-3 to which the heat dissipation fin 5-1 is attached is inserted into the heat sink mounting hole 7-1 provided in the holding mechanism 7, and the spring 6 is inserted from below to form a heat absorbing body. 5-2 is screwed. The cross section after this assembly is as shown in Figure 1, and due to the elasticity of the spring 6, the heat absorbing body 5-2
It is devised to ensure that the tip contacts the chip carrier 2. As shown in FIG. 1, the holding mechanism 7 holds a plurality of heat sinks 5, and uses the elasticity of a spring 6 attached to each heat sink 5 to attach the heat absorbing body of the heat sink to each of the chip carriers 2 on the multilayer wiring board 8. are attached to the substrate 8 so as to be in uniform contact with each other. In one embodiment of the present invention, as described above, the heat absorber 5-2
Although we have described an example in which the spring 6 is used to ensure that the heat sink is brought into contact with the chip carrier 2, another example is to provide a female screw tap on the inner wall of the heat sink mounting hole 7-1 and to attach a support post to which the heat dissipation fin 5-1 is attached. Provide a male screw tap around 5-3 and attach the support 5.
- By screwing in 3, the heat absorbing body 5 is heated by the pressure of the screw.
-2 may be brought into contact with the chip carrier 2. Of course, in this case, when screwing in the strut 5-3, the heat absorbing body 5-2 must already be screwed to the support 5-3.

以上の説明により本発明によるマルチチツプ
LSIパツケージは次のような効果をもたらす。
According to the above explanation, the multi-chip according to the present invention
The LSI package brings the following effects.

第1に、チツプキヤリアに接着されたICチツ
プのリードは直接多層配線基板にボンデイング接
続されるためチツプキヤリア内に配線を施す必要
がなく従つてチツプキヤリアの材料に熱伝導性の
良好な金属材料を用いることができ効果的な放熱
が可能である。
First, since the leads of the IC chip bonded to the chip carrier are directly bonded to the multilayer wiring board, there is no need to provide wiring inside the chip carrier, and therefore a metal material with good thermal conductivity is used as the material of the chip carrier. This enables effective heat dissipation.

第2に、さらに前記第1と同じ理由によりチツ
プキヤリアの小型化が可能となり基板上高密度実
装が実現できる。
Second, for the same reason as the first, it is possible to downsize the chip carrier and achieve high-density mounting on the board.

第3に、チツプキヤリアは突起によつてチツプ
を覆いこみ機械的保護の役目も果すので、吸熱体
の接触圧力に対して十分にチツプを機械的に保護
することができる。
Thirdly, since the chip carrier also serves as mechanical protection by covering the chip with its protrusions, the chip can be sufficiently mechanically protected against the contact pressure of the heat absorbing body.

第4に、第1から第3の特徴により多数個の
ICチツプを基板上に高密度に実装できることに
なるが、この場合、ICチツプ間を接続する配線
数が増大するが基板に多層配線基板を使用するこ
とにより配線の高密度化が可能であり、総合的に
高密度のLSIパツケージを実現することができ
る。
Fourth, due to the first to third characteristics, a large number of
This means that IC chips can be mounted on the board with high density, but in this case, the number of wires connecting between the IC chips increases, but by using a multilayer wiring board for the board, it is possible to increase the density of wiring. A comprehensively high-density LSI package can be realized.

第5に第2の特徴によりICチツプを高密度に
実装できることからLSIパツケージの小型化が可
能となり従つてICチツプ間接続配線長も短くな
るので高速化、すなわち、高性能化が実現でき
る。
Fifth, because of the second feature, IC chips can be mounted at high density, making it possible to miniaturize the LSI package, and thus also shorten the length of interconnections between IC chips, thereby achieving higher speeds, that is, higher performance.

本発明には熱伝導性の良好な小型チツプキヤリ
アとこれに接触して放熱できるヒートシンクと小
型チツプキヤリアを高密度に搭載できる多層配線
基板とにより構成することにより高密度および高
速度のマルチチツプLSIパツケージを実現できる
という効果がある。
The present invention realizes a high-density and high-speed multi-chip LSI package by constructing a small chip carrier with good thermal conductivity, a heat sink that can dissipate heat by contacting it, and a multilayer wiring board that can mount small chip carriers at high density. There is an effect that it can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す図、第2図は
第1図のチツプキヤリア2の詳細な構成を示す図
および第3図は第1図のヒートシンク5の詳細な
構成を示す図である。 第1図から第3図において、1……ICチツ
プ、2……チツプキヤリア、3……ICリード、
4……ボンデイングパツド、5……ヒートシン
ク、6……バネ、7……保持機構、8……多層配
線基板。
1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the chip carrier 2 shown in FIG. 1, and FIG. 3 is a diagram showing a detailed configuration of the heat sink 5 shown in FIG. 1. be. In Figures 1 to 3, 1...IC chip, 2...chip carrier, 3...IC lead,
4... Bonding pad, 5... Heat sink, 6... Spring, 7... Holding mechanism, 8... Multilayer wiring board.

Claims (1)

【特許請求の範囲】 1 少なくとも1つのボンデイングパツドを有す
る多層配線基板と、 前記ボンデイングパツドに接続されるICリー
ドをもつ少なくとも1つのICチツプと、 それぞれが良熱伝導性材料により形成され前記
ICチツプを搭載しこの搭載面の四隅に設けられ
前記多層配線基板に固定された少なくとも4つの
突起を有する複数のチツプキヤリアと、 これらチツプキヤリアの各々に対応して設けら
れかつこれらキヤリアのそれぞれのICチツプ搭
載面とは反対側の面に設けられた複数のヒートシ
ンクと、 これらヒートシンクのそれぞれを前記チツプキ
ヤリアの前記反対側の面に固定するよう保持する
保持機構とを有することを特徴とするマルチチツ
プLSIパツケージ。
[Scope of Claims] 1. A multilayer wiring board having at least one bonding pad; and at least one IC chip having an IC lead connected to the bonding pad, each of which is made of a material with good thermal conductivity;
A plurality of chip carriers each having at least four protrusions on which IC chips are mounted, which are provided at the four corners of the mounting surface and fixed to the multilayer wiring board; A multi-chip LSI package characterized by having a plurality of heat sinks provided on a surface opposite to a mounting surface, and a holding mechanism that holds each of these heat sinks so as to be fixed to the opposite surface of the chip carrier.
JP3169181A 1981-03-05 1981-03-05 Multichip lsi package Granted JPS57147255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3169181A JPS57147255A (en) 1981-03-05 1981-03-05 Multichip lsi package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3169181A JPS57147255A (en) 1981-03-05 1981-03-05 Multichip lsi package

Publications (2)

Publication Number Publication Date
JPS57147255A JPS57147255A (en) 1982-09-11
JPS6217871B2 true JPS6217871B2 (en) 1987-04-20

Family

ID=12338093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3169181A Granted JPS57147255A (en) 1981-03-05 1981-03-05 Multichip lsi package

Country Status (1)

Country Link
JP (1) JPS57147255A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143395U (en) * 1989-05-02 1990-12-05

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6381844B1 (en) 1999-12-15 2002-05-07 Sun Microsystems, Inc. Method for thermally connecting a heat sink to a cabinet
FR2967763B1 (en) * 2010-11-19 2014-07-04 Thales Sa HEAT DISSIPATING DEVICE AND CORRESPONDING ELECTRONIC BOARD
CN109920755B (en) * 2019-02-25 2021-01-05 天津大学 Nano-silver solder paste low-pressure auxiliary sintering clamp and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143395U (en) * 1989-05-02 1990-12-05

Also Published As

Publication number Publication date
JPS57147255A (en) 1982-09-11

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