JPS614239A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To ensure the burying of polysilicon in each isolating groove even if difference is present in the opening widths of the isolating grooves, which are used for isolating elements in the same substrate, by decreasing the resistance of the polysilicon in a part adjacent to the isolating groove in comparison with the polysilicon filled in the isolating groove for the element isolation. CONSTITUTION:Patterning is performed on a three-layer film 17 comprising an oxide film 14, which is layered on a substrate 10, a nitride film 15 and a PSG film 16. Etching is performed by an RIE method, and an isolating groove 19 is formed. Thereafter, thermal oxidation of the substrate 10 is performed, and an oxide film 21 is formed on the surface of the isolating groove 19. Then, polysilicon 22 is deposited on the entire surface of the substrate 10 by a pressure reduced CVD method. Thereafter, phosphorus in the PSG film 16 is infiltrated into the polysilicon in an upper region P, wherein the PSG film 16 is present, by thermal treatment. The resistance of said region is made low. Then, etching is performed for the polysilicon on the substrate 10 by an RIE method. The etching conditions are selected so that an upper surface 22a of the polysilicon in a region Q, whose etching rate is small, is approximately aligned with a surface 10a of the substrate 10. Then thermal oxidation of the surface of the polysilicon 22 in the isolating groove 19 is performed, and an oxide film 24 is formed. Thereafter the three- layer film 17 is removed by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device by improving the device isolation technology applied to ICs, LSIs, VLSIs, etc.

(B) Prior art The conventional method for isolating elements between buried type elements in a semiconductor element is to form a groove in the element isolation part and deposit polysilicon on the semiconductor element including the isolation groove. The idea is to take advantage of the fact that the isolation trench is thick and to remove the polysilicon on the semiconductor element while leaving the polysilicon in the isolation trench. However, with this method, there is no problem if the opening widths of the isolation trenches are the same size9, but if there is a large difference in the width of the multiple openings, polysilicon may not be sufficiently filled into the isolation trenches with large opening widths. There was a drawback that there was no

Figure 3 explains the drawbacks of this conventional method.
, b are cross-sectional views showing a state in which a polysilicon film is attached and a state in which a surface portion is removed and removed after being attached. In the figure, (1) is a semiconductor substrate, (2) is an oxide film, (3a) (3b) (3c)
(4) is an isolation trench for element isolation, and (4) is a polysilicon film. On the isolation trenches (3a) and (3c) with small opening widths, a polysilicon film with a sufficiently larger thickness than the film on the adjacent substrate is obtained, so even if the polysilicon film in the adjacent region is removed, the isolation trenches It is possible to leave polysilicon in (3a) and (3c), but the polysilicon film on the isolation trench (3b) with a large opening width can be completely removed in the etching process. One drawback was that no separation region was formed. Regarding element isolation, see Nikkei Electronics Magazine March 29, 1982 issue F90-100.
You can refer to the paper titled ``Presentation of a new device isolation technology to replace selective oxidation.''

(c) Problems that the invention seeks to solve The present invention makes it possible to reliably fill polysilicon into each isolation trench even if the opening widths of the isolation trenches used for element isolation differ between devices on the same substrate. 1 64'(7)f
;F+6° (D) Means for Solving Problems The present invention provides a method for forming isolation trenches for element isolation in a semiconductor substrate and burying polysilicon therein. A polysilicon layer is attached on the adjacent semiconductor substrate, and the adjacent portion of the polysilicon layer is subjected to a process to lower its resistance. After that, an etching process is performed on the polysilicon layer to form a sufficient amount of silicon in the isolation trench for device isolation. This is characterized by allowing polysilicon to remain.

(E) Function In the present invention, compared to the polysilicon filling the isolation trench for element isolation, the polysilicon in the portion adjacent to the isolation trench is subjected to a lower resistance treatment, so that the resistance of the polysilicon in the portion adjacent to the isolation trench is lowered. In the etching step, the etching speed of the polysilicon in the low-resistance portion can be increased, so that the polysilicon in the isolation groove portion can be left and the polysilicon in the adjacent portion of the isolation groove can be removed.

(f) Example FIG. 1 is a partial cross-sectional view of a semiconductor device manufactured by the method of the present invention (the 1g cell structure is not shown). (
10) is a semiconductor substrate made of single crystal silicon, (l1g>(
llb>(llc) is an isolation groove for element isolation, (12
a) (12b) (12c) are polysilicon filled in each of these isolation trenches, (138) (13b) < 13
C) is a 5i02 film between each of these polysilicon and the semiconductor substrate (10). Separation groove with small opening width (lla
) (11C) are polysilicon (12a) (12c) in the isolation groove (flb) with a large opening width.
2b), and at least the filling (polysilicon and S, 40z) in the separation groove (12b)
) is constructed to have a level higher than the surface of the substrate (10).

- Figures 2a to 2f' are process explanatory diagrams of an example of the method of the present invention. (lO) is an N-type silicon semiconductor substrate, and an oxide film (S io 2 > (14) with a thickness of 500 nm is formed on the surface of the substrate by a thermal oxidation method, and then a night film is formed on this oxide film. A Ride (S'i3N4) film (15) was formed to a thickness of 1200 by low pressure CVD,
Furthermore, on top of this nitride film, a PS film with a thickness of 1000A is applied.
G (phospho-silicate glass)
Deposit a membrane (16). Figure 2(a) shows the substrate (
10) On top, oxide film (14), nitride film (15)
, and a 3HI film <17> consisting of a PSG film (16) are shown stacked one after another.

Next, patterning is performed on this three-layer film (17), and then the three-layer film (18) in the area where element isolation is to be performed is applied.
17) by a dry etching method, and then the substrate (10) in this area is subjected to RIE (react, ive io
Separation grooves are created by etching using the
form. This separation groove is formed without causing so-called side etching due to the characteristics of the RIE method. FIG. 2(b) shows the substrate (1) immediately after forming this separation groove (19).
0) is shown.

Next, channel stop ions such as phosphorus (20) are injected into the lower region of the separation groove (19) to make the lower region highly concentrated N type and ensure separation in the separation groove region. Thereafter, the substrate (10) is thermally oxidized to form isolation grooves (19).
By oxidizing the Si on the surface, a film thickness of approximately 1,000 oxides (S
io 2 ) (21). FIG. 2(c) shows a cross-sectional view of the substrate after one culm of this heat treatment is completed.

Next, polysilicon (22) is deposited to a thickness of about 12,000 on the entire surface side of this substrate (10) using a low pressure CVD method that thermally decomposes silane gas. After that, normal pressure,
A heat treatment is performed at 1000° C. for about 30 minutes in a N2 atmosphere, and in this heat treatment step, the phosphorus in the PSG film (16) penetrates into the polysilicon in the upper region (P) where the PSG film (16) exists. ze, lower the resistance of the relevant part. Broken line (23
a) The polysilicon in the region (Q) surrounded by (23b) is not affected by the PSG film <16) and is maintained at the resistance at the time of deposition and is not lowered in resistance. FIG. 2(d) shows a cross-sectional view of the substrate after the heat treatment process.

Next, RIE is performed on the polysilicon on the substrate (10).
Perform etching by law. This erasing condition is such that the polysilicon film (film in region (P)) other than the region (Q) with a small etching rate is completely removed, and the polysilicon film (22 ) is almost the substrate, D
o) cn*i("0°)" *t6, l: 3
1: −Z −y + > f p. (See Figure 2(e)).

Next, the polysilicon (22hlE) in the isolation trench (19) is
The surface is thermally oxidized to form an oxide film (24) with a thickness of about 3000 nitrides, and then the 3NI film (17) is removed by etching (see FIG. 2 <r>). This three-layer film (17
) may be etched at once with one etchant, but it may also be removed sequentially from the upper layer side using an etchant that has a small effect on the polysilicon in the isolation trench. After this, transistors and the like are formed in the region adjacent to the isolation trench, but a description of the process will be omitted.

In the present invention, a method of implanting ions using a mask having an opening in the relevant region may be used to reduce the resistance of the adjacent region, but the above embodiment is easier to manufacture because it does not require mask alignment. There is an advantage to having one. Incidentally, FIGS. 2(a) to 2(f) represent the portions (■) to (■) in FIG. 1.

(g) Effects of the Invention The present invention performs a process to lower the resistance of the polysilicon located in the region adjacent to the separation trench and the polysilicon located above the trench to increase the etching rate. Therefore, it is possible to remove polysilicon in the adjacent region and leave polysilicon in the isolation trench.
Even if the opening widths of the isolation trenches are different, polysilicon isolation regions can be formed in all of them. In addition, the resistance reduction process is applied to the P layer located below the polysilicon film adjacent to the isolation trench.
If the phosphorus component from the SG film is used for ion implantation to lower resistance, a mask is not required, which is advantageous.

[Brief explanation of the drawing]

Figure 1 is a partial sectional view of a semiconductor device manufactured by the method of the present invention, Figures 2 (a) to (f') are process explanatory diagrams of the method of the present invention, and Figures 3 (a) and (b) are conventional methods. FIG.

Claims (2)

[Claims] (1) A step of forming an isolation trench in an element isolation portion of a semiconductor substrate, a step of attaching an oxide film to the surface portion of this isolation trench, and a step of forming an oxide film on the surface of the isolation trench, and a step of forming an isolation trench within the isolation trench and adjacent to the isolation trench on the oxide film. A step of attaching polysilicon on an adjacent portion of the semiconductor substrate, and performing a resistance reduction treatment on the polysilicon on the adjacent portion to create a difference in etching rate between the polysilicon in the isolation trench and the polysilicon on the adjacent portion. and a step of removing polysilicon on the adjacent portion. (2) The resistance lowering treatment is performed by infiltrating the phosphorus component in the PSG film on the semiconductor substrate into the polysilicon on the adjacent portion by heat treatment.
) The method for manufacturing a semiconductor device according to item 2.