JPS6142282A - Single-phase transistor inverter - Google Patents

Abstract

PURPOSE:To improve the conversion efficiency by using field effect transistors connected in parallel as a switching circuit, and further providing a pause period at switching time, thereby preventing a peak voltage from generating. CONSTITUTION:An abnormal DC input voltage is detected by high and low voltage detectors 1, 2, and an oscillation stopping circuit 3 stops oscillating of an oscillator 4 by the detected output. A rectangular wave signal from the oscillator 4 is fed to switching circuits 51, 52. The circuits 51, 52 are formed of CMOS buffers BA1, BA2, and field effect transistors Q5-Q10, Q11-Q16, and a pause period that both become OFF is provided between when the buffer BA1 is ON and when the buffer BA2 is ON. An AC voltage having the pause period is obtained at the secondary side coil of the transformer T.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application) This invention relates to a single-phase transistor inverter that converts direct current to alternating current.

(Prior Art and its Problems) Conventionally, as this type of single-phase transformer/displacement meter, a transistor switching method using separately excited oscillation and a transistor switching method using self-excited oscillation are known.

FIG. 4 shows an example of an inverter circuit using the self-excited oscillation-based transistor/distortion inoting method. This system uses a transformer T, switching power transistors Ql, Q2
．． It consists of resistors R1°R2, R5 capacitors C1 and C2, and diode D. This method has the advantage of being inexpensive to manufacture because it has a simple structure, but
The AC output frequency is unstable, and as shown in FIG. 5, a peak voltage (indicated by symbol P in the figure) occurs in the output waveform, and furthermore, the female conversion efficiency is good at the rated output.

It has the disadvantage of being poor at 1/3 to L/2 loads (see curve q in FIG. 3). Note that the generation of peak voltage can damage electrical equipment connected to the inverter.

On the other hand, although an inverter using a transistor switching method using separately excited oscillation has a stable frequency and fewer peak voltages occur in the output waveform, the conversion efficiency is still not improved.

Generally, transistors used in transistor switching systems have a low current amplification factor (hfe), so a large amount of pace current is passed through them for ON/OFF operation.However, this base current is not used for alternating current output. does not contribute anything and is a big loss. To compensate for this, it is possible to use a Darlington transistor with a high current amplification factor (hfe), but this transistor has a high ON voltage (VCE), which reduces the efficiency at the rated output and also reduces the characteristics. The disadvantage is that there is a large variation in the number of units, making it difficult to connect multiple units in parallel.

Therefore, most commercially available transistor switching type inverters #1 are those in which a plurality of transistors with a low current amplification factor (HFE) are connected in parallel. However, even in this case, if a balance resistor is not interposed at the emitter of each transistor, individual variations will cause abnormal heat to be concentrated in one transistor with a large current, leading to the destruction of the transistors one after another. However, it also has the disadvantage of reduced reliability.

(Summary of the Invention) In particular, in order to increase conversion efficiency, the present invention includes a switching circuit consisting of a plurality of field effect transistors connected in parallel, and an oscillator that outputs a signal waveform that does not generate peak voltage in the AC output waveform. and an oscillation stop circuit that detects an abnormal DC input voltage and stops the oscillation of the oscillator, rendering the entire inverter inoperable.

(Embodiment) FIG. 1 is an overall circuit diagram of a single-phase transistor I/PARK according to an embodiment of the present invention.

In the figure, 5WIt';j operation switch, SW211 AC output 50H2/60H2 changeover switch (60H2 when closed,
50H2 when open), L] C Light emitting diode for displaying DC voltage input, L2 is light emitting diode for displaying DC excessive input voltage and under input terminal, Dz-06H diode, Z
l~Z7 Hanoener diode, S is cyrisk, Bl
i Varistor, Ht1 choke coil, Cl-Cl0 are capacitors, R1-R28 are resistors, Q]~Q4 are transistors, Q5~Q16 are field effect transistors, COM
I and C0M2 are comparators, BAI and BA2 H are each 6
C MOS buffer IC (405
0), ACV fl AC voltmeter, T is transformer, cv
H constant voltage circuits are shown respectively. In addition, the operation switch 5w
tH, capacitor C], and diodes DI and D2. It also serves as a circuit breaker that operates by reverse connection. Also, Chikok Coil H and Conde/SuC
This is a filter for blocking the noise component of the 211 DC input voltage, and serves as a malfunction prevention circuit for the constant voltage L-to-circuit CV. Furthermore, the light emitting diode L]fl is also used to display the operation of the constant voltage circuit CV.

Further, in FIG. 1, numeral 1 is a high voltage detection circuit that detects a high voltage abnormality in the DC input voltage, and 2 is a low voltage detection circuit that detects a low voltage abnormality in the DC input voltage.

The high voltage abnormality detection circuit 1 has a comparator COMI, and a reference voltage (
For example, the output voltage E (V') of the constant electronic circuit CV is set to 8 (Vl
Then, 40) is done manually.

Here, when the voltage at the + (plus) input terminal of this comparator COMI becomes higher than the reference voltage of one input terminal, the comparator COMI
A 5-output voltage signal (abnormality detection signal) is output to the output terminal of M+, and this signal acts on the thyristor S in the oscillation stop circuit 3 of the next circuit (thyristor trigger) through the diode D3 to turn on the thyristor S. (conductivity). Note that, if the rated DC input voltage is 12 [V'], the high voltage detection circuit 1 is equipped with electronic elements (resistors, foundations, /su etc.) etc.

It has a low voltage abnormality detection circuit 2Vi and a comparator C0M2, and a reference voltage is applied to the input terminal of the comparator C0M2 by an electric element including a Zener diode z1. Here, when the voltage of one input terminal of this comparator C0M2 becomes lower than the reference electron of the tenth input terminal, the comparator C0M
A Hi voltage signal (abnormality detection signal) is output to the output terminal of 2, and this signal acts (thyristor trigger) on the thyristor S in the oscillation stop circuit 3 of the next circuit through the diode D4, turning this thyristor S ON ( For example, if the rated DC input voltage is 12[Vl], the low voltage detection circuit 2 is designed to output an abnormality detection signal when the DC input voltage is 9°511y1 or less. It is set by electronic elements etc.

The oscillation stop circuit 3 is a circuit that is operated by the abnormality detection signals from the high voltage abnormality detection circuit 1 and the low voltage abnormality detection circuit 2, and this operation causes the oscillation of the oscillator 4 in the next circuit to be stopped.

That is, when the thyristor S turns on, the transistor Q
l is QFF (non-conducting), and accordingly transistor Q
2 turns on, the collector voltage of the oscillator 4 in the next circuit is turned off via the diodes D5 and D6, and the oscillation of the oscillator 4 is stopped (both transistors Q3 and Q4 (I-OFF)).

Note that transistor Q1 is turned off by the abnormality detection signal.
L, when transistor Q2 turns on, light emitting diode L
2 lights up, indicating that there is an abnormality in the DC input voltage. When the thyristor trigger degree is ON, the activation switch swi
It is suitable for circuit protection because it will not turn off until the switch is turned off, a predetermined DC input voltage is applied, and the operating switch SWI is turned on again. Therefore, instead of this thyristor S, R
You can use S flip-flops.

Oscillator 4 includes transistors Q3. In the non-stable multivibrator having Q4, each of the collectors a and bK can obtain rectangular wave signals having a phase difference of 180° as shown in FIGS. 2(a), (b) and K.

If the piezoelectric F of the constant voltage circuit CV is E concavity - e.g. This is a falling waveform.This envelope is formed by resistor R21 and capacitor C8,
and is formed by resistor R23 and content C9. These two rectangular wave signals are sent to the next switching circuits 51 and 52, respectively.

A switching circuit 51c, for example, six pins.

) T CMOS buffer IC (4050) BAI
-hereinafter referred to as the Banoff circuit BAI-- and six field effect transistors (FET) Q5-Q10. In addition, the switching circuit 52 has a CMOS buffer IC (405
0) BA2 - hereinafter referred to as buffer circuit BA2 - and 6
field effect transistors (FETs) Qll to Q16
It is composed of.

Each buffer of the buffer circuit BAl receives the second signal from the oscillator 4.
A rectangular wave signal shown in FIG. 2(a) is input, and a rectangular wave signal having a waveform shown in FIG. 2(C) is output.

That is, for example, if the output voltage of the constant voltage circuit CV is Eo, it turns on at E /2 [yl and outputs E [V] (generally, the Sureno/Jord voltage of CMO5 is 1/2 of the power supply voltage). ) The output of each buffer is given to the gate terminal of FETQ5-QIO installed opposite to it,
Each FETQ5-QIO is designed to operate ON and OFF.

The buffer element circuit BAz4 is completely similar to the buffer circuit BA1, and outputs a rectangular wave signal with the waveform shown in FIG. 2(d).
ETQ11 to Q16 are turned ON and OFF. In addition,
As shown in Figure 2 (a), (b), (C), and (d),
Buffer y circuit BA 1 at 08 o'clock and buffer circuit BA2
A pause time t in which both are OFF is provided between 08:00 and 08:00.

The outputs e and f of these switching circuits 51 and 52 are connected to the primary fill of the transformer T, and the secondary coil is connected to the rest time ti as shown in FIG. 2 (el).
It is designed to obtain an AC voltage of A varistor B is connected between both ends of the primary coil of the transformer T, and a direct current →-input terminal is connected to the intermediate end thereof via an operating switch SWI. barista 811
Together with six Zener diodes 22 to Z7, it constitutes a protection circuit for FETs Q5 to Q]6 in the switching circuit 51.52.

FETQ 5 in switching circuit 51.52
If a power MO5FET is used as Q16, its ON/OFF can be determined by the fl gate voltage, and the loss is only the ON resistance of the FET.
This is a switching circuit that takes full advantage of the characteristics of ET.

Since the oscillation frequency of the oscillator 4 is low, the gate drive
Direct left drab is possible with the CMOS banff buffers (4050) of the buffer γ circuits BAI and BA2.

How much power does this require?

This is extremely small compared to the base current drive of general transistors. This is also the reason why the conversion efficiency is improved.

FIG. 3 is a conversion efficiency graph in which the input DC voltage is 12 [V], the output AC voltage is 100III/l, and 3 yen as an example, and the second curve shows the efficiency curve of the single-phase transistor inverter according to the present invention. The q curve shows the efficiency curve of the conventional single-phase transistor inverter shown in FIG. 4. Furthermore, the DC input power when the AC output is not loaded is less than 1/4 of that of the conventional type.

The single-phase inverter of this invention can be used alone, as well as
This can be applied to an uninterruptible power supply by combining a charger and a battery.

In this case, since the conversion efficiency is good, there is a power reduction problem in that the bank up time during a power outage becomes longer.

(Effects) As described above, according to the present invention, a field effect transistor connected in parallel to a switching circuit is used, and a rest time is provided during switching, so that a simple circuit with extremely high conversion efficiency and no peak voltage is generated can be achieved. It can provide Aitra/Jistai/Bark. In addition, since it detects excessive or insufficient DC input voltage and renders the entire device inoperable, it is extremely effective from the viewpoint of protecting the device and electrical equipment connected to the inverter.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a single-phase transistor inverter according to an embodiment of the present invention, and Fig. 2 (a) (bl (C) (d)
(el Id, signal waveform diagram of main points in Figure 1,
Figure 3 is an efficiency graph of the present invention compared to the conventional single-phase transistor inverter/disty/permet, Figure 4 is a circuit diagram of the conventional single-phase transistor inverter, and Figure 5 is the AC output voltage in Figure 4. FIG. 3... Oscillation stop circuit 4... Oscillator 51.52... Switching circuit T... Transformer ACV... AC voltmeter

Claims (1)

[Claims] Consisting of a detection circuit that compares the DC input voltage and the DC rated input voltage to detect high or low abnormal voltages of the DC input voltage, and an unstable multivibrator,
° an oscillator that outputs two rectangular wave signals with different phases;
an oscillation stop circuit that stops oscillation of the oscillator in response to an abnormality detection signal from the detection circuit; and two switching circuits comprising a parallel connection configuration of field effect transistors that are turned on and off by two output signals of the oscillator, respectively; A single-phase transistor inverter comprising a transformer that inputs each output signal of two switching circuits to a primary coil, and an AC voltmeter that displays an AC voltage obtained at a secondary coil of the transformer. .