JPS6142274A - Spike voltage absorbing circuit - Google Patents
Spike voltage absorbing circuitInfo
- Publication number
- JPS6142274A JPS6142274A JP15916784A JP15916784A JPS6142274A JP S6142274 A JPS6142274 A JP S6142274A JP 15916784 A JP15916784 A JP 15916784A JP 15916784 A JP15916784 A JP 15916784A JP S6142274 A JPS6142274 A JP S6142274A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- power supply
- capacitor
- voltage
- absorption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Protection Of Static Devices (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、スイッチング電源装置のスイッチング・トラ
ンジスタをスパイク電圧から保護するためのスパイク電
圧吸収回路(スナバ回路)に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a spike voltage absorption circuit (snubber circuit) for protecting a switching transistor of a switching power supply from spike voltage.
(従来例の構成とその問題点)
従来、電力効率が高く、小型化し易い等の長所を有する
スイッチング方式の安定化直流電源、所謂、スイッチン
グ電源は、電源装置におけるその使用比率が急速に高ま
っている。ところが、スイッチング電源には、しばしば
問題となるスイッチングノイズの問題に加えて、スイッ
チング・トランジスタのコレクタ端子に現れる高圧のス
パイク電圧の問題がある。近年ではスイッチングに用い
られるトランジスタやFETに比較的高耐圧のものが開
発されたり、変成器の1次側と2次側との結合度を高め
てスパイク電圧を小さくする工夫がなされてはいるが、
やはり何等かの保護回路がなくては、トランジスタの破
壊を防ぐことはできない。即ち、スイッチング・トラン
ジスタの最大導通時間比率を1/2とすると、そのコレ
クタ端子に印加される直流電圧の最大値は、理想的には
電源電圧の2倍になる。しかし、実際にはスパイク電圧
が発生するため、保護回路が挿入されていない状態では
、コレクタ電圧は電源電圧の3〜5倍にもなってしまう
。(Conventional configuration and its problems) Traditionally, switching type stabilized DC power supplies, so-called switching power supplies, which have advantages such as high power efficiency and easy miniaturization, are rapidly becoming more popular in power supply devices. There is. However, in addition to the frequent switching noise problem, switching power supplies also have the problem of high voltage spikes appearing at the collector terminal of the switching transistor. In recent years, relatively high voltage transistors and FETs have been developed for switching, and efforts have been made to reduce spike voltage by increasing the degree of coupling between the primary and secondary sides of transformers. ,
After all, it is impossible to prevent the transistor from being destroyed without some kind of protection circuit. That is, if the maximum conduction time ratio of a switching transistor is 1/2, the maximum value of the DC voltage applied to its collector terminal is ideally twice the power supply voltage. However, since a spike voltage actually occurs, the collector voltage will be 3 to 5 times the power supply voltage if no protection circuit is inserted.
第1図は、従来のスパイク電圧吸収回路の構成を示すも
ので、1はスイッチング用の主トランジスタ、2は主ト
ランジスタ1のベース駆動回路、3は1次側を1次側直
流電源〔以下直流電源という(図示しない)〕に接続し
、2次側を整流回路(図示しない)に接続した変成器、
4はダイオード5と、吸収用コンデンサ6と、抵抗7と
からなるスパイク電圧吸収回路で、このスパイク電圧吸
収回路4に入力したスパイク電圧は、ダイオード5を経
て吸収用コンデンサ6に充電、吸収された上、抵抗7に
よって放電される。Figure 1 shows the configuration of a conventional spike voltage absorption circuit, where 1 is the main transistor for switching, 2 is the base drive circuit of the main transistor 1, and 3 is the primary side DC power supply (hereinafter referred to as DC). A transformer connected to a power source (not shown) and whose secondary side is connected to a rectifier circuit (not shown),
4 is a spike voltage absorption circuit consisting of a diode 5, an absorption capacitor 6, and a resistor 7, and the spike voltage input to this spike voltage absorption circuit 4 is charged and absorbed by the absorption capacitor 6 via the diode 5. Above, it is discharged by the resistor 7.
このように構成された従来例では、1次側直流電源電圧
(以下電源電圧という)を140V(交流100Vを両
波整流したときの値)、主トランジスタ1の導通時間比
率を1/3とすれば、主トランジスタ1が遮断状態での
安定後のコレクタ電圧は210vとなり、ダイオード5
のカソード電圧は、スパイク波形によりコレクタ電圧よ
り少なくとも30V程度上昇して(スパイク電圧は完全
にはなくならない)、240v程度になり、抵抗7には
、ダイオード5のカソード電圧と電源電圧との差の10
0v程度が常時印加されることになる。この関係を図示
すると、第2図のようになる。In the conventional example configured in this way, the primary side DC power supply voltage (hereinafter referred to as power supply voltage) is 140V (the value when AC 100V is double-wave rectified), and the conduction time ratio of the main transistor 1 is set to 1/3. For example, when the main transistor 1 is in the cut-off state, the stabilized collector voltage is 210V, and the diode 5
The cathode voltage of the diode 5 rises by at least 30V from the collector voltage due to the spike waveform (the spike voltage does not disappear completely), and reaches about 240V. 10
Approximately 0V is constantly applied. This relationship is illustrated in FIG. 2.
今、抵抗7の抵抗値を5にΩとすると、電力損失WLは
、
WL = 1002/ 5000 = 2 (W)と
極めて大きな値となり、スイッチング電源装置の電力効
率の向上を妨げたり、放熱設計を困難にする上、抵抗7
の許容電力損失が大きくなると共に、抵抗7の形状が大
きくなって、装置の小型化を阻害し、更には、抵抗7の
抵抗値を上げて許容電力損失を低下させると、スパイク
電圧の吸収効果も低下させてしまう欠点があった。Now, if the resistance value of the resistor 7 is set to 5Ω, the power loss WL becomes an extremely large value of WL = 1002/5000 = 2 (W), which hinders the improvement of the power efficiency of the switching power supply and makes it difficult to improve the heat dissipation design. Make it difficult and resist 7
As the allowable power loss increases, the shape of the resistor 7 becomes larger, which impedes the miniaturization of the device.Furthermore, if the resistance value of the resistor 7 is increased to lower the allowable power loss, the effect of absorbing the spike voltage increases. It also had the disadvantage of lowering its performance.
(発明の目的)
本発明の目的は、抵抗の許容電力損失を生じることなく
スパイク電圧を吸収すると共に、電力効率が良く、発熱
の少ないスパイク電圧吸収回路を提供することにある。(Objective of the Invention) An object of the present invention is to provide a spike voltage absorption circuit that absorbs spike voltages without causing allowable power loss in resistors, has good power efficiency, and generates little heat.
(発明の構成)
本発明は、スパイク電圧を充電するときには、吸収用コ
ンデンサが1次側直流電源の高電位側端子と主トランジ
スタのコレクタ端子の間に接続され、吸収用コンデンサ
から放電するときには、吸収用コンデンサが1次側直流
電源の低電位側端子と1次側直流電源の高電位側端子と
の間に接続されるように、吸収用コンデンサの接続をス
イッチング素子によって切り換えることにより、スパイ
ク電圧を吸収して得たエネルギーを無損失で直流電源に
帰還させるようにしたものである。(Structure of the Invention) According to the present invention, when charging a spike voltage, an absorption capacitor is connected between the high potential side terminal of the primary DC power supply and the collector terminal of the main transistor, and when discharging from the absorption capacitor, By switching the connection of the absorption capacitor using a switching element so that the absorption capacitor is connected between the low potential side terminal of the primary side DC power supply and the high potential side terminal of the primary side DC power supply, the spike voltage can be reduced. The energy obtained by absorbing the energy is returned to the DC power supply without loss.
(実施例の説明)
第3図は、本発明の一実施例の原理を示すもので、第1
図の符号と同一符号のものは同一部分を示しており、又
、8は商用の交流電源、9は整流用のダイオード10.
11.12及び13からなる整流回路、14は平滑用の
コンデンサで、交流電源8、整流回路9及び平滑用コン
デンサ14で1次側直流電源(以下直流電源という)を
構成しており、交流電源8から出力された交流電圧は、
整流回路9において整流された後、平滑用コンデンサ1
4によって平滑されて、1次側直流電源電圧(以下電源
電圧という)となる。15はダイオード5と、吸収用コ
ンデンサ6と、スイッチング素子16及び17とからな
るスパイク電圧吸収回路で、このスパイク電圧吸収回路
15は主トランジスタ1のコレクタ端子に接続されてお
り、スイッチング素子16及び17の可動接点か第3図
に示した位置にあるときには、直流電源のプラス側が低
電位に、主トランジスタ1のコレクタ端子側が高電位に
なって、吸収用コンデンサ6は充電状態になり、スイッ
チング素子16及び17の可動接点が第3図に示した位
置と反対側にあるときには、直流電源のマイナス側が低
電位に、そのプラス側が高電位になって、吸収用コンデ
ンサ6は放電状態になる。(Explanation of Embodiment) FIG. 3 shows the principle of one embodiment of the present invention.
The same reference numerals as those in the figure indicate the same parts, 8 is a commercial AC power supply, 9 is a rectifier diode 10.
11. A rectifier circuit consisting of 12 and 13, and 14 a smoothing capacitor. The AC power supply 8, the rectification circuit 9, and the smoothing capacitor 14 constitute a primary DC power supply (hereinafter referred to as DC power supply). The AC voltage output from 8 is
After being rectified in the rectifier circuit 9, the smoothing capacitor 1
4 to become the primary side DC power supply voltage (hereinafter referred to as power supply voltage). 15 is a spike voltage absorption circuit consisting of a diode 5, an absorption capacitor 6, and switching elements 16 and 17; this spike voltage absorption circuit 15 is connected to the collector terminal of the main transistor 1; When the movable contact of is in the position shown in FIG. When the movable contacts 17 and 17 are on the opposite side from the position shown in FIG. 3, the negative side of the DC power source becomes a low potential, and the positive side becomes a high potential, and the absorption capacitor 6 is placed in a discharged state.
このように構成された本実施例では、吸収用コンデンサ
6の充放電のタイミング、即ち、スイッチング素子16
及び17の切り替わるタイミングは、主トランジスタ1
のスイッチングのタイミングと同期しており、主トラン
ジスタ1がスパイク電圧を発生する遮断時は吸収用コン
デンサ6への充電期間となり、又、主トランジスタ1の
コレクタ端子の電圧が下がる導通時は放電期間となる。In this embodiment configured in this way, the charging/discharging timing of the absorption capacitor 6, that is, the switching element 16
The switching timing of main transistor 1 and 17 is
The switching timing is synchronized with the switching timing, and when the main transistor 1 is cut off and generates a spike voltage, it is a charging period for the absorption capacitor 6, and when the voltage at the collector terminal of the main transistor 1 decreases and it is turned on, it is a discharging period. Become.
即ち、主トランジスタ1が導通しているときには、吸収
用コンデンサ6の一方の端子は直流電源のプラス側に、
吸収用コンデンサ6の他方の端子、は直流電源のマイナ
ス側にそれぞれ接続されるので、吸収用コンデンサ6の
端子間の電位差は、当然、電源電圧と等しくなる。そし
て、主トランジスタ1が遮断された瞬間は、吸収用コン
デンサ6が充電状態に切り替わって、吸収用コンデンサ
6の高電位側の端子が主トランジスタ1のコレクタに接
続され、吸収用コンデンサ6の低電位側の端子が直流電
源のプラス側に接続されるため、吸収用コンデンサ6の
高電位側の端子の電圧は更に電源電圧分だけ上積みされ
て、電源電圧の2倍となる。このとき、主トランジスタ
1は大きなスパイク電圧を発生しようとするが、主トラ
ンジスタ1のコレクタ端子の電圧が電源電圧の2倍まで
上がると、それ以降は吸収用コンデンサ6に充電電流が
流れて、スパイク電圧の上昇は小さく押えられる。従っ
て、吸収用コンデンサ6の両端子間の電位差は、電源電
圧よりやや高い値まで上昇した以降、充電電流が停止す
ると、その値のまま保持される。次に、主トランジスタ
1が再び導通すると、吸収用コンデンサ6が放電状態に
切り替わって、吸収用コンデンサ6の両端子間の電位差
が電源電圧に戻るまで放電され、この放電電流は平滑用
コンデンサ14に流れ込む。詰り、スパイク電圧のエネ
ルギーが直流電源に無損失で帰還されたことになる。こ
の場合、平滑用コンデンサ14の容量は、吸収用コンデ
ンサ6に比べて十分大きいので(通常1ooo倍以上)
、平滑用コンデンサ14の両端子間型位差に与える影響
は無視できる。以」二の動作によって、主トランジスタ
1のコレクタ端子の最大電圧は、電源電圧の2倍よりや
や高い程度の値で押えることができる。例えば、電源電
圧が1.40Vであれば、コレクタ端子での最大電圧は
、140■× 2+α となり、αの値として、第1図
の従来例の説明で用いた30Vを代入すれば、最大電圧
は310vとなる。そこで、この関係を図示すると、第
4図のようになる。但し、第4図から分かるように、主
トランジスタ1の遮断時におけるコレクタ電圧の定常値
が、電源電圧の2倍以上となるような場合には、本発明
は利用できない。換言すると、主トランジスタ1の最大
導通時間比率を172とする必要があることを意味する
。何故ならば、導通時間比率をrで表せば、前述のコレ
クタ電圧の定常値は、電源電圧の1/(1−r)倍とな
るからである。ところで、通常のスイッチング電源装置
では、原理上スイッチング・トランジスタの導通時間比
率は最大1/2であり、大半の製品においてはやや余裕
をとって、最大導通時間比率を40%程度としている。That is, when the main transistor 1 is conducting, one terminal of the absorption capacitor 6 is connected to the positive side of the DC power supply.
Since the other terminals of the absorption capacitor 6 are connected to the negative side of the DC power supply, the potential difference between the terminals of the absorption capacitor 6 is naturally equal to the power supply voltage. At the moment when the main transistor 1 is cut off, the absorption capacitor 6 is switched to a charging state, and the high potential side terminal of the absorption capacitor 6 is connected to the collector of the main transistor 1, and the low potential of the absorption capacitor 6 is connected to the collector of the main transistor 1. Since the side terminal is connected to the positive side of the DC power supply, the voltage at the high potential side terminal of the absorption capacitor 6 is further increased by the power supply voltage, and becomes twice the power supply voltage. At this time, the main transistor 1 tries to generate a large spike voltage, but when the voltage at the collector terminal of the main transistor 1 rises to twice the power supply voltage, a charging current flows to the absorption capacitor 6, causing a spike. The increase in voltage can be kept small. Therefore, after the potential difference between both terminals of the absorption capacitor 6 rises to a value slightly higher than the power supply voltage, when the charging current is stopped, the potential difference is maintained at that value. Next, when the main transistor 1 becomes conductive again, the absorption capacitor 6 switches to a discharge state and is discharged until the potential difference between both terminals of the absorption capacitor 6 returns to the power supply voltage, and this discharge current is transferred to the smoothing capacitor 14. Flow into. This means that the energy of the blockage and spike voltage is fed back to the DC power supply without loss. In this case, the capacitance of the smoothing capacitor 14 is sufficiently larger than that of the absorption capacitor 6 (usually 10oo times or more).
, the influence on the type difference between both terminals of the smoothing capacitor 14 is negligible. By the above second operation, the maximum voltage at the collector terminal of the main transistor 1 can be suppressed to a value slightly higher than twice the power supply voltage. For example, if the power supply voltage is 1.40V, the maximum voltage at the collector terminal is 140×2+α, and if we substitute the 30V used in the explanation of the conventional example in Figure 1 as the value of α, the maximum voltage becomes 310v. Therefore, this relationship is illustrated in FIG. 4. However, as can be seen from FIG. 4, the present invention cannot be used when the steady-state value of the collector voltage when the main transistor 1 is cut off is more than twice the power supply voltage. In other words, this means that the maximum conduction time ratio of the main transistor 1 needs to be 172. This is because, if the conduction time ratio is expressed as r, the steady-state value of the collector voltage mentioned above will be 1/(1-r) times the power supply voltage. By the way, in a normal switching power supply device, in principle, the conduction time ratio of the switching transistor is at most 1/2, and in most products, the maximum conduction time ratio is set to about 40%, with some margin.
従って、上記の1/2以下という条件は実用上、本発明
の適用範囲を狭めるものではないことがわかる。Therefore, it can be seen that the above condition of 1/2 or less does not practically narrow the scope of application of the present invention.
第5図は1本発明の一実施例の具体例を示すもので、第
3図の符号と同一符号のものは同一部分を示しており、
又、18は、主トランジスタ1の制御信号を偏移させた
バイアス電圧を信号として出力するバイアス変換回路1
9と、コレクタをダイオード5と吸収用コンデンサ6と
の間に接続し、エミッタを直流電源のプラス側に接続し
、ベースをバイアス変換回路19に接続した、スイッチ
ング素子として機能する放電用トランジスタ2oと、吸
収用コンデンサ6と直流電源のプラス側との間に接続し
たダイオード21と、吸収用コンデンサ6と直流電源の
マイナス側との間に接続したダイオード22とからなる
スパイク電圧吸収回路で、主トランジスタ1と放電用ト
ランジスタ20とは同時に導通或いは遮断するように動
作する。FIG. 5 shows a specific example of one embodiment of the present invention, and the same reference numerals as those in FIG. 3 indicate the same parts.
Further, 18 is a bias conversion circuit 1 that outputs a bias voltage obtained by shifting the control signal of the main transistor 1 as a signal.
9 and a discharge transistor 2o functioning as a switching element, the collector of which is connected between the diode 5 and the absorption capacitor 6, the emitter connected to the positive side of the DC power supply, and the base connected to the bias conversion circuit 19. , a spike voltage absorption circuit consisting of a diode 21 connected between the absorption capacitor 6 and the positive side of the DC power supply, and a diode 22 connected between the absorption capacitor 6 and the negative side of the DC power supply. 1 and the discharging transistor 20 operate to conduct or cut off simultaneously.
このように構成された本具体例では、主トランジスタ1
が遮断されているときには、吸収用コンデンサ6の高電
位側の端子がダイオード5を介して主トランジスタ1の
コレクタに接続されると共に、吸収用コンデンサ6の低
電位側の端子がダイオード21を介して直流電源のプラ
ス側に接続されて、吸収用コンデンサ6が充電状態にな
り、スパイク電圧が吸収用コンデンサ6に充電される。In this specific example configured in this way, the main transistor 1
is cut off, the high potential side terminal of the absorption capacitor 6 is connected to the collector of the main transistor 1 via the diode 5, and the low potential side terminal of the absorption capacitor 6 is connected via the diode 21 to the collector of the main transistor 1. Connected to the positive side of the DC power source, the absorption capacitor 6 is placed in a charged state, and the absorption capacitor 6 is charged with a spike voltage.
又、主トランジスタ1が導通しているときには、吸収用
コンデンサ6の一方の端子は放電用トランジスタ20を
介して直流電源のプラス側に接続されると共に、吸収用
コンデンサ6の他方の端子はダイオード22を介して直
流電源のマイナス側に接続されて、吸収用コンデンサ6
が放電状態になり、吸収用コンデンサ6の両端子間の電
位差が電源電圧に戻るまで放電され、この放電電流は平
滑用コンデンサ14に流れ込む。但し、このスパイク電
圧吸収回路18では、ダイオード5,21.22の順方
向電圧降下及び放電用トランジスタ20のコレクタ、エ
ミッタ間の飽和電圧によって多少の損失が発生するが、
従来の方式による本質的な損失と比較すれば、極めて小
さい。又、放電用トランジスタ20は、比較的小容1
(0,01〜0.1pF)の吸収用コンデンサ6の放電
を行うだけなので、許容コレクタ損失の小さいものでも
よい。When the main transistor 1 is conductive, one terminal of the absorption capacitor 6 is connected to the positive side of the DC power supply via the discharge transistor 20, and the other terminal of the absorption capacitor 6 is connected to the diode 22. is connected to the negative side of the DC power supply through the absorption capacitor 6.
enters a discharge state and is discharged until the potential difference between both terminals of the absorption capacitor 6 returns to the power supply voltage, and this discharge current flows into the smoothing capacitor 14. However, in this spike voltage absorption circuit 18, some loss occurs due to the forward voltage drop of the diodes 5, 21, 22 and the saturation voltage between the collector and emitter of the discharge transistor 20.
This is extremely small compared to the essential loss caused by conventional methods. Further, the discharge transistor 20 has a relatively small capacity 1
(0.01 to 0.1 pF) since the absorption capacitor 6 is simply discharged, a capacitor with a small allowable collector loss may be used.
(発明の効果)
以上説明したように、本発明によれば、スパイク電圧吸
収回路を吸収用コンデンサとスイッチとで構成し、且つ
、充電時と放電時とで電流の経路が切り換わるように吸
収用コンデンサを接続することによって、損失を発生す
ることなくスパイク電圧によるエネルギーを電源に帰還
することができるると共に、スパイク波形の制限電圧を
電源電圧の2倍付近に設定できる利点がある。又、損失
が低減されたことにより、スイッチング電源自体の小型
化や、放熱設計の簡素化ができる利点がある。(Effects of the Invention) As explained above, according to the present invention, the spike voltage absorption circuit is configured with an absorption capacitor and a switch, and the spike voltage absorption circuit is configured such that the current path is switched between charging and discharging. By connecting the power supply capacitor, the energy due to the spike voltage can be fed back to the power supply without causing loss, and there is an advantage that the limit voltage of the spike waveform can be set to approximately twice the power supply voltage. Furthermore, since the loss is reduced, there are advantages in that the switching power supply itself can be made smaller and the heat dissipation design can be simplified.
第1図は従来のスパイク電圧吸収回路の構成図、第2図
は従来のスパイク電圧吸収回路の各部の出力波形図、第
3図は本発明の一実施例の原理図、第4図は本発明の一
実施例の各部の出力波形図、第5図は本発明の一実施例
の具体例の構成図である。
1 ・・ 主トランジスタ、 5,2]、22甲ダイオ
ード、 6 ・・・吸収用コンデンサ、16、17・・
・スイッチング素子(20・・・放電用トランジスタ)
。
特許出願人 松下電器産業株式会社
第1図
第2図
第3図
・15
第4図Fig. 1 is a configuration diagram of a conventional spike voltage absorption circuit, Fig. 2 is an output waveform diagram of each part of the conventional spike voltage absorption circuit, Fig. 3 is a principle diagram of an embodiment of the present invention, and Fig. 4 is a diagram of the present invention. FIG. 5 is a diagram showing the output waveforms of each part of an embodiment of the invention. FIG. 5 is a configuration diagram of a specific example of an embodiment of the invention. 1... Main transistor, 5, 2], 22K diode, 6... Absorption capacitor, 16, 17...
・Switching element (20...discharge transistor)
. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3/15 Figure 4
Claims (4)
イッチングする主トランジスタのコレクタに現れるスパ
イク電圧を吸収して、前記主トランジスタを保護するス
パイク電圧吸収回路において、前記主トランジスタのコ
レクタ端子に発生したスパイク電圧を充電、吸収する吸
収用コンデンサが具備され、前記スパイク電圧を充電す
るときには、前記吸収用コンデンサが1次側直流電源の
高電位側端子と前記主トランジスタのコレクタ端子の間
に接続され、前記吸収用コンデンサから放電するときに
は、前記吸収用コンデンサが前記1次側直流電源の低電
位側端子と前記1次側直流電源の高電位側端子との間に
接続されるように、前記吸収用コンデンサの接続をスイ
ッチング素子によって切り換えることを特徴とするスパ
イク電圧吸収回路。(1) In a spike voltage absorption circuit that protects the main transistor by absorbing the spike voltage appearing at the collector of the main transistor that switches the primary side DC power supply voltage of the switching power supply device, the spike voltage generated at the collector terminal of the main transistor An absorption capacitor that charges and absorbs a spike voltage is provided, and when charging the spike voltage, the absorption capacitor is connected between a high potential side terminal of the primary side DC power supply and a collector terminal of the main transistor, When discharging from the absorption capacitor, the absorption capacitor is connected between the low potential side terminal of the primary side DC power supply and the high potential side terminal of the primary side DC power supply. A spike voltage absorption circuit characterized by switching the connection of a capacitor using a switching element.
に設定されることを特徴とする特許請求の範囲第(1)
項記載のスパイク電圧吸収回路。(2) Claim (1) characterized in that the conduction time ratio of the main transistor is set to 1/2 or less.
Spike voltage absorption circuit as described in section.
トランジスタのコレクタ端子に接続し、カソード端子を
前記吸収用コンデンサの一方の端子と接続した第1のダ
イオードと、アノード端子を前記吸収用コンデンサの他
方の端子と接続し、カソード端子を前記1次側直流電源
の高電位側の端子と接続した第2のダイオードと、アノ
ード端子を前記1次側直流電源の低電位側の端子と接続
し、カソード端子を前記吸収用コンデンサと前記第2の
ダイオードとの接続点に接続した第3のダイオードと、
前記第1のダイオードと前記吸収用コンデンサとの接続
点と前記1次側電源電圧の高電位側の端子との間に設置
された前記スイッチング素子とで構成された回路によっ
て充放電が制御されることを特徴とする特許請求の範囲
第(1)項記載のスパイク電圧吸収回路。(3) The absorption capacitor includes a first diode whose anode terminal is connected to the collector terminal of the main transistor and whose cathode terminal is connected to one terminal of the absorption capacitor, and a first diode whose anode terminal is connected to the collector terminal of the main transistor. a second diode connected to the other terminal, the cathode terminal of which is connected to the high potential side terminal of the primary DC power source, and the anode terminal connected to the low potential side terminal of the primary DC power source; a third diode whose cathode terminal is connected to a connection point between the absorption capacitor and the second diode;
Charging and discharging are controlled by a circuit configured with the switching element installed between a connection point between the first diode and the absorption capacitor and a terminal on the high potential side of the primary power supply voltage. A spike voltage absorption circuit according to claim (1).
制御信号によって制御されることを特徴とする特許請求
の範囲第(2)項記載のスパイク電圧吸収回路。(4) The spike voltage absorption circuit according to claim (2), wherein the switching element is controlled by a control signal of the main transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15916784A JPS6142274A (en) | 1984-07-31 | 1984-07-31 | Spike voltage absorbing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15916784A JPS6142274A (en) | 1984-07-31 | 1984-07-31 | Spike voltage absorbing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6142274A true JPS6142274A (en) | 1986-02-28 |
JPH0313830B2 JPH0313830B2 (en) | 1991-02-25 |
Family
ID=15687735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15916784A Granted JPS6142274A (en) | 1984-07-31 | 1984-07-31 | Spike voltage absorbing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6142274A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS637993U (en) * | 1986-06-27 | 1988-01-19 | ||
JPS6333379U (en) * | 1986-08-20 | 1988-03-03 | ||
JPS6439268A (en) * | 1987-07-31 | 1989-02-09 | Toko Inc | Switching power circuit |
WO2014174626A1 (en) * | 2013-04-25 | 2014-10-30 | 日立オートモティブシステムズ株式会社 | Electromagnetic coil driving control device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8668651B2 (en) | 2006-12-05 | 2014-03-11 | Covidien Lp | ECG lead set and ECG adapter system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5869463A (en) * | 1981-10-21 | 1983-04-25 | Nec Corp | Current snubber circuit |
-
1984
- 1984-07-31 JP JP15916784A patent/JPS6142274A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5869463A (en) * | 1981-10-21 | 1983-04-25 | Nec Corp | Current snubber circuit |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS637993U (en) * | 1986-06-27 | 1988-01-19 | ||
JPS6333379U (en) * | 1986-08-20 | 1988-03-03 | ||
JPH0537670Y2 (en) * | 1986-08-20 | 1993-09-22 | ||
JPS6439268A (en) * | 1987-07-31 | 1989-02-09 | Toko Inc | Switching power circuit |
WO2014174626A1 (en) * | 2013-04-25 | 2014-10-30 | 日立オートモティブシステムズ株式会社 | Electromagnetic coil driving control device |
JP6066531B2 (en) * | 2013-04-25 | 2017-01-25 | 日立オートモティブシステムズ株式会社 | Electromagnetic coil drive control device |
US10002699B2 (en) | 2013-04-25 | 2018-06-19 | Hitachi Automotive Systems, Ltd. | Electromagnetic coil driving control device |
Also Published As
Publication number | Publication date |
---|---|
JPH0313830B2 (en) | 1991-02-25 |
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