JPH05336737A - Rush current suppressing circuit - Google Patents

Abstract

PURPOSE:To suppress rush current generated at the time of switch on, concerning to a rush current suppressing circuit for a DC/DC converter. CONSTITUTION:In a DC/DC converter which obtains DC voltage at a smoothing capacitor CL turning DC voltage on and off with a switch SW, a current suppressing circuit 1 which is connected in series to a circuit and suppresses rush current in the circuit when the switch SW is turned on, an operation delaying capacitor C1 for the current suppressing circuit 1, and a forced discharging circuit 2 which forcedly discharges a accumulated in the operation delaying capacitor C1 when the switch SW is off, are provided to constitute the title rush current suppressing circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rush current suppressing circuit for a DC / DC converter.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration example of a conventional circuit. The DC voltage Ei, the smoothing capacitor CL, the field effect transistor (FET) TR1 and the switch SW1 form a loop. When the switch SW1 is turned on and off in a constant cycle, charges are accumulated in the smoothing capacitor CL and a voltage is generated. The voltage applied across the capacitor CL becomes the output voltage and supplies power to the load RL.

Resistor R1, resistor R2, transistor TR1
The zener diode D1 constitutes a rush input current suppressing portion. C1 is an operation delay capacitor. A charging circuit is formed by the resistor R2 and the capacitor C1, and the resistor R1
And the capacitor C1 form a discharge circuit. The Zener diode D1 clamps the gate-source voltage VGS of the transistor TR1 at a certain value (Zener voltage) or less so that the transistor TR1 is not broken down. The operation of the circuit thus configured will be described below.

When the switch SW is turned on, the above loop circuit is formed. At this time, the charging circuit composed of the resistor R2 and the capacitor C1 operates, and the voltage of the capacitor C1 increases with the time constant R2 · C1. This capacitor C
The voltage between both ends of 1 is applied between the gate and source of the transistor TR1, and the resistance of the transistor TR1 is large at first and becomes small with the passage of time. Therefore, the current ID of the loop circuit does not suddenly increase at the moment when the switch SW is turned on. At this time, charges are accumulated in the smoothing capacitor CL.

Next, when the switch SW is turned off, the discharge circuit composed of the operation delay capacitor C1 and the resistor R1 discharges with the discharge time constant R1.C1. Then, when the voltage across the capacitor C1 becomes equal to or lower than the off voltage of the transistor TR1, the transistor TR1 is turned off. In this way, the switch SW is repeatedly turned on and off, so that the output voltage VO is generated in the smoothing capacitor CL.

[0006]

However, the circuit shown in FIG. 4 has the following problems. This will be described with reference to the time chart of FIG. In FIG. 5, (a) shows the operation of the switch SW, (b) shows the gate-source voltage VGS of the transistor TR1, and (c) shows the circuit current (current flowing between the drain and source of the transistor TR1) I.
D is shown respectively.

When the switch SW is turned on at time t1,
Until then, the transistor TR1 is in the off state and its resistance is large. Therefore, at the moment when the switch SW is turned on, the current flowing through the circuit is not so large as shown in (c). On the other hand, the charging circuit composed of the resistor R2 and the capacitor C1 charges with the time constant of R2 · C1. As a result, the voltage across the capacitor C1 (again, the gate-source voltage VGS of the transistor TR1) gradually increases as shown in (b). In response to this, the on-resistance of the transistor TR1 gradually decreases.

Here, it is assumed that the switch SW is turned off at time t2. This time, the discharge circuit composed of the resistor R1 and the capacitor C1 discharges with the time constant R1 · C1. However, since the discharge resistor R1 cannot be made extremely small, the discharge curve becomes extremely gentle as indicated by A in (b). Therefore, VGS cannot be made sufficiently small within the ON / OFF cycle of the switch SW. As a result, the transistor TR1 is in the on state even while the switch SW is off.

When the switch SW is turned on again at the time t3, the loop circuit applies the voltage Ei to the series circuit of the ON resistance Ron of the transistor TR1 and the capacitor CL, which is relatively small, and is represented by the following equation. A current ID that flows as described above flows.

ID = (Ei-VO) / Ron In this equation, the current ID becomes a large current because Ron is relatively small. B in (c) of the figure shows this inrush current. Due to this inrush current, there is a problem that the contact of SW sticks or the transistor TR1 is destroyed.

The present invention has been made in view of the above problems, and an object thereof is to provide an inrush current suppressing circuit capable of suppressing an inrush current generated when a switch is turned on.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, SW is a switch for turning on / off the DC voltage Ei, CL is a smoothing capacitor, 1 is a series connection with the circuit, and a current suppressing circuit for suppressing an inrush current flowing in the circuit when the switch SW is on, and C1 are The operation delay capacitor 2 of the current suppressing circuit 1 is a forced discharge circuit for forcibly discharging the electric charge accumulated in the operation delay capacitor C1 when the switch SW is off.

[0013]

When the switch SW is off, the forced discharge circuit 2 rapidly discharges the voltage across the operation delay capacitor C1. As a result, the resistance connected in series to the circuit of the current suppressing circuit 1 becomes sufficiently large. Then, when the switch SW is turned on, the current suppressing circuit 1 gradually reduces the resistance connected in series to the circuit from a sufficiently large state. As described above, according to the present invention, it is possible to suppress the inrush current generated when the switch is turned on.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is an electric circuit diagram showing an embodiment of the present invention. The same parts as those in FIGS. 1 and 4 are designated by the same reference numerals. The current suppression circuit 1 is the same as that of FIG.
1, R2, Zener diode D1 and transistor T
It is composed of R1. The forced discharge circuit 2 is composed of a transistor TR2, a diode D2 and a resistor R3.

The diode D2 is connected in series with the operation delay capacitor C1, and is connected to the transistor TR2 and the resistor R3.
Is connected in parallel with the capacitor C1.
The base of the transistor TR2 is connected to the anode of the diode D2, and the emitter of the transistor TR2 is connected to the cathode. And the collector is a resistor R3
It is connected to the. The diode D2 functions as a reverse current element diode. The other end of the resistor R3 is connected to the common line. The operation of the circuit thus configured will be described below with reference to the time chart of FIG.

First, it is assumed that the switch SW is turned on at time t1 as shown in (a). As a result, a loop circuit is formed. At this time, the charging circuit including the resistor R2 and the capacitor C1 is charged with the electric charge with the time constant of R2 · C1. As a result, the voltage across the capacitor C1 (equal to the gate-source voltage VGS of the transistor TR1) gradually increases as shown in (b). As a result, the on-resistance of the transistor TR2 gradually decreases from a sufficiently large state. Therefore, the circuit current ID
As shown in (c), does not increase significantly even when the switches are switched, and then takes a constant value.

When the switch SW is turned off at time t2, the loop circuit is disconnected. On the other hand, at this time, a voltage is generated across the capacitor C1. This voltage turns on the transistor TR2. As a result,
The electric charge of the capacitor C1 is consumed by the resistor R3, and its voltage rapidly becomes 0 as shown by C in (b). Therefore, the transistor TR1 which receives this voltage as VGS is completely turned off.

When the switch SW is turned on at time t3 while the transistor TR1 is completely off, a loop is formed. However, since the off resistance of the transistor TR1 is sufficiently large, the resistance of the transistor TR1 is sufficient. From a very large state, it gradually becomes smaller as VGS increases. Therefore, as shown by D in (c), a large inrush current does not flow.

By turning the switch SW on and off in this manner, a constant DC voltage VO is generated in the smoothing capacitor CL, and power is supplied to the load RL. The value VO of the DC voltage can be arbitrarily set by changing the switching on / off ratio (duty ratio) shown in (a).

In the above-mentioned embodiments, the case where the field effect transistor (FET) is used as the active element of the current suppressing circuit 1 is taken as an example. However, the present invention is not limited to this, and other types of active elements such as normal bipolar transistors can be used. Further, the transistor TR2 in the forced discharge circuit 2 is also the PN shown in the embodiment.
Not only P-type transistors but NPN-type transistors can be used. Also, a FET can be used.

[0021]

As described above in detail, according to the present invention, it is possible to provide the inrush current suppressing circuit capable of suppressing the inrush current generated when the switch is turned on.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an electric circuit diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment.

FIG. 4 is a diagram showing a configuration example of a conventional circuit.

FIG. 5 is a time chart showing the operation of a conventional circuit.

[Explanation of symbols]

 1 Current Suppression Circuit 2 Forced Discharge Circuit C1 Operation Delay Capacitor CL Smoothing Capacitor RL Load SW Switch

Claims (5)

[Claims] 1. A DC / DC for obtaining a DC voltage in a smoothing capacitor (CL) by turning on / off the DC voltage with a switch (SW).
In a DC converter, a current suppressing circuit (1) that is connected in series to the circuit and suppresses an inrush current flowing in the circuit when a switch (SW) is turned on, and an operation delay capacitor (1) for the current suppressing circuit (1) ( C1)
And a forced discharge circuit (2) for forcibly discharging the charge accumulated in the operation delay capacitor (C1) when the switch (SW) is off. 2. When the switch (SW) is turned on,
The inrush current suppressing circuit according to claim 1, wherein the current suppressing circuit (1) is configured such that its resistance is gradually reduced from a sufficiently large state to suppress the inrush current. 3. The forced discharge circuit (2) is provided with an operation delay capacitor (C) while the switch (SW) is off.
The electric charge accumulated in 1) is forcibly discharged, and the series resistance of the current suppressing circuit (1) is completely turned off so that the next switch (SW) is turned on. Item 2. The inrush current suppressing circuit according to item 2. 4. The current suppressing circuit (1) comprises a field effect transistor (TR1) connected in series to the circuit, and a drive circuit for the field effect transistor. Inrush current suppression circuit. 5. The inrush current suppressing circuit according to claim 1, wherein the forced discharge circuit (2) is configured to short-circuit both ends of the operation delay capacitor (C1) with a transistor (TR2).