JPS614226A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS614226A JPS614226A JP12577284A JP12577284A JPS614226A JP S614226 A JPS614226 A JP S614226A JP 12577284 A JP12577284 A JP 12577284A JP 12577284 A JP12577284 A JP 12577284A JP S614226 A JPS614226 A JP S614226A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、特に従来より遥に低温
度の液相エピタキンヤル成長方法によって、m−v族化
合物半導体のn型及びp型の伝導層を形成する製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method for manufacturing semiconductor devices, in particular, a method for manufacturing n-type and p-type m-v group compound semiconductors using a liquid phase epitaxial growth method at a much lower temperature than conventional methods. The present invention relates to a manufacturing method for forming a conductive layer.
■−v族化合物半導体が光半導体装置及び電子回路装置
に広く用いられており、これらの半導体装置に必要な、
化合物の組成、導電型或いは不純物濃度等が選択された
半導体層の組合わせ構造が液相エピタキシャル成長方法
(以下LPE法と略称する)によってしばしば形成され
ている。■-V group compound semiconductors are widely used in optical semiconductor devices and electronic circuit devices, and the
A combination structure of semiconductor layers whose compound composition, conductivity type, impurity concentration, etc. are selected is often formed by a liquid phase epitaxial growth method (hereinafter abbreviated as LPE method).
しかしながらLPE法は高温プロセスであって、結晶を
成長させる半導体基体の劣化を招き易く、種々の対策が
既に提供されているが、プロセス温度の低下が最も望ま
しい。However, the LPE method is a high-temperature process and tends to cause deterioration of the semiconductor substrate on which crystals are grown.Although various countermeasures have already been provided, it is most desirable to lower the process temperature.
■−v族化合物半導体、例えばガリウム砒素/ガリウム
アルミニウム砒素(GaAs/GaAA’As )やイ
ンジウム燐/インジウムガリウム砒素燐(InP/I
nGaAsP )などを用いた半導体レーザ等において
は、LPE法が多く適用されているがその従来例を第2
図に示す工程順断面図を参照して説明する。■-V group compound semiconductors, such as gallium arsenide/gallium aluminum arsenide (GaAs/GaAA'As) and indium phosphorous/indium gallium arsenide phosphorous (InP/I
The LPE method is often applied to semiconductor lasers using materials such as nGaAsP (nGaAsP ).
Description will be given with reference to step-by-step sectional views shown in the figures.
第2図(a)参照
n型InP基板1上に、n型InP閉じ込め層2゜p型
InGaAsP活性層3+ PmInP閉じ込め層4
及びp m InGaAsP コyタクト層5をLPE
法によって順次連続して成長する。Refer to FIG. 2(a) On an n-type InP substrate 1, an n-type InP confinement layer 2゜p-type InGaAsP active layer 3 + PmInP confinement layer 4 is formed.
and p m InGaAsP coytact layer 5 by LPE
It grows sequentially and continuously according to the law.
ただし成長溶液の溶媒はイ/ジクム(In)であって、
成長開始温度は600℃程度である。However, the solvent of the growth solution is I/Dicum (In),
The growth starting temperature is about 600°C.
第2図(b)参照
p型InGaAsPコンタクト層5上に二酸化シリry
(SiCh)等によってストライブ状のマスク6を形成
する。Refer to FIG. 2(b). Silicon dioxide ry is deposited on the p-type InGaAsP contact layer 5.
A striped mask 6 is formed using (SiCh) or the like.
このマスク6によって、図に示す如き逆メサストライプ
を形成するエツチングを行なう。Using this mask 6, etching is performed to form reverse mesa stripes as shown in the figure.
第2図(c)参照
第2回目のLPE成長を行なって、p型InPH7及び
n型InP層8を形成する。この第2回目のLPE成長
も第1回目のLPE成長と同様に、Inを溶媒とし成長
開始温度は600℃程度であるO
これらのInP層7及び8はレーザの横モードを制御す
る屈折率ガイディングと、np逆接合によって電流を阻
止する電流狭窄とを目的として設けられてお蜘、本例の
構造は埋め込みストライプ構造と呼ばれている。Referring to FIG. 2(c), a second LPE growth is performed to form a p-type InPH layer 7 and an n-type InP layer 8. Similar to the first LPE growth, this second LPE growth also uses In as a solvent and the growth start temperature is about 600°C. The structure of this example is called a buried stripe structure.
−この構造を実現するために上述の如く通常2回のLP
E成長が行なわれており、これらの2回のLPE成長は
従来、いずれもInを溶媒として成長開始温度600℃
程度としている。- To realize this structure, two LPs are usually required as described above.
E growth is performed, and these two LPE growths were conventionally performed at a growth start temperature of 600°C using In as a solvent.
It is said that the amount of
LPE法では所定量の溶質を溶媒に溶解し、かつ熱的平
衡状態を形成するために、基体及び溶液を成長開始温度
以上の温度に20〜40分程度保程度ることが必要であ
る。In the LPE method, in order to dissolve a predetermined amount of solute in a solvent and to form a thermal equilibrium state, it is necessary to maintain the substrate and solution at a temperature equal to or higher than the growth initiation temperature for about 20 to 40 minutes.
前記の逆メサエツチング後のM2回目のLPE成長の際
のこの高温保持によって、半導体基体の表出面の近傍に
熱損傷を生じ、埋め込み構造の内部に第2図(c)にX
印で示す如く多くの結晶欠陥を導入することになる。Due to this high temperature maintenance during the second M LPE growth after the reverse mesa etching described above, thermal damage occurs near the exposed surface of the semiconductor substrate, and an X as shown in FIG.
Many crystal defects will be introduced as shown by the marks.
と力らの結晶欠陥は、とのレーザの動作中の洩れ電流を
大幅に増加させ、またいわゆるダークリージョン(発光
暗部)が成長する劣化の原因の一つとなって、その特性
を著しく悪くしている。These crystal defects significantly increase the leakage current during operation of the laser, and are one of the causes of deterioration in which the so-called dark region (emission dark area) grows, significantly deteriorating its characteristics. There is.
この状況を改善するために従来、例えば燐(P)の分離
を抑制するために基体表出面にP圧を加えるなどの処置
が試みられているが、所要の効果を得るに至らない。Conventionally, attempts have been made to improve this situation by, for example, applying P pressure to the exposed surface of the substrate in order to suppress the separation of phosphorus (P), but these efforts have not resulted in the desired effect.
前記の熱損傷を抑制するためKは、LPE成長温度を出
来るだけ下けることが望ましい。しかしながらIn、或
いはGa等の■族金属を溶媒とする従来のLPE成長法
では、その溶解度の点から低温化には限界があり、Ga
As系では700℃以上、InP系では550℃以上が
成長可能温度と考えられている。In order to suppress the thermal damage described above, it is desirable for K to lower the LPE growth temperature as much as possible. However, in the conventional LPE growth method using group Ⅰ metals such as In or Ga as a solvent, there is a limit to lowering the temperature due to the solubility of the metals.
It is considered that the growth temperature is 700° C. or higher for As-based materials, and 550° C. or higher for InP-based materials.
これより成長温度を低下することができるLPE法とし
ては、錫(Sn)を溶媒とする方法が既に知られている
。しかし乃、がらIII−V族化合物牛導体について5
nid通常ドナー不純物として作用し、Sn溶媒からエ
ピタキシャル成長した■−■族半導体は通常n型となり
、p型半導体結晶を成長することは不可能である。As an LPE method capable of lowering the growth temperature, a method using tin (Sn) as a solvent is already known. However, regarding III-V group compound conductors 5.
nid usually acts as a donor impurity, and a ■-■ group semiconductor epitaxially grown from an Sn solvent usually becomes n-type, making it impossible to grow a p-type semiconductor crystal.
〔発明が解決しようとする問題点3
以上説明した如く、■−V族化合物半導体基体上へのp
型伝導層のLPE成長を、該基体に#損′傷を与えるこ
となく行なうことは不可能な状況にあり、前記埋め込み
ストライプ構造静置ついてこの問題点の解決が強く要望
されている。[Problem 3 to be solved by the invention As explained above,
It is currently impossible to perform LPE growth of a type conductive layer without causing damage to the substrate, and there is a strong demand for a solution to this problem with respect to the buried stripe structure.
前記問題点は、n型■−■族化合物半導体結晶を、錫を
溶媒とし、該化合物を構成する元素とH族元素とを溶質
とする液相エピタキシャル成長方法によって成長し、該
半導体結晶に隣接する半導体結晶内に該H族元素を拡散
してp型頭域を形成する工程を含む本発明による半導体
装置の製造方法によ抄解決される。The problem is that an n-type ■-■ group compound semiconductor crystal is grown by a liquid phase epitaxial growth method using tin as a solvent and an element constituting the compound and an H group element as a solute. This problem is solved by a method for manufacturing a semiconductor device according to the present invention, which includes a step of diffusing the H group element into a semiconductor crystal to form a p-type head region.
本発明においては、化合物半導体結晶を構成するm族及
びV族元素に対して大きい溶解度が低温で得られる錫を
溶媒とし、かつ■−V族化合物半導体結晶に対してアク
セプタ不純物として機能するH族元素、例えば亜鉛、カ
ドミウム又はマグネンウムを溶質として相当量添加する
。In the present invention, the solvent is tin, which has high solubility at low temperatures for the M group and V group elements constituting the compound semiconductor crystal, and the H group element, which functions as an acceptor impurity for the -V group compound semiconductor crystal. Substantial amounts of elements such as zinc, cadmium or magnenium are added as solutes.
この溶液を用いることによって、半ふ体基体上の自然酸
化層の除去効果を考慮しても、成長温度を400℃程度
1で低下することができる。By using this solution, the growth temperature can be lowered by about 400.degree. C.1 even when the effect of removing the natural oxide layer on the semi-solid substrate is considered.
このLPE成長層の導電型は多量の錫が不純物として含
まれるためにn型であるが、前述のH族元素もLPE成
長層に含まれてこれを隣接する半導体基体等に熱拡散さ
せることによって、n型成長層に接してp型伝導層を形
成することができる。The conductivity type of this LPE growth layer is n-type because it contains a large amount of tin as an impurity, but the above-mentioned H group elements are also contained in the LPE growth layer and are thermally diffused into the adjacent semiconductor substrate. , a p-type conductive layer can be formed in contact with the n-type growth layer.
前記熱拡散には例えば600℃程度の、従来の■族元素
を溶媒とするLPE成長温度とほぼ′等しい温度が必要
であるが、半導体装置の特性及び信頼性上重要な領域が
表出しないために、熱損傷による特性及び信頼性の劣化
が防止される。The thermal diffusion requires a temperature of approximately 600° C., which is approximately the same as the conventional LPE growth temperature using group Ⅰ elements as a solvent, but this does not expose areas important for the characteristics and reliability of the semiconductor device. In addition, deterioration of characteristics and reliability due to thermal damage is prevented.
以下本発明を第1図に工程順断面図を示す実施例により
具体的に説明する。The present invention will be specifically explained below with reference to an embodiment shown in FIG.
第1図(a)参照
前記従来例と同様に、n型InP基板1上に次の各半導
体J@2〜5をLPE法によって順次連続して成長する
。なお成長溶液の溶媒はInで、成長開始温度600℃
としている。Refer to FIG. 1(a) Similar to the conventional example, the following semiconductors J@2 to 5 are sequentially grown on an n-type InP substrate 1 by the LPE method. The solvent of the growth solution was In, and the growth starting temperature was 600°C.
It is said that
2は錫(S n)をi x t O”crIL−’程度
にドープし厚さ約1μmのn型InP閉じ込め層、3は
亜鉛(Zn)をlX1017儂−3程度にドープし、厚
さ約0.1μm媛 °”””°゛°0°°°°
°”°°°゛0.35fg性層、4はZnを5X10′
7σ−3程度にドープし、厚さ約1.5μmのp型In
P閉じ込め層、5はZnをI X 10 ”cm−’程
度にドープし、厚さ約0.5μmのp型In O,70
Ga O,304a O,65Po、3.5 :yンタ
クトーである。2 is an n-type InP confinement layer doped with tin (S n) to about ix t O"crIL-' and has a thickness of about 1 μm; 3 is an n-type InP confinement layer doped with zinc (Zn) to about lX1017 儂-3 and has a thickness of about 1 μm. 0.1 μm 媛 °”””°゛°0°°°°
°"°°°゛0.35fg layer, 4 Zn 5X10'
P-type In doped to about 7σ-3 and about 1.5 μm thick
The P confinement layer 5 is made of p-type InO doped with Zn to about I x 10 cm-' and has a thickness of about 0.5 μm, 70
Ga O,304a O,65Po,3.5 :y intact.
第1図(b)参照
p型InGaAsPコンタクト層5上にSin、等の皮
膜をスパッタ法などによって被着し、リングラフィ法に
よって例えば幅35μm程度のストライプ状のマスク6
を形成する。Refer to FIG. 1(b). A film such as Sin is deposited on the p-type InGaAsP contact layer 5 by sputtering or the like, and a striped mask 6 having a width of about 35 μm, for example, is formed by phosphorography.
form.
臭X(Br)のメタノール溶液によるエツチングを行な
い、図に示す如き逆メサストライプを形成する。Etching is performed using a methanol solution of odor X (Br) to form an inverted mesa stripe as shown in the figure.
第1図(c)参照
第2回目のLPE成長を行なって、n型InP原子分率
とし、この溶液及び前記半導体基体を温度460℃に約
30分間保持した後に温度440℃で成長を開始してい
る。Refer to FIG. 1(c). A second LPE growth was performed to obtain an n-type InP atomic fraction, and after holding this solution and the semiconductor substrate at a temperature of 460°C for about 30 minutes, growth was started at a temperature of 440°C. ing.
このLPE成長によって得られたInP層9は、キャリ
ア濃度が約8X1g+aσ−3のn型である。The InP layer 9 obtained by this LPE growth is n-type with a carrier concentration of approximately 8×1g+aσ-3.
第1図(d)参照
前記半導体基体に例えば温度600℃2時間20分間程
度の熱処理を行なって、InP埋め込み層9に含まれて
いるZ、nを拡散させる。このZn拡散によって11型
InP層2内にp型領域10が形成される。本実施例で
はp型領域10の深さは約05μm1閉じ込め層9側の
界面におけるキャリア濃度はlXl0”儒−3程度であ
る。Refer to FIG. 1(d). The semiconductor substrate is subjected to heat treatment at a temperature of 600° C. for about 2 hours and 20 minutes, for example, to diffuse Z and n contained in the InP buried layer 9. A p-type region 10 is formed in the 11-type InP layer 2 by this Zn diffusion. In this embodiment, the depth of the p-type region 10 is about 05 μm, and the carrier concentration at the interface on the side of the confinement layer 9 is about 1×10”f−3.
第1図(e)参照
基板1裏面の研摩等によってその厚さを湖<シた後にn
0Ill電極11を例えば金・錫(Au−8矛)合金
によ絵、マたp9Ill電極12を例えばチタン/白金
/金(T i/p t/A−u )によって形成し、襞
間等を行なって本実施例の製造を終る。Figure 1(e) After reducing the thickness of the back surface of the reference substrate 1 by polishing, etc.
The 0Ill electrode 11 is made of, for example, a gold-tin (Au-8) alloy, and the p9Ill electrode 12 is made of, for example, titanium/platinum/gold (Ti/pt/A-u), with gaps between the folds, etc. This completes the manufacturing of this embodiment.
前記拡散処理によって半導体基体の表出面近傍では熱損
傷を受けるが、予め保護膜を設け、或いは損傷層を除去
することも容易に可能であって、素子特性には影響し々
い。Although the diffusion process causes thermal damage in the vicinity of the exposed surface of the semiconductor substrate, it is easily possible to provide a protective film in advance or remove the damaged layer, which does not significantly affect the device characteristics.
半導体基体内部の、従来問題であった埋め込みノーとの
界面は、埋め込み成長温度が450℃程度に低下するた
めに熱伊傷は無視できる程度に抑制されて、例えば本実
施例と相当する前記従来例とを比較して、閾値電流が約
40mAから約25mAに減少[2、発光効率が片面に
ついて約020から約0.40に増大するなど、優れた
特性が得られる。Since the embedding growth temperature is lowered to about 450° C. at the interface with the embedding hole inside the semiconductor substrate, which has been a problem in the past, thermal damage is suppressed to a negligible level. In comparison with the example, excellent characteristics are obtained such that the threshold current decreases from about 40 mA to about 25 mA [2] and the luminous efficiency increases from about 0.20 to about 0.40 on one side.
以上の説明はInP/InGaA8P系レーザを対象と
しているが、半導体材料はこれに限られるものでけ々く
、■=V族化合物半導体の何れにも本発明を適用す2)
ことができ、またレーザその他の光半導体装置のみなら
ず、電子回路装置にも適用することができる。The above explanation is directed to InP/InGaA8P lasers, but the semiconductor materials are limited to these, and the present invention is applicable to any group V compound semiconductor2)
Moreover, it can be applied not only to lasers and other optical semiconductor devices, but also to electronic circuit devices.
また■族元素としては前記実施例のZnの他に例えばC
d、M、47等を用いることができる。In addition to Zn in the above example, examples of group Ⅰ elements include, for example, C.
d, M, 47, etc. can be used.
以上説明した如く本発明によれば、■−v族化合物半導
体基体にす1どんど熱損傷を生ずることなく、n型及び
p型の伝導層を選択的に形成することが可能となって、
光半導体装置をけじめとして各種半導体装置の特性及び
信頼性の向上に大きい効果が得られる。As explained above, according to the present invention, it is possible to selectively form n-type and p-type conductive layers on a -V group compound semiconductor substrate without causing any thermal damage.
Great effects can be obtained in improving the characteristics and reliability of various semiconductor devices, including optical semiconductor devices.
第1図は本発明の実施例の工程順断面図、第2図は従来
例の工程順断面図である。
3はp型InGaAsP層、 4はp型InP層、5は
p型I nGaASP層、 9はn型InP層、10は
p型頭域、 11はn側電極、12はpgll
l電極を示す。
(、C,)
亮 1 図
り一一一一一一一一」
第 2 図FIG. 1 is a process-order sectional view of an embodiment of the present invention, and FIG. 2 is a process-order cross-sectional view of a conventional example. 3 is a p-type InGaAsP layer, 4 is a p-type InP layer, 5 is a p-type InGaASP layer, 9 is an n-type InP layer, 10 is a p-type head area, 11 is an n-side electrode, 12 is a pgll
1 electrode is shown. (,C,) Ryo 1 Figure 1111111” Figure 2
Claims (1)
化合物を構成する元素とII族元素とを溶質とする液相エ
ピタキシャル成長方法によって成長し、該半導体結晶に
隣接する半導体結晶内に該II族元素を拡散してp型領域
を形成する工程を含むことを特徴とする半導体装置の製
造方法。An n-type III-V group compound semiconductor crystal is grown by a liquid phase epitaxial growth method using tin as a solvent and an element constituting the compound and a group II element as solutes. A method for manufacturing a semiconductor device, comprising the step of diffusing a group II element to form a p-type region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12577284A JPS614226A (en) | 1984-06-19 | 1984-06-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12577284A JPS614226A (en) | 1984-06-19 | 1984-06-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS614226A true JPS614226A (en) | 1986-01-10 |
Family
ID=14918448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12577284A Pending JPS614226A (en) | 1984-06-19 | 1984-06-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS614226A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02136274A (en) * | 1988-11-16 | 1990-05-24 | Ricoh Co Ltd | Image forming system |
JPH0567200U (en) * | 1992-01-31 | 1993-09-03 | 西芝電機株式会社 | Digital control automatic voltage regulator terminal voltage detector |
US6657303B1 (en) * | 2000-12-18 | 2003-12-02 | Advanced Micro Devices, Inc. | Integrated circuit with low solubility metal-conductor interconnect cap |
-
1984
- 1984-06-19 JP JP12577284A patent/JPS614226A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02136274A (en) * | 1988-11-16 | 1990-05-24 | Ricoh Co Ltd | Image forming system |
JPH0567200U (en) * | 1992-01-31 | 1993-09-03 | 西芝電機株式会社 | Digital control automatic voltage regulator terminal voltage detector |
US6657303B1 (en) * | 2000-12-18 | 2003-12-02 | Advanced Micro Devices, Inc. | Integrated circuit with low solubility metal-conductor interconnect cap |
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