JPS614226A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable n type p type conductive layers to be selectively formed without causing any thermal damage to a substrate, by growing an n type III-V group compound semiconductor crystal by a liquid-phase epitaxial growth using tin as a solvent and an element forming this compound and a II-group element as dissolved substances, and diffusing the II-group element into a semiconductor crystal adjacent to the grown crystal, thereby forming a p type region. CONSTITUTION:As a solvent, tin is employed which enables a large degree of solubility of a III-group element and a V-group element which constitute of a III-V group compound semiconductor crystal at a relatively low temperature, and an appropriate amount of a II-group element which functions as an acceptor impurity for the III-V group compound semiconductor crystal, e.g., zinc, cadmium or magnesium, is added as a dissolved substance. Employment of this solution enables the growth temperature to be lowered to about 400 deg.C. The conductivity type of the LPE grown layer 9 thereby obtained is n type since it contains a relatively large amount of tin as an impurity. However, the above-mentioned II-group element is also contained in the LPE grown layer 9. Therefore, this II-group element is thermally diffused into a semiconductor substrate 2 or the like which is adjacent to the layer 9, whereby a p type conductive layer 10 can be formed adjacent to the n type grown layer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method for manufacturing semiconductor devices, in particular, a method for manufacturing n-type and p-type m-v group compound semiconductors using a liquid phase epitaxial growth method at a much lower temperature than conventional methods. The present invention relates to a manufacturing method for forming a conductive layer.

■-V group compound semiconductors are widely used in optical semiconductor devices and electronic circuit devices, and the
A combination structure of semiconductor layers whose compound composition, conductivity type, impurity concentration, etc. are selected is often formed by a liquid phase epitaxial growth method (hereinafter abbreviated as LPE method).

However, the LPE method is a high-temperature process and tends to cause deterioration of the semiconductor substrate on which crystals are grown.Although various countermeasures have already been provided, it is most desirable to lower the process temperature.

[Conventional technology]

■-V group compound semiconductors, such as gallium arsenide/gallium aluminum arsenide (GaAs/GaAA'As) and indium phosphorous/indium gallium arsenide phosphorous (InP/I
The LPE method is often applied to semiconductor lasers using materials such as nGaAsP (nGaAsP ).
Description will be given with reference to step-by-step sectional views shown in the figures.

Refer to FIG. 2(a) On an n-type InP substrate 1, an n-type InP confinement layer 2゜p-type InGaAsP active layer 3 + PmInP confinement layer 4 is formed.
and p m InGaAsP coytact layer 5 by LPE
It grows sequentially and continuously according to the law.

However, the solvent of the growth solution is I/Dicum (In),
The growth starting temperature is about 600°C.

Refer to FIG. 2(b). Silicon dioxide ry is deposited on the p-type InGaAsP contact layer 5.
A striped mask 6 is formed using (SiCh) or the like.

Using this mask 6, etching is performed to form reverse mesa stripes as shown in the figure.

Referring to FIG. 2(c), a second LPE growth is performed to form a p-type InPH layer 7 and an n-type InP layer 8. Similar to the first LPE growth, this second LPE growth also uses In as a solvent and the growth start temperature is about 600°C. The structure of this example is called a buried stripe structure.

- To realize this structure, two LPs are usually required as described above.
E growth is performed, and these two LPE growths were conventionally performed at a growth start temperature of 600°C using In as a solvent.
It is said that the amount of

In the LPE method, in order to dissolve a predetermined amount of solute in a solvent and to form a thermal equilibrium state, it is necessary to maintain the substrate and solution at a temperature equal to or higher than the growth initiation temperature for about 20 to 40 minutes.

Due to this high temperature maintenance during the second M LPE growth after the reverse mesa etching described above, thermal damage occurs near the exposed surface of the semiconductor substrate, and an X as shown in FIG.
Many crystal defects will be introduced as shown by the marks.

These crystal defects significantly increase the leakage current during operation of the laser, and are one of the causes of deterioration in which the so-called dark region (emission dark area) grows, significantly deteriorating its characteristics. There is.

Conventionally, attempts have been made to improve this situation by, for example, applying P pressure to the exposed surface of the substrate in order to suppress the separation of phosphorus (P), but these efforts have not resulted in the desired effect.

In order to suppress the thermal damage described above, it is desirable for K to lower the LPE growth temperature as much as possible. However, in the conventional LPE growth method using group Ⅰ metals such as In or Ga as a solvent, there is a limit to lowering the temperature due to the solubility of the metals.
It is considered that the growth temperature is 700° C. or higher for As-based materials, and 550° C. or higher for InP-based materials.

As an LPE method capable of lowering the growth temperature, a method using tin (Sn) as a solvent is already known. However, regarding III-V group compound conductors 5.
nid usually acts as a donor impurity, and a ■-■ group semiconductor epitaxially grown from an Sn solvent usually becomes n-type, making it impossible to grow a p-type semiconductor crystal.

[Problem 3 to be solved by the invention As explained above,
It is currently impossible to perform LPE growth of a type conductive layer without causing damage to the substrate, and there is a strong demand for a solution to this problem with respect to the buried stripe structure.

[Means for solving problems]

The problem is that an n-type ■-■ group compound semiconductor crystal is grown by a liquid phase epitaxial growth method using tin as a solvent and an element constituting the compound and an H group element as a solute. This problem is solved by a method for manufacturing a semiconductor device according to the present invention, which includes a step of diffusing the H group element into a semiconductor crystal to form a p-type head region.

[Effect]

In the present invention, the solvent is tin, which has high solubility at low temperatures for the M group and V group elements constituting the compound semiconductor crystal, and the H group element, which functions as an acceptor impurity for the -V group compound semiconductor crystal. Substantial amounts of elements such as zinc, cadmium or magnenium are added as solutes.

By using this solution, the growth temperature can be lowered by about 400.degree. C.1 even when the effect of removing the natural oxide layer on the semi-solid substrate is considered.

The conductivity type of this LPE growth layer is n-type because it contains a large amount of tin as an impurity, but the above-mentioned H group elements are also contained in the LPE growth layer and are thermally diffused into the adjacent semiconductor substrate. , a p-type conductive layer can be formed in contact with the n-type growth layer.

The thermal diffusion requires a temperature of approximately 600° C., which is approximately the same as the conventional LPE growth temperature using group Ⅰ elements as a solvent, but this does not expose areas important for the characteristics and reliability of the semiconductor device. In addition, deterioration of characteristics and reliability due to thermal damage is prevented.

〔Example〕

The present invention will be specifically explained below with reference to an embodiment shown in FIG.

Refer to FIG. 1(a) Similar to the conventional example, the following semiconductors J@2 to 5 are sequentially grown on an n-type InP substrate 1 by the LPE method. The solvent of the growth solution was In, and the growth starting temperature was 600°C.
It is said that

2 is an n-type InP confinement layer doped with tin (S n) to about ix t O"crIL-' and has a thickness of about 1 μm; 3 is an n-type InP confinement layer doped with zinc (Zn) to about lX1017 儂-3 and has a thickness of about 1 μm. 0.1 μm 媛 °”””°゛°0°°°°
°"°°°゛0.35fg layer, 4 Zn 5X10'
P-type In doped to about 7σ-3 and about 1.5 μm thick
The P confinement layer 5 is made of p-type InO doped with Zn to about I x 10 cm-' and has a thickness of about 0.5 μm, 70
Ga O,304a O,65Po,3.5 :y intact.

Refer to FIG. 1(b). A film such as Sin is deposited on the p-type InGaAsP contact layer 5 by sputtering or the like, and a striped mask 6 having a width of about 35 μm, for example, is formed by phosphorography.
form.

Etching is performed using a methanol solution of odor X (Br) to form an inverted mesa stripe as shown in the figure.

Refer to FIG. 1(c). A second LPE growth was performed to obtain an n-type InP atomic fraction, and after holding this solution and the semiconductor substrate at a temperature of 460°C for about 30 minutes, growth was started at a temperature of 440°C. ing.

The InP layer 9 obtained by this LPE growth is n-type with a carrier concentration of approximately 8×1g+aσ-3.

Refer to FIG. 1(d). The semiconductor substrate is subjected to heat treatment at a temperature of 600° C. for about 2 hours and 20 minutes, for example, to diffuse Z and n contained in the InP buried layer 9. A p-type region 10 is formed in the 11-type InP layer 2 by this Zn diffusion. In this embodiment, the depth of the p-type region 10 is about 05 μm, and the carrier concentration at the interface on the side of the confinement layer 9 is about 1×10”f−3.

Figure 1(e) After reducing the thickness of the back surface of the reference substrate 1 by polishing, etc.
The 0Ill electrode 11 is made of, for example, a gold-tin (Au-8) alloy, and the p9Ill electrode 12 is made of, for example, titanium/platinum/gold (Ti/pt/A-u), with gaps between the folds, etc. This completes the manufacturing of this embodiment.

Although the diffusion process causes thermal damage in the vicinity of the exposed surface of the semiconductor substrate, it is easily possible to provide a protective film in advance or remove the damaged layer, which does not significantly affect the device characteristics.

Since the embedding growth temperature is lowered to about 450° C. at the interface with the embedding hole inside the semiconductor substrate, which has been a problem in the past, thermal damage is suppressed to a negligible level. In comparison with the example, excellent characteristics are obtained such that the threshold current decreases from about 40 mA to about 25 mA [2] and the luminous efficiency increases from about 0.20 to about 0.40 on one side.

The above explanation is directed to InP/InGaA8P lasers, but the semiconductor materials are limited to these, and the present invention is applicable to any group V compound semiconductor2)
Moreover, it can be applied not only to lasers and other optical semiconductor devices, but also to electronic circuit devices.

In addition to Zn in the above example, examples of group Ⅰ elements include, for example, C.
d, M, 47, etc. can be used.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to selectively form n-type and p-type conductive layers on a -V group compound semiconductor substrate without causing any thermal damage.
Great effects can be obtained in improving the characteristics and reliability of various semiconductor devices, including optical semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a process-order sectional view of an embodiment of the present invention, and FIG. 2 is a process-order cross-sectional view of a conventional example. 3 is a p-type InGaAsP layer, 4 is a p-type InP layer, 5 is a p-type InGaASP layer, 9 is an n-type InP layer, 10 is a p-type head area, 11 is an n-side electrode, 12 is a pgll
1 electrode is shown. (,C,) Ryo 1 Figure 1111111” Figure 2

Claims (1)

[Claims] An n-type III-V group compound semiconductor crystal is grown by a liquid phase epitaxial growth method using tin as a solvent and an element constituting the compound and a group II element as solutes. A method for manufacturing a semiconductor device, comprising the step of diffusing a group II element to form a p-type region.