JPS6139771B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a code converter system in which code converters are provided before and after a buffer memory to control data structure such as compression and rank conversion in order to convert an input information code into a desired output information code, and which also has a response function. . Conventionally, a code converter method for converting an input information code from an information processing device CPU or a control device having a similar function into a desired output information code is based on a fixed memory ROM, as shown in the configuration of Figure 1a. The code converter 10 is used to convert input information code 1 to output information code 2. As shown in the flowchart of FIG. For example, if the input information code is 8 bits per byte, the output information code converted one-to-one is also composed of 8 bits per byte, so it is not compressed and there is redundancy. do. Also, since the conversion of input/output information is unidirectional, the code converter in this case does not have reversibility to enable response. An object of the present invention is to provide a code converter system that controls data structure such as compression and rank conversion, and has a response function. In order to achieve the above object, the code converter method of the present invention converts an input information code from an external device into a desired output information code using a code converter. A first code converter sequentially converts the address information into address information and stores it in a buffer memory, reads out the address information stored in the buffer memory according to a control code from a control device, and corresponds to the address information by a second code converter. At the same time as obtaining an output information code, the address information stored in the buffer memory is sent back to the first code converter using the control code from the control device, and converted into a response information code by the first code converter and sent to the external device. It is characterized by being returned to the device. The present invention will be described in detail below with reference to examples. FIG. 2a is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, an input information code 1 from an information processing device or a similar control device is input to a reversible code converter 11 consisting of a ROM, and this input information code is sequentially converted as shown in Table 1 below. do.

[Table] That is, sequential address information is assigned as an output code to an arbitrary input code string. Address information 1' of this output code is stored in a buffer memory 12 consisting of a random access memory RAM. This buffer memory 12 is arbitrarily controlled by an external control code 3. That is, it is possible to convert the order of the contents of the buffer memory 12 and to combine sequences, and it is also possible to compress information. Address information 2' processed in this manner is input to a code converter 13 consisting of the same ROM as in FIG. 1, where it is converted into desired output information 2 and sent out. In addition, address information 4' is input from the buffer memory 12 to the reversible code converter 11, which is controlled by the control code 3, converted to a response information code 4, and sent to the CPU, etc., making it possible to confirm the response of the processed data, increasing reliability. I can figure it out. Figure b is a flowchart showing the operation of the embodiment of the present invention. That is, a match between the input information code [] and the contents of the reversible code converter 11 is detected [], and when they match, the code converter 11 at that time is
Outputs the address information held by []. This address information is stored in the buffer memory 12 [], and this address information is stored in the code converter 13.
It is converted into a desired output information code at [ ], and the output information code is extracted [ ]. FIG. 3 shows an example of application of the present invention. In the figure, when a Kanji code 1 is input to a reversible code converter 21, address information 1' to which the Kanji code is assigned is output. It is stored in a buffer memory 22 for monitor display, and the address information 2' of the contents of the buffer memory 22 is input to a kanji pattern memory 23 which is a code converter at the next stage. This kanji pattern memory 23 compares the given address information 2' with the address of its own kanji pattern, inputs the kanji pattern 2 with the matching address to the video signal generator 24, and outputs the video signal 5. and displayed on the monitor 25. As explained above, according to the present invention, the first stage of two types of code converters is a reversible code converter, the second stage is a simple converter, and a buffer memory is arranged between them, and the buffer memory can be controlled as described above. Rank conversion and sequence combinations are possible. Furthermore, since the input information can be compressed, the capacity of the output buffer memory can be reduced to the necessary minimum. In addition, since the code converter in the previous stage can reversely convert the stored information shown in the buffer memory,
Confirmation responses can be made between the CPU, control device, and buffer memory, which greatly contributes to improving the reliability of information.

[Brief explanation of the drawing]

Figure 1 a, b is an explanatory diagram of the conventional example, Figure 2 a, b
3 is an explanatory diagram a showing the configuration of an embodiment of the present invention and a flowchart b of the operation, and FIG. 3 is an application example of the present invention. In the figure, 1 is an input information code, 2 is an output information code,
3 is a control code, 4 is a response information code, 1',
2' and 4' are address information, 11 is a code converter, 12 is a buffer memory, and 13 is a code converter.

Claims (1)

[Claims] 1. In a code converter method in which an input information code from an external device is converted into a desired output information code using a code converter, the input information code is sequentially converted into address information by a reversible first code converter. and storing the address information stored in the buffer memory in accordance with a control code from a control device to obtain an output information code corresponding to the address information by a second code converter, and The address information stored in the buffer memory according to the control code from the control device is
A code converter method characterized in that the first code converter converts the response information code into a response information code and sends the response information code back to the external device.