JPS6139143A - Data processor - Google Patents

Abstract

PURPOSE:To reduce an increase in hardware with the extension of a processor without providing an error storage register for each processor by using two kinds of error storage registers of a main storage device for error registration in normal operation and error registration in diagnosing operation. CONSTITUTION:The main storage device is connected to plural central processors to constitute the data processor, and this main storage device is provided with the 1st and the 2nd error storage registers 16 and 17. Further, a comparing circuit 12 which accesses a processor number storage register 9 and the main storage device and compares the output of the accessed processor with the output of the register 9 is provided in correspondence to each processor. An error detecting circuit 11 detects a hardware error in the main storage device and registers an error in normal operation in the register 16. Further, an error in diagnosing operation is registered in the register 17. Then, an increase in hardware accompanying the extension of a processor is reduced without providing an error storage register for every processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data processing device having a plurality of processing devices and a main storage device connected thereto.

[Prior art]

Generally, a data processing device is often composed of a plurality of processing devices (a central processing unit and an input/output processing unit) and one main storage device connected to these processing devices.

In response to memory requests from each processing unit, the main memory executes the operation according to the request command, and if an error is detected during execution of the operation, it reports the error to the processing unit and provides detailed error information. is registered in the error storage register. Once error information is stored in this error storage register, detailed information regarding newly occurring errors will not be registered until this information is harvested. When an error is reported from the main memory to the processing unit, the processing unit issues a command to read the error storage register, obtains detailed error information, and sends a notification to the software via software or firmware. do. Software 1 is notified of the main memory address where the error has been detected as detailed information, and the software scans the main memory addresses in the area near the reported main memory address to check whether there is an address with a fixed failure. This scanning operation is executed, for example, in units of one page (one page in paging), and if an error is detected, software processing is performed such as not assigning the corresponding main memory address to page allocation. As a result, even if a fixed failure occurs at a certain main memory address, it is possible to remove it by software.

In a system where multiple processes run in parallel, such as a multiprocessor system, one process performs normal work while other parallel processes perform memory scans to detect main memory failures. There are cases in which an action is performed. The present invention relates to error registration when such normal read/write operations and memory scan operations overlap.

Conventionally, due to the eight-double condition that there is only one error storage register in the main memory, error information detected in a memory scan operation is registered in the error storage register 42, and normal successive writes/writes occur. A case may occur in which the error information of an error detected during execution of a read operation is not registered.In other words, an error is detected in a memory scan operation by a command from one processing unit, and then the error information is not registered until the error storage register is harvested. Error information for errors during read/write operations (due to commands from other processing devices) that occur in between becomes unavailable.

In order to eliminate the above disadvantages, there is a method of having an error storage register in the main memory for each processing unit, but if the number of processing units is increased by this method, the increase in number of hard quests becomes proportionally large, resulting in cost problems. becomes.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a data processing device that can collect detailed error information when a normal successive/write operation overlaps with a memory scan operation while minimizing an increase in eight-domain squares. .

[Structure of the invention]

The present invention provides an error storage register that stores error information when executing an operation from a processing device that is executing a specific process, and an error storage register that stores error information when executing an operation from a processing device that is executing other normal operations. An error storage register that stores information is divided into first and second error storage registers that register errors detected in the main memory;
a processing device number storage register that stores a processing device number associated with each of the processing devices; a comparison circuit that compares a processing device number that has accessed a main storage device with an output of the processing device number storage register; and one state. When an error in the main storage device is registered in the first error storage register, and when in one other state, an error related to the processing device having the processing device number that accessed the main storage device that matches the output of the processing device number storage register. is registered in the second error storage register, and an error related to a processing device having a processing device number that does not match the output of the first register is stored in the first error register. It has two registering control circuits.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. This data processing device is composed of a main storage device 1 and three central processing units 2 to 4. The main storage device 1 and the central processing device 2 include a request signal 201, a request acceptance signal 202, a command signal 206, a processing device number selection signal 204, address information 205, and write data 20.
6, read data 207, and other control signals 208. Main memory 1 and central processing unit 3, main memory,
The device 1 and the central processing unit 4 also receive similar signals and information 6.
01-608, 401-408 are connected.

FIG. 2 is a block diagram showing details of the main storage device 1. As shown in FIG. This main storage device 1 receives request signals 201 . ．． 501, 401 according to a predetermined priority order, and the receiving device signal 101 (consisting of 2 bits in this embodiment, '00'', ``'',
When "io", control (b) central processing unit 2, m respectively
A request reception circuit 5 outputs a request (indicating that the central processing unit 6 and the central processing unit 4 have been accepted) and corresponding command signals 206 and 606 from the central processing units 2 to 4 based on this reception device signal 101. ,40. a command selection circuit 6 that selects one of the received command signals 102 and outputs a reception command signal 102, and a corresponding processing device number 204.
604. Select one of 404 and select reception processing device number 10.
7, a processing device number storage register 9 that inputs and stores this acceptance processing device number 107, and an output 1 of this processing device number storage register 9.
08 and reception processing device number 107, and outputs a signal 109 of "1" when they match, and a comparison circuit 12 that detects a hardware error in the main storage device 1 and outputs an error detection signal 112 and error information 116. An error detection circuit 11 that outputs a first set signal 114 as a set input, a first reset signal 105 as a reset input, and an error detection signal 112 from the error detection circuit 11 and error information 1.
16 as an input, a second set signal 117 as a set input, a second reset signal 106 as a reset input, and an error detection signal 112 from the error detection circuit 11 and error information 116 as inputs. A second error storage register 17 as an input, a control flip-flop 10 controlled by a control signal 104, and an AND circuit 15 that receives an output 110 of this control flip-flop 10 and a coincidence signal 109 from a comparison circuit 12 as input signals. and,
A reception command signal 102 is input, a control signal 106 is sent to the processing device number storage register 9, a control signal 104 for controlling the control flip-flop 10, and a first error storage register 1.
The first reset signal 105 and the second
The main control circuit 8 generates the second reset signal 106 that resets the error storage register 17 of An AND circuit 16 which receives the first set signal 114 as an input, and a second set which receives the output signal 116 from the $2 error storage register 17, the error detection signal 112, and the output signal 111 of the AND circuit 15 as input. and an AND circuit 14 which outputs a signal 117.

Next, the operation of the data processing apparatus of this embodiment will be explained. Here, the central processing unit 2 is assumed to be a processing unit executing a diagnostic (memory scan) operation, and the central processing unit 6.4 is assumed to be a processing unit executing a normal operation. The central processing unit 2 receives a command signal 203
I: Processing device number 20 to processing device number storage register 9
4, and request signal 2.
Set 01 to “1”. The main storage device 1 recognizes the request signal 201 from the central processing unit 2 in the request reception circuit 5, and if the request signal 201 is in an acceptable state, it is accepted and the reception device signal 101 is set to "00".

When the reception device signal 101 is “OO”, the command selection circuit 6,
The processing device number selection circuit 7 outputs a command signal 206 and a processing device number 204 from the central processing device 2 as an acceptance command signal 102 and an acceptance processing device number 107, respectively. The main control circuit 8 analyzes the acceptance command signal 102, interprets it as a command requesting registration of the processing device number in the processing device number storage register 9, and sets the control signal 106 to “1”. This control signal
When 106 becomes 1', the processing unit number "00" of the central processing unit 2 is registered in the processing unit number storage register 9 via the processing unit number selection circuit 7.

Subsequently, the central processing unit 2 issues a command to set the control flip-flop 10, the main control circuit 8 issues a control signal 104, and the control flip-flop 10 is set.

In the above state, the request signal 60 is sent from the central processing unit 6.
1 is issued, this is accepted by the main memory 1, and during the execution of the operation (if a second error is detected, the error detection signal 112 which is the output of the error detection circuit 11 becomes "1" (:), and an error related to this error is detected. Information 116 is generated. Since "00" is stored in the processing device number storage register 9 and is ε1, and on the other hand, the reception processing device number 107 is "01" indicating the central processing device 6, the output of the comparison circuit 12 is The signal 109 becomes “0” and the output signal 111 of the AND circuit 15
also becomes “On.” The first and second error storage registers 16
゜17 (= Since no error has been registered yet, the respective output signals 115 and 116 are "0", and from these, the first set signal 114 from the AND circuit 16 is "1".
”, the second set signal 117 from the AND circuit 14 is 0.
”, the error storage register 16 of $1 (- means an error is registered, and no error is registered in the second error storage register 17.

Next, a request signal 201 is issued from the central processing unit 2, and this is accepted by the main storage device 1. If an error is detected during execution of the operation, the error detection signal 112, which is the output of the error detection circuit 11, is "1'' and error information 116 regarding this error is generated. 00" is stored in the processing unit number storage register 9, and the reception processing unit number 107 is also "00#, which indicates the central processing unit 2, so the output signal 109 of the comparison circuit 12 becomes "1".
Since the output signal 110 of the control flip-flop 10 is also "1", the output signal 111 of the AND circuit 15 is "1". Since the output signal 116 of the second error storage register 17 is 40# and the error detection signal 112 is "1", the second set signal 117 which is the output of the AND circuit 14 is "
1'', and the error is registered in the second error storage register 17.

〔Effect of the invention〕

As described above, the present invention eliminates the need to provide error storage registers in the main memory that are accessed by a plurality of processing units for each processing unit. By using two types, one for registration and one for registering, there is no need to increase the number of error storage registers for storing error information even if the number of processing devices that access the main memory increases, and the number of 8-domain registers increases as the number of processing devices increases. It has the effect of reducing

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing details of the main storage device 1 of FIG. 1. 1: Main storage device, 2.6.4: Processing device, 5:
Request reception circuit, 6: Command selection circuit, 7: Processing device number selection circuit, 8: Main control circuit, 9: Processing device number storage register, 10: Control flop, 11: Error detection circuit, 12: Comparison circuit, L6.14.
15: AND circuit, 16: First error storage register, 17: %2 error storage register.

Claims (1)

[Scope of Claims] A data processing device having a plurality of processing devices and a main memory device connected thereto, comprising first and second error storage registers for registering errors detected in the main memory device; A processing device number storage register that stores a processing device number associated with a processing device, and a comparison circuit that compares a processing device number that has accessed a main storage device with an output of the processing device number storage register, when in one state. Errors in the main storage device are registered in a first error storage register, and errors related to the processing device having the processing device number that accessed the main storage device that matches the output of the processing device storage number register in one of the other states are registered in the first error storage register. 2. A data processing device comprising: a control circuit that registers an error related to a processing device having a processing device number that does not match the output of the first register in the first error storage register.