JPS6137710B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a highly integrated, large capacity dynamic semiconductor memory device. In recent years, there has been remarkable progress in integrated circuit technology, especially in semiconductor memory devices. Such semiconductor memory devices are required to have larger capacity and faster read and write times. Conventionally, the memory cell of a MOS dynamic RAM has been a one-transistor cell 1 consisting of one capacitor 02 and one transistor 01, as shown in FIG. 1a. An example of this cell configuration (4 Kbit RAM) is shown in FIG. 1b, but the cell element is approaching the limit of reduction. Here, 11 is a field oxide film,
12 is a gate of a storage capacitor, 13 is a transfer gate, and 14 is a digit line diffusion layer. Therefore, there is a type (16 Kbit RAM) of the same one-transistor cell whose structure is made into a two-layer polysilicon structure as shown in Figure 2c, and whose cell area is greatly reduced. However, 21 is the field oxide film, 22 is the gate of the storage capacitor, and 2
3 is a transfer gate, and 24 is a digit line diffusion layer. This allows dynamic RAM
It can be said that both the configuration and structure of memory cells have almost reached their limits of shrinkage. Therefore, in order to manufacture dynamic RAM with even higher capacity, it is necessary to reduce the dimensions of individual transistors and capacitors. For this purpose, research and development are being carried out on electron beam phosphorography technology to replace the current photorinography technology. By the way, in the case of dynamic RAM, memory data is stored in the storage capacitor in the form of electric charge. Therefore, it is easy to infer that the amount of charge in the storage capacitor of a cell will greatly affect the performance of the RAM. fact, second
In the basic configuration circuit of a dynamic RAM as shown in FIG. , where W is the word line, which occurs when the charge from the memory cell C is distributed to the total capacitance of the digit line. If Cdig is the daisy line capacitance, Vi is the potential of the daisy line in the initial state, Cs is the capacitance of the storage capacitor of memory cell C, Vs is the cell potential, and Ctr is the gate capacitance of the transistor in cell C, then the potential variation △
From the equivalent circuit of one daigit wire shown in Figure 2b, V is △V=Vi-ViCdig+CsVs/Cs+Ctr+C
It is dig. In the case of an n-channel MOS transistor, when logic "1" is written in the cell, ΔV is about 1V for 4Kbit RAM and about 600mV for 16KbitRAM.
Current RAM uses a sense circuit 50 using a balanced flip-flop and a dummy cell DC to detect and amplify this minute signal. The dummy cell DC provides a necessary reference potential to the daisy line on the opposite side of the sense circuit 50 from the cell, and is usually 1/2 of the capacitor of the cell.
It is a one-transistor memory cell with a capacity of . The daisyte line on the dummy cell side always has a potential fluctuation of about 1/2 of △V in the case of "1" on the cell side, and the logic "1" of the cell
It has been devised so that it can read out "0" and "0" accurately. Table 1 below shows the differences in memory cell values between 4KbitRAM and 16KbitRAM.

[Table] Compared to 4KbitRAM, 16KbitRAM has about half the cell area, but its storage capacitor capacity is almost the same. Also, since the number of cells connected to one digit line doubles, the value of Cdig increases, and the signal level increases.
16KbitRAM is slightly lower. In the future, when developing even larger capacity dynamic RAM, it will be inevitable to use smaller elements. In this case the capacitor capacity of the cell will be significantly reduced. To compensate for this, (1) the insulation film thickness of the cell capacitor should be made extremely thin. (2)
Reduce Cdig and make the signal level as high as possible. (3) Increase the level of "1" written into the memory cell to increase the amount of stored charge.
It is necessary to use such a method to bring the signal level within the sensitivity of the sense circuit. However, there are three major problems in reducing the thickness of the gate insulating film as described in (1) above. The first is the issue of reliability. When a thin insulating film is used, even if a small voltage is applied, the electric field is inversely proportional to the thickness of the insulating film, so it easily reaches the dielectric breakdown strength and causes dielectric breakdown. The second problem is so-called pinholes when making thin films. Pinholes always occur with a certain probability, and the thinner the film, the greater the number of pinholes. Moreover, the higher the density of elements is integrated, the higher the probability that such a film defect will hit a region forming an element. Therefore, the yield of products decreases and manufacturing costs increase. Thirdly, there is the problem of increased leakage current of the gate oxide film. This is a problem in which the minute current flowing in the insulating film increases and discharges or charges the accumulated charges, changing the stored contents. When the insulating film becomes particularly thin, the electric field within the film becomes particularly strong, and currents due to Poole-Frenkel conduction and other conduction mechanisms increase particularly. Therefore, it is unlikely that an extremely thin insulating film can be used. Furthermore, as mentioned in (2) above, reducing the number of Cdigs usually increases as the capacity increases. This is because, for example, if a multiplex addressing system is adopted, the most rational arrangement of the memory array is n×n (n is an integer and is a power of 2 to the number of address pins). Therefore, the number of cells connected to one digit line will definitely increase and its length will also increase, and Cdig will tend to increase. Therefore, it would be quite difficult to reduce Cdig. Regarding the last remaining method (3) of increasing the potential for writing, it is difficult to apply increasing the power supply voltage because of the various breakdown voltages of fine elements and the two-dimensional effect of the elements. In particular, in recent years, when using microscopic elements, the prevailing idea is to lower the voltage in accordance with the degree of miniaturization. Lowering the voltage is considered to be an inevitable direction in order to reduce the two-dimensional effect of power consumption reduction elements. Therefore, in the future, even larger capacity dynamic
In order to manufacture RAM, it is necessary to use miniaturized elements. Under such circumstances, it is a major problem to ensure that the signal level from the memory cell is sufficiently large. The present invention was made in view of the above circumstances, and an object of the present invention is to provide a dynamic semiconductor memory device that can extract large signals from memory cells even when the constituent elements are miniaturized and the capacity is increased. There is. According to the present invention, in order to obtain a low-voltage, large-capacity dynamic semiconductor memory device, the voltages of the daisyte line and the cell word line are boosted. An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 3 is a block diagram conceptually showing an embodiment of the present invention. In the figure, one sense amplifier 50 is representatively selected from a large number of sense amplifiers housed in a memory chip and cells arranged in rows and columns, one row of daisy lines A and B, and several cells C (MOS (including a type transistor 54 and a MOS type capacitor 55) are shown separately. Here, the word line 60' is connected to transistors of many cells in the vertical direction, but only the connection to one cell is shown in this figure. The main point of the present invention is that the sense
The potentials of the daisyte lines A and B sensed by the amplifier 50 are fed back to the daisyte booster circuit 51 and become "1".
digit lines A and B are boosted to raise the potential of the digit lines. This high potential can be about 1.8 times the externally applied power supply voltage _VDD . Next, the circuit 53 for decoding the word line 60 can be constructed from an ordinary address decoding circuit. Fourth
Figure a shows an example. Further, FIG. 5B shows each signal waveform. Here, the clock _φD is a boost clock, which is connected to the word line 60 through the decode transistor 71, and makes the "1" level of the word line about 1.8 times the power supply voltage _VDD . Also clock φ _D
The circuit that generates this is the boost clock generating circuit 52 shown in Figure 3.
It is. Even if the voltage on the daisy line (assumed to be A) is increased, if the gate potential of the transfer gate 54 of the memory cell C becomes higher than the voltage on the daisy line A, the increased voltage cannot be written into the capacitor 55 of the cell. Therefore, the word line 60
The potential is also boosted to make it high enough for writing. FIG. 5a shows an example of a boost clock generating circuit, and FIG. 5b shows each signal waveform. This is a normal clock generation circuit 101.
A boosting capacitor 102 and a boosting clock generation circuit 103 are added to the same. Here, in order to obtain a sufficient bootstrap effect, the circuit 101
An appropriate delay is applied between the two clock signals generated from circuit 103 and 103. In other words, the voltage of the clock _φ101 begins to rise and charges the capacitor 102. Then, when the battery is sufficiently charged, the clock _φ103 starts to rise, boosting the voltage of the clock _φD . In this way, a clock at a level higher than the power supply voltage is obtained. FIG. 6a shows a specific example of a daisy-line booster circuit. Figure b is a diagram showing the waveforms of each signal. That is, the transistors 31 and 32 constitute a ratioless inverter 70, the drain of the transistor 31 receives the clock _φ1 , and the gate thereof is connected to the digit line _DA . Further, a clock _φ2 is inputted to the gate of the transistor 32, and the output terminal of this inverter is lowered to the ground potential by a precharge signal. The drain of the transistor 33 is connected to a digit line D _A to which the gate of the transistor 31 is connected. Its gate is also connected to the clock _φ3 . A boosting capacitor 34 is connected between the output terminal of the inverter 70 and the source of this transistor 33. Note that although a regiores type dynamic sense reflex amplifier as shown in Figure 6a is used here, the daisy-wire that goes to the "1" level after the sensing ends becomes a floating node in the circuit. , the same effect can be obtained no matter what kind of sense amplifier is used, as long as the digit line that goes to the "0" level is electrically connected to the ground terminal. The operation of the circuit in FIG. 6a is as follows:
During the pre-charge cycle, the transistor 33 becomes conductive and charges the capacitor 34. At this time, the output of the inverter is at ground potential. Transistor 33 then becomes non-conductive and daisy line D
_A and the capacitor 34 are separated. Data is then read out from the cell onto the daisy-bit line _DA ,
A sense amplifier determines "1" or "0". During this time, _φ2 becomes the ground potential, and the transistor 32 becomes non-conductive. After that, _φ1 rises to a high potential. At that time, a transistor 31 whose gate is connected to the digit line determined to be "1"
becomes conductive, charging the output terminal of the inverter 70, boosting the voltage of the capacitor 34, and increasing the voltage of the transistor 33.
raises the potential at the source end of the source to higher than the power supply potential. At this time, φ ₃ becomes a potential higher than the power supply voltage V _DD again, pushing the daisy conductor line higher than the power supply potential. In addition, in the case where the gate is connected to the digit line determined as “0”, the transistor 3
1 is non-conductive, the capacitor 34 is not boosted and the digit line is not boosted either. However, at this time, the transistor 33 becomes conductive in the same way as the "1" side, so the charge that had been charged in the capacitor flows into the digit line, raising its potential slightly above the ground potential, but the daigit on the "0" side If the line is connected to ground by the sense amplifier and is not floating, it is immediately fixed to ground potential again. In this way, "1" at a potential higher than V _DD and "0" equal to the ground potential remain on the daisyte line. The "1" and "0" are written into the storage capacitor 55 of memory cell C through the transfer gate 54 of memory cell C, which is conductive by the word line at a potential higher than V _DD . Word line 60 is then brought to ground potential, transfer gate 54 is closed and charge is stored in cell C. The effects obtained by the present invention are as follows. First, in order to make both the word line potential and the digit line potential higher than the power supply voltage, conventionally the maximum write potential into the memory cell was the power supply voltage, but according to the present invention, the maximum write potential into the memory cell is the power supply voltage. can be written into the cell. By doing this, for example, if the same power supply and sense amplifier as in the conventional case are used, the capacitor of the memory cell can be made smaller by that amount. In particular, the larger the capacity of the memory, the larger the ratio of the area of the entire memory cell to the entire chip, and even a slight reduction in the size of the cell will lead to a large reduction in the chip area. For example, in a conventional 16Kbit dynamic RAM that uses +12V as a power supply, the memory cell area is 500μ ² and the capacitor area is 140μ ² .
The capacitance was 0.06pF. The charge stored in the cell is 0.06 x 10 ^-12 (F) x 12 (V) = 0.72
(pC). When the write voltage is increased as in the present invention, the capacity required to guarantee the same amount of charge is as follows. Now, if the voltage is boosted using a 12V system, and the bootstrap efficiency is 70%, the write voltage will be 12 + 12 x 0.7 = 20.4V. The capacitance of the cell is Cs'=0.035pF, and the capacitor area of the cell is ^82μ2 . Even if you do simple calculations, this means that the memory cell area per 1 bit is 11.6
% decrease. This leads to a reduction in the chip area almost by this amount. This increases the number of chips in a single wafer, improving product yield, and at the same time reducing product cost and generating more profits. Second, if the same memory cells as before are used, the amount of charge written into the memory cells will increase significantly, so the signal level output to the daisyte line will increase accordingly, reducing the operating margin of the RAM. It can provide larger and more reliable memory. Third, when developing 64Kbit or 256Kbit dynamic RAM, the power supply voltage will also decrease in line with the geometry of the transistors used. In such a case, in the prior art, the voltage written to the memory cell must also be reduced. This, together with the reduction in the capacitor area of the cell, results in a doubly reduction in the amount of charge within the cell, resulting in further deterioration of the signal. For example, with 64Kbit dynamic RAM,
It is thought that the cell area is about ^200μ2 and the cell capacitor area is about ^45μ2 . If a gate oxide film of about 300 Å is used for this and the power supply is 8V,
In the conventional method, the amount of charge stored in the cell is 0.0518
(pF)×8(V)=0.414(pC). According to the present invention, the write voltage becomes 13.6V by boosting 8V by 70%. Therefore, 0.0518 (pF) x 13.6 (V) = 0.704
(pC). This is approximately equal to the amount of charge stored in the current 16Kbit RAM cell. As a result, the signal obtained on the daisyte line can maintain a signal level equivalent to the current 16Kbit signal level. Furthermore, when the amount of charge decreases, the influence of leakage current increases. This is because the leakage current within a cell consists of a component that is proportional to its area (such as a recombination generation current) and a component that is not proportional and is unique. Therefore, if the amount of charge is small, the reflash time must be shortened, which causes an increase in dead time when the memory device is actually incorporated into an electronic computer or the like. It also causes a decrease in the reliability of the LSI itself. According to the present invention, all of these can be avoided and a highly reliable, highly integrated dynamic
RAM can be provided. Fourthly, in the circuit shown in FIG. 6a, the advantages that transistor 33 has by itself have a significant effect on the present invention. In other words, as described above, the signal level appearing on the daisy line is a change in the potential of the daisy line caused by the amount of charge in the memory cell being distributed to the capacitance of the daisy line. Therefore, the signal level decreases as the capacitance of the digit line increases. When a fairly large capacitor is attached to the daisy line as in the present invention, the capacitance of the capacitor is added to the daisy line capacity. In this case, the effect of the present invention is halved.
Therefore, this transistor 33 separates the capacitor 34 from the daisy line while the data comes out from the memory cell and is transmitted to the node of the sense amplifier, substantially preventing an increase in the capacitance of the daisy line and preventing the signal from increasing. It gives the effect of raising the level. Furthermore, since the clock _φ3 is "1" during the precharge period, precharging of the capacitor 34 can be performed simultaneously with precharging of the daisy line, and no special transistor or clock for capacitor precharging is required. This prevents the chip area from increasing and the clock system from becoming complicated. Fifth, when the signal output to the daisy line is "1", it is higher than the precharge potential of the daisy line, and when it is "0", it is lower than the precharge potential of the daisy line. For this reason, in the past, a dummy cell was used to create a potential as a reference for determining "0" and "1", but in the present invention, the daisy line precharge potential can be directly used as the reference potential. Therefore, no dummy cell is required. The area of the tip can be reduced by this amount. Furthermore, the dummy cell clock can be eliminated. Next, modified embodiments of the present invention will be described. (1) A dynamic system in which a dummy cell is added to the daisy-wire to set the reference voltage to a more accurate value.
RAM is included in the present invention. (2) In place of the circuit 51 of the embodiment of the present invention, the circuits shown in FIGS. 7a and 7b are also included in the present invention. In this case, the precharge potential to capacitor 34 is not generated from the daisy conductor line, but from another route. Therefore, the waveform of clock φ ₃ ' is simpler than that of φ ₃ in FIG. 6b. Also here φ ₂ and φ
The same clock as ₄ may be used. (3) In the circuit 51 of the embodiment of the present invention, a circuit in which the transistor 32 is removed from both the circuits of FIGS. 6 and 7 is also included in the present invention.

[Brief explanation of the drawing]

Figure 1a is a circuit diagram showing an example of the configuration of a one-transistor cell, and Figure 1b is a circuit diagram showing an example of the configuration of a one-transistor cell.
Cross section of 14Kbit RAM single layer polysilicon cell,
Figure 2c is a cross-sectional view of a 16Kbit RAM two-layer polysilicon cell formed on a semiconductor substrate, Figure 2a is a block diagram showing the basic circuit configuration of a conventional dynamic RAM, and Figure 2b is the equivalent of one daigit line. A circuit diagram, FIG. 3 is a circuit diagram showing an embodiment of the present invention,
FIG. 4a is a circuit diagram showing a specific example of a word line decoder circuit, FIG. 4b is a characteristic diagram showing voltage waveforms of each timing clock, and FIG. Figure 6b is a diagram showing its timing chart, Figure 6a is a circuit diagram showing a specific example of the daisy-line booster circuit, Figure 7b is a diagram showing its timing chart, Figure 7a
1 is a diagram showing another example of the daisy-line booster circuit, and FIG. 1B is a diagram showing its timing chart. 11, 21...Field oxide film, 14, 24...
Digit line diffusion layer, 12, 22... Gate of storage capacitor, 13, 23... Transfer gate, A, B... Daigit line, 50... Sense amplifier, 51... Daigit line booster circuit, 52... Word line booster clock generator circuit. 53...Word line decoder circuit, 54...Memory cell transfer gate, 55...Memory cell storage capacitor.

Claims (1)

[Claims] 1. A plurality of memory cells configured by connecting insulated gate field effect transistors and insulated gate capacitors are arranged in rows and columns, and a digit line is connected to the source or drain of the transistor, and a word is connected to the gate. In an apparatus in which a sense circuit is connected to the digit line and the digit line is connected to the digit line, a voltage booster applies a voltage higher than a power supply voltage to the digit line in response to data read from the digit line; 1. A dynamic semiconductor memory device comprising: means for making a high level voltage higher than a power supply voltage. 2. The dynamic semiconductor memory device according to claim 1, wherein the boosting means is configured to boost the digit line potential sensed by the sense circuit.