JPS6137652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test method for logic circuits in an information processing system. In recent years, storage devices/circuits in information processing systems have become faster and larger in capacity as the main memory of information processing equipment as semiconductor technology advances, and on the other hand, they have become more distributed and diverse as input/output devices become more intelligent. Its uses are expanding.

Along with this, it is expected to automate the work and shorten the time required for testing for the increasing number of storage devices/circuits.

Scan systems are broadly divided into address systems that use random access and shift register systems that consist of serially connected flip-flop operating elements. When a system performs a storage or read operation, it is necessary to scan the entire number of memory elements connected in a chain. Since it is necessary to prepare test data corresponding to the total number of storage elements in the shift register, the test data has the disadvantage that a large amount of unnecessary data is included in the test data.

The present invention seeks to provide means to eliminate this drawback. For this reason, the present invention provides a test method for a scan system consisting of a shift register, which is equipped with means for storing valid data and addresses corresponding to the valid data, and which sequentially scans all addresses in accordance with a clock signal. When there is a match with the address, the stored contents of valid data corresponding to the address are sent out, and when there is no match, a fixed code is sent out.

This makes it possible to reduce the amount of test data corresponding to memory elements that do not require data.

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a scanning system testing method according to an embodiment of the present invention.

In the figure, 11 and 13 are counters, 12 and 17 are verifiers, 14 is an address register, 15 is a data register, 16 is a selector, 17 is a scan length register, and AND is an AND circuit.

The clock signal is "0" except in the stop state where "1" is input to the other input gates of the AND, and each time a logical product is obtained and a clock signal is output to the counter 11. Counter 11 accumulates the count every time a clock signal arrives, and sends the signal to collators 12 and 17. The address register 14 inputs the address of valid data stored in advance in the area designated for counting by the counter 13 to the collation device 1.
2 and also outputs to the data register 15 that stores valid data. Collator 12 compares the valid data address of address register 14 with counter 1.
Find a match for the cumulative total (number) of 1. When a match is obtained, the match signal is input to the selector 16 to be used as a selection signal, and is input to the counter 13 to accumulate the count and output the next address. The selector 16 which receives the selection signal from the collation unit 12 performs a two-to-one selection operation, selects the A terminal, and outputs valid data for testing from the data register 15. Collator 12
When the signal from the address register 14 and the counter 11 does not match, it outputs a "0" signal, and the selector 16 that receives this selects the B terminal and outputs a constant signal "1" or "0". ” is output. In this manner, the count is accumulated according to the clock signal of the counter 11 and the counter 13 is driven. The output of the address register 14 is constantly checked and matched by the checker 12, and valid data is output each time. In this way, the total number of storage elements is scanned, and the data register 15 is
If the valid data stored in the data register 15 is sent out according to the contents of the address register 14 which stores a preset address corresponding to the data register 15, it would be necessary to store the valid data in advance in correspondence with all the memory elements. Regarding the test data, especially when applied to the test of divided partial areas, only the necessary portions need to be stored, so the data register and storage work for a small amount of test data is required compared to the conventional method.

Note that the signal of the scan length register 18 and the counter 1 in which the total number of storage elements of the shift register under test is set in advance
When the comparator 17 compares the output signal of 1, when the scanning of all the memory elements is completed, a match is obtained and a signal ``1'' is output, which is sent to others as a signal to stop the test on the test specimen. and input into AND. At this point, it becomes difficult to obtain an AND with the clock signal, and there is no output to the counter 11, and subsequent operations automatically stop.

[Brief explanation of the drawing]

The figure is a block diagram of a test method in one embodiment of the present invention. 11 and 13 are counters, 12 is a verifier, 14 is an address register, and 15 is a data register.

Claims (1)

[Claims] 1 In a scan system test method using a scan circuit consisting of a shift register, the test method is equipped with means for storing valid data and addresses corresponding to the valid data, and the output of a counter that sequentially scans all addresses in accordance with a clock signal and the output of the valid data. A scan system test method characterized in that when a match with an address is found, the stored contents of valid data corresponding to the address are sent out, and when a match is not found, a fixed code is sent out.