JPS6014324A - Associative storage device - Google Patents

Abstract

PURPOSE:To eliminate the increase of cost and to shorten the retrieving time for an associative storage device by compressing the information quantity of a key word to produce a key code, storing this key code in response to the key word and detecting the coincidence between the key code and the key word in a retrieval mode. CONSTITUTION:A sequence controller 312 starts a block address scanning circuit 309 to read successively the contents of a register marker memory 308. The address scan of the circuit 309 is stopped when 0 is detected, and 1 is written in an address of the memory 308. While a key code is obtained by compressing the plural-word length of the key code into the one-word length through a compresssing circuit 311. This key code is written in a key code memory 307. Then the controller 312 starts a word address scanning circuit 310 to store a record 302 and a key word 301 in a record memory 305 and a key word memory 306 respectively while scanning the word address at and after an address 0. Thus the registration is ended. The retrieval is carried out by detecting the coincidence between the key code and the key word.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory device that outputs records related to a keyword by giving it a keyword.

Content addressable memory is an MJ component of database systems. The database is responsible for retrieving data records related to a given keyword. As shown in FIG. 1(b), data records are recorded on a mass storage device 10 such as a magnetic disk or magnetic tape. In order to search the contents of this mass storage device relatively efficiently, the method shown in FIG. An index table 15 as shown is generally used (index table 15).
The details of the table are described in the document ``Database Management'' written by Koji Kobayashi, published by Planning Center (Taru Publishing, so the explanation will be omitted). As shown in FIG. 2, index table 15 is preferably stored in content addressable memory 25 and can be loaded from magnetic disk 10 and saved to magnetic disk 10.

There are already many documents about the associative memory elements used in the associative memory device in this building, such as ``Logical Memory'' published in the ``Information Processing Handbook'' (published by Ohmsha in May 1947, edited by the Information Processing Society of Japan).

It is introduced in PP13-96 to PP13-99).

According to this, an associative memory device requires an associative memory element having a configuration in which each memory element that stores information is provided with a match detection circuit that checks whether the stored content matches the search information. Therefore, compared to memory elements used in ordinary memory devices that are accessed by supplying an address indicating the storage location of desired data, conventional content addressable memory elements have a more complex structure and a lower cost per bit. It had the disadvantage that it was several tens of times as large.

In order to eliminate this drawback, it is possible to consider an associative memory device configuration in which a normal memory element is used, the contents of all addresses are read, and a single match detection circuit sequentially compares the read results with the search keyword. In this device configuration, the search time is too long compared to the time required to read all the contents, and the performance is limited by the comparison processing capacity.

That is, conventional associative memory devices are expensive and require a long search time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an associative memory device with a new configuration that eliminates the above-mentioned drawbacks.

Associative notes of the present invention 1. C) The first device stores address records and keywords given from the outside in correspondence with each other.
．． a second storage means; a data compression means for compressing the information amount of the keyword to generate a key code; a third storage means for storing the key code in correspondence with the keyword; block address scanning means for sequentially outputting the contents of the third storage means; key code comparison means for comparing the key code with the contents of the third storage means; and a matching output of the key code comparison means;
The first .
word address scanning means that starts scanning the word address of the second storage means; keyword comparison means that compares the keyword with the content of the second storage means and outputs the comparison result to the outside as a matched output; It consists of:

The present invention will be explained in detail below using the drawings.

FIG. 3 is a block diagram of an associative memory device showing one embodiment of the present invention. The content addressable memory device shown in this figure is supplied with a keyword 301, an address record 302, and a registration marker signal 303 from the outside at the time of registration, and is supplied with a search keyword 301 at the time of search, and an address record 304 that matches it is supplied. Output. Keyword 30
When the number of 1's becomes two or more, the portion of the search control circuit 320 in the dashed line block increases in accordance with the number.

Four RAMs (random access memories) are prepared in the content addressable memory device: a record memory 305, a keyword memory 306, a key code memory 307, and a registered marker memory 308, each of which stores records related to disk addresses and keywords. , key codes compressed from keywords, and registration markers are stored. record 30
2 and keyword 301 are multiple words (one word is 8,
The word address is scanned by a word address scanning circuit 310 connected to the RAM during operation. Data compression circuit 311
The keyword 301 supplied to the key code 301 is compressed into a one-word key code, and then supplied to the key code memory 307 and the key code comparison circuit 314. In addition, the registered marker signal 30
3 is input into the registered marker memory 308, and record 30
2. Keyword 301. When registering the key code 313, a registration marker is placed to indicate that the key code 313 has been registered.

Addresses of data blocks returned from a set of records, keywords, code, and registration markers are designated or sequentially scanned by block address scanning circuit 309.

The registration operation of this content addressable memory device is performed as follows.

The sequence controller 312ij activates the block address scanning circuit 309 and sequentially reads the contents of the registered marker memory 308, which means that the data block is empty.
0” is detected, the block address scanning circuit 30
9 is stopped, and °l'', which means that the data block has been registered, is written to the current address of the registration marker memory 308. Also, the data compression circuit 311 compresses the multiple word length keyword into one word length. The obtained key code is written into the key code memory 307.

Furthermore, the sequence controller 312 activates the word address scanning circuit 310 and sequentially scans word addresses starting from address 0, and then transfers the record 302 to the record memory 305 and the keyword 301 to the keyword memory 306.
, respectively, and the registration operation is completed.

Note that the data compression circuit 311 is a part that reduces the word length of the keyword 301. In the present case, the length of multiple words is reduced to a single word length, but this is generally not the case. There are also various methods of compression. The easiest method is to extract one specific word within a keyword as a key code. 1 word length key code 31
Since it is desirable to select data (records and keywords) so that they can be divided equally (separately) into two classes by 3, the data compression circuit 111 is also generally called a badge circuit. The FCC used for error detection and correction can be used to enhance the functionality of this circuit.

The operation of searching the records registered in this way using keywords and finding related records is performed by (1) key code match detection and (2) keyword match detection.

(1) Key code match detection Keyword 301 for external search is in register 3
18 and 319, the data compression circuit 311 generates a key code 313 in the same manner as during registration. Register 319 provides a code indicating the attribute of keyword 301 to sequence controller 312 . The sequence controller 312 activates the block address scanning circuit 309 for the search control circuit 320 specified by the attribute code, and scans the addresses of the key code memory 307 and the registered marker memory 308. The key code comparison circuit 314 compares the content of the key code memory 307 with the key code 313 of the search keyword when the content of the registered marker memory 308 is "1", and the key code is '1' if there is a match, and '0° if there is no match. A match signal 315 is provided to a sequence controller 312 and a keyword comparison circuit 316. The key code match signal 315 of "0" indicates that the contents of the keyword memory 306 indicated by the block address scanning circuit 309 do not match the keyword 301,
The key code matching number 315 in the code indicates that there is a high possibility that they match.

(2) Keyword match detection 9 - When the key code match signal 315 indicates "1", the system controller 312 starts the keyword comparison operation in the keyword comparison circuit. First, the system controller 312 uses the crosspiece control circuit 3 defined by the attribute code tkf.
20, the word address scanning circuit 310 is activated and the word addresses of the keyword memory 306 are sequentially scanned by the word length. The keyword comparison circuit 316 compares the contents of the keyword memory 306 with the externally given keyword 301, and returns "1".
A keyword matching signal 317 is output that indicates a match at "0°" and "mismatch at 0°."A matching record 304 is output from the record memory 305 by scanning the word address. Consistency record 3 output when all match signals 317 are output
04 is valid as a record that matches the keyword 301. This completes the content search.

If the keyword match signal 317 indicates a mismatch,
The scanning of the 10-block address by the block address scanning circuit 309 is restarted, and the operation returns to (1) key code match detection. The system controller 312 performs operations (1) and (2) on all data blocks and ends the search operation.

As mentioned above, since the associative memory device of the present invention uses a normal memory element that stores contents by addressing,
resulting in a significant price drop. Furthermore, since keyword match detection only needs to be performed for keywords that match with the key code, the search time can be significantly reduced compared to conventional associative memory devices that compare all keywords.

FIG. 4 shows another embodiment of the invention. The difference from FIG. 3 is that keywords 302 and records 301 are serially input in word units and loaded into semiconductor RAM 400, and that the first, second, and third storage means shown in the claims are respectively It is formed in a distributed manner in a record area 405, a keyword area 4.06, and a key code area 407 in the semiconductor RAM 400.

Keyword components in data 401 consisting of keywords and records are selectively taken into buffer 418 according to attribute codes added to the keywords, and the output thereof is converted into key code 313 by data compression circuit 311 . When loading data 401 into semiconductor RAM 400, key code 313 is written into RAM 400 via OR circuit 402 after keywords and records are written in sequence.

The address scanning circuit of the semiconductor RAM 400 is further divided into smaller parts as in the case of FIG. 3; an address scanning circuit 411 for the key code area and an address scanning circuit 41 for the record area.
It consists of an address scanning circuit 409 for 0 and keyword areas, and an address scanning circuit 408 for a data block including a set of key code, record, and keyword. The sequence coat roller 312 receives the output of the key code comparison circuit 314, the registration marker signal included in the key code, and the buffer 41.
Data full (indicating blockage) signal 40 coming from 8
4 and the output of the keyword comparison circuit 316, and controls the search processing of the content search. It includes a match record that is inserted into the data block output from the RAM 400 when a match detection signal is output from any of the keyword comparison circuits 316 of the plurality of search control circuits 320. When no match signal is output, data block address scanning circuit 408 advances scanning to the next address.

Now, the number of data blocks stored in the semiconductor RAM 400 is 10, and the number of words in each data block is 128.
shall be. Also, the key code is 1 word, and the keyword is 1
It should be 6 words. The number of keywords is 4. Assume that the number of consistent data blocks is 102. Assuming that the H cycle time of the word line is 100nsee, as in the conventional case,
If all addresses are scanned only for keywords, the search time is 1
6X4X105×102nseC or 640m5e
It is c.

As shown in Figure 4, when searching by key code, 105
data blocks can be reduced to 1/28, that is, 400 data blocks. Therefore, the key code search time is 105X1
02nsee. The search time for 400 keywords is 4 OX16X10 n5ee. In yellow, the total is approximately 11m5ec. Therefore, by adopting the present invention, the search time is reduced to about 1/64.

FIG. 5 shows the procedure for loading and retrieving data blocks.

In order to initially load records and keywords from the backup magnetic disk to the semiconductor RAM 400, data blocks are written to the semiconductor RAM 400 in the order of keyword area 406, record area 405, and key code area 407 (from arrow 501 to 502). . Each block 503 means one word.

When performing a content inspection, the key code area 407, keyword area 406, and record area 405 are read in this order from the starting point 504 according to the arrow. If a mismatch signal is generated when the key code area 407 is finished reading, keyword area 406 and record area 4
05 and jumps to the key code area 407' of the next data block.

If a mismatch signal is generated when the keyword area 406 has been searched, the subsequent record 14-area 405 is not searched and similarly jumps to the key code area 407' of the next data block.

The record area 405 is read and output to the outside only when no mismatch signal is generated even after reading the keyword area 406.

If the keyword area 406 contains multiple keywords, the keywords within the range selected by the attribute code are read sequentially, and if a mismatch signal is generated, the key code of the next data block is read even in the middle. Elijah 407' jumps. In this way, it is possible to narrow down the readable range in the RAM 400 during the accumulation process.

As described above, it can be seen that according to the present invention, the deficiencies of the conventional associative memory structure, such as high cost and excessive search time, can be easily solved.

[Brief explanation of the drawing]

Figures 1(a) and (b) are diagrams showing the configuration of a general database, Figure 2 is a diagram showing the configuration of a normal index table, and Figure 3 is a diagram showing the configuration of an associative memory device according to the first embodiment of the present invention. A block diagram, FIG. 4 is a block diagram of an associative memory device according to a second embodiment of the present invention, and FIG. 5 (al, (b))
is a diagram showing the procedure for storing and retrieving data blocks. 10--Magnetic disk, 15... Index table, 25... Content addressable memory device, 305... Record memory, 306... Keyword memory, 307...
Key code memory, 308... Registration marker, 309.
...Block address scanning circuit, 310... Word address scanning circuit, 311... Data compression circuit, 312
... sequence controller, 314 - key code comparison circuit, 316 ... keyword comparison circuit, 318,
319...Register, 320-...Search control circuit, 4
00... Companion conductor RAM, 402-... OR circuit, 40
8,409,410,411--address scanning circuit,
One 72 Figure 3 Odo U

Claims (2)

[Claims] (1) The first step is to store records and keywords given from the outside in correspondence with each other. a second storage means; a data compression means for compressing the information amount of the keyword to generate a key code; a third storage means for storing the key code in correspondence with the keyword; block address scanning means for sequentially outputting the contents of the third storage means; key code comparison means for comparing the key code with the contents of the third storage means; The first address specified by the address scanning means. a word address scanning means that starts scanning the word address of the second storage means, and a comparison between the keyword and the contents of the second storage means;
An associative memory device comprising keyword comparison means for outputting a comparison result to the outside as a matching output. (2) The content addressable memory device according to claim 1, wherein the data compression means is an error correction circuit.