JPH05109289A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To retrieve data in a short time by using an external address input inputted from the outside and positional information stored in an internal memory area for retrieval jointly and retrieving the data in the memory area. CONSTITUTION:When an address switching signal 5 is made a binary logical value 1, by an address switching circuit 4, the address to the memory area 2 is switched from a first address input 6 to a second address 7 outputted from the memory area 3 for retrieval. At this time, since the input 6 is inputted to the area 3, as well, the address data of the memory area specified by the address 6 in the data of the area 3 is outputted. Then, when the address 0 is supplied as the input 6, the data of the address A001 is outputted. Next, when the signal 5 is made zero, since the input 6 is selected and outputted by the circuit 4, when the output data 8 outputted by supplying successively from the address succeeding to A001 to the address input 6 is read, the target data is found.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory integrated circuit,
In particular, it relates to a large capacity memory integrated circuit used in a computer system.

[0002]

2. Description of the Related Art Generally, the reading of data stored in a memory integrated circuit is performed by selecting an area in which "target data" is stored by an address signal and then permitting the circuit to read by a read control signal. Do it.

As described above, when the address where the "target data" is stored is known, the "target data" can be immediately retrieved. However, if the address where the "target data" is stored is unknown, it is not so easy to retrieve that data.

For example, assume that "target data" is stored somewhere in the memory area, but its address is unknown.

In this case, in order to take out the "target data", it is necessary to read the data one by one from the beginning of the memory area and repeat this until the "target data" is found.

[0006]

In the conventional large-capacity memory integrated circuit, when the stored "target data" is taken out and the address where the data is stored is unknown, the data is stored one by one. The procedure of reading out and determining whether or not it is "target data" had to be repeated until the "target data" was found. For this reason, when the memory area is very large, there is a disadvantage in that a great amount of time is required for searching depending on the place where the "target data" is stored.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a large-capacity memory integrated circuit capable of easily reading data when reading the data.

[0008]

In a memory integrated circuit of the present invention, a search memory area storing position information serving as a base point for each data group of data stored in a memory area and an address of the memory area are designated. An address switching circuit for switching between a first address input input from the outside and a second address input based on the position information output from the search memory area by an address switching signal supplied from the outside is configured. It

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a memory integrated circuit according to an embodiment of the present invention.

The memory integrated circuit 1 shown in FIG. 1 includes a memory area 2 for storing data, a search memory area 3 for storing address information of data stored in the memory area 2,
An address for switching the address input to the memory area 2 between the first input address 6 of the external input address and the second address input 7 output from the search memory area 3 by the address switching signal 5 supplied from the outside. And the selection circuit 4.

At the time of normal memory access, the address switching signal 5 is set to a binary logic value 0. When the address switching signal 5 is set to 0, the address switching circuit 4 supplies the first input address of the external input to the memory area 2. That is, the data in the memory area 2 is output as the output data 8 by the external input address input as the first input address 6.

Next, the address switching signal 5 is set to a binary logical value 1.

The address switching circuit 4 switches the address for the memory area 2 from the first address input 6 to the second address input 7 output from the search memory area 3. At this time, since the first address input 6 is also input to the search memory area 3, the first input address 6 in the data of the search memory area 3 is designated as the second address input. Address data of the memory area to be output.

The relationship between the data in the search memory area 3 and the data in the memory area 2 is shown in FIG.

Reference numeral 9 in FIG. 2 shows a part of the stored data in the search memory area 3. Further, 10 in FIG. 2 shows a part of the stored data in the memory area 2.

An address serving as a base point of the data group in the memory area 2 is written in the search memory area 3. For example, it is assumed that there are three data groups in the memory area, and the respective head addresses are A001, B001, and C001. In this case, A001 is written in address 0, B001 is written in address 1, and C001 is written in address 2 in the search memory area 3.

For example, if "target data" exists in the data group starting from A001 and ending at B001 in the memory area 2, first, the address switching signal 5
To 1.

When the address 0 is supplied as the first address input 6, the data D001 of the address A001 is output as the output data 8 of the memory area 2.

Next, if the address switching signal 5 is set to 0,
Since the address switching circuit 4 selects and outputs the first address input 6, the address A00 is input to the first address input 6.
The "target data" can be found by reading the output data 8 which is sequentially supplied and output from the address next to 1.

[0021]

As described above, according to the present invention, there is provided a search memory area for storing position information serving as a base point for each data group of data stored in the memory area, and an external address input from the outside is provided. By searching the data in the memory area in combination with the position information stored in the search memory area, the data can be searched in an extremely short time.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an address of data stored in a memory area 2 and a data stored in a search memory area 3 in FIG.

[Explanation of symbols]

 1 memory integrated circuit 2 memory area 3 search memory area 4 address switching circuit 5 address switching signal 6 first input address 7 second input address 8 output data

Claims (1)

[Claims] 1. A search memory area storing position information, which is a base point for each data group of data stored in the memory area, a first address input from the outside for designating an address of the memory area, and an external An address switching circuit for switching between a second address input based on the position information output from the search memory area in response to an address switching signal supplied from the memory integrated circuit.