JPS6136628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor testing device that performs various characteristic measurement tests on semiconductor devices. Conventionally, in order to perform a characteristic measurement test on a semiconductor device, such as a DIP type IC, using a semiconductor test device, the semiconductor device was first inserted into a socket provided in the test device, and then a test start switch was operated. ing. As a result, the test device automatically performs dozens of characteristic measurement tests, and finally determines the quality of the semiconductor element. As described above, in the conventional method, a characteristic measurement test cannot be performed unless the test start switch is operated after inserting the semiconductor element into the socket, which has the drawback of poor operability. Furthermore, the conventional method has the disadvantage that there is wasted idle time between inserting the semiconductor element into the socket and operating the test start switch, resulting in a long test time. These drawbacks become particularly noticeable when testing a large number of semiconductor devices. The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor testing device that is highly operable and capable of conducting characteristic measurement tests of semiconductor elements in a short period of time. There is a particular thing. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a semiconductor testing apparatus according to the present invention. In the figure, 1 is for example DIP where various characteristic measurement tests are performed.
a socket portion into which a type of semiconductor device under test is inserted;
Reference numeral 2 denotes a tester section that performs a characteristic measurement test of the semiconductor device under test inserted into the socket section 1, and 3 an insertion detection section that detects whether the semiconductor device under test is completely inserted into the socket section 1. The insertion detection section 3 detects that the semiconductor device under test is completely inserted into the socket section 1, and holds the test start signal STRT at a high level. Furthermore, by holding this test start signal STRT at a high level, the tester section 2
In addition to executing various characteristic tests on the semiconductor device under test inserted into the test device, the test signal TEST held at a low level during the test execution period is supplied to the insertion detection section 3 to stop the insertion detection operation. It's getting old. FIG. 2 is a detailed circuit diagram showing the insertion detection section 3 together with the socket section 1. As shown in FIG. As shown in the figure, the insertion detection section 3 is roughly divided into two continuity detection sections 11 ,
12 , a test start signal generating section 13 , and a detection operation control section 14 . In the figure, 15a to 15c are the socket parts 1.
When the semiconductor device under test is completely inserted into the terminal, the predetermined terminals of the semiconductor device under test are the contact electrodes. Each of the electrodes 15a to 15c is connected to the tester section 2, and the electrode 15a is connected to a ground potential point via a normally open contact 16a of a relay device 16 of the detection operation control section 14 , which will be described later. , 15c are connected to the respective input ends of the continuity detection sections 11 and 12 via the normally open contacts 16b and 16c of this relay device 16 , respectively. The two continuity detection sections 11 and 12 have the same configuration, and the normally open contact 16b or 16
a diode 17 having one end connected to its cathode; a capacitor 18 connected between the anode of this diode 17 and a ground potential point; a resistor 19 having one end connected to the anode of the diode 17; A PNP transistor 20 whose other end is connected to its base, a resistor 21 connected between the emitter of this transistor 20 and the positive power supply voltage V _CC application point, and a connection between the collector of the transistor 20 and the ground potential point. Resistor 2 connected between
2. An NPN transistor 2 whose base is connected to the connection point between the transistor 20 and the resistor 22 and whose collector is connected to the ground potential point.
3. A resistor 24 is connected between the collector of the transistor 23 and the power supply voltage application point, and its base is connected to the connection point between the transistor 23 and the resistor 24, and its emitter is connected to the ground potential point. Each of them is composed of an NPN transistor 25, a resistor 26 connected between the collector of the transistor 25 and a power supply voltage application point, and a diode 27 whose cathode is connected to the connection point between the transistor 25 and the resistor 26. . Further, the anodes of the diodes 27 of the two continuity detection sections 11 and 12 are connected in common, and the common connection point is connected to the input end of the test start signal generation section 13 . This test start signal generating section 13 is connected to a diode 28 whose anode is connected to the anode common connection point of the diode 27;
a resistor 29 connected between the anode of the diode 8 and the power supply voltage application point; an NPN transistor 30 to which the cathode of the diode 28 is connected to its base and whose emitter is connected to the ground potential point; and a collector of the transistor 30. a resistor 31 connected between the transistor 30 and the power supply voltage application point, a diode 32 whose cathode is connected to the connection point between the transistor 30 and the resistor 31, and a diode 3 whose anode is connected to the anode of this diode 32.
3. A resistor 34 connected between the connection point of the two diodes 32 and 33 and the power supply potential application point, the cathode of the diode 33 being connected to its base and its emitter being connected to the ground potential point. An NPN transistor 35, a variable resistor 36 connected between the collector of the transistor 35 and the power supply voltage application point, and a variable resistor 37 connected between the connection point of the transistor 35 and the variable resistor 36 and the ground potential point to perform integration. A capacitor 37 forming a circuit, the variable resistor 36 and the capacitor 37
A diode 38 whose anode is connected to the connection point with the NPN transistor 39 whose cathode is connected to its base and whose emitter is connected to the ground potential point, and the collector of this transistor 39 and the supply voltage applied. a resistor 40 connected between the point and the transistor 39;
Its base is connected to the connection point between the resistor 40 and the resistor 40, and its emitter is connected to the ground potential point.
NPN transistor 41, this transistor 41
A resistor 42 is connected between the collector of the transistor 41 and the power supply voltage application point, a capacitor 43 has one end connected to the connection point between the transistor 41 and the resistor 42, and a capacitor 43 is connected between the other end of the capacitor 43 and the ground potential point. The capacitor 4 is composed of a resistor 44 connected to the capacitor 43 to form a differential circuit, and a diode 45 connected in parallel with the resistor 44.
3. A terminal 46 for outputting a test start signal STRT is provided from the common connection point of the resistor 44 and diode 45. The detection operation control section 14 also includes a terminal 47 to which the test signal TEST output from the tester section 2 is supplied, a resistor 48 connected to this terminal 47,
The other end of this resistor 48 is connected to its base, and its emitter is connected to the ground potential point.
NPN transistor 49, this transistor 49
A coil 16A of the relay device 16 is connected between the capacitor and the power supply voltage application point, a resistor 50 has one end connected to the connection point between the transistor 49 and the coil 16A, and the other end of the resistor 50 has its base. a resistor 52 connected between the collector of this transistor 51 and a power supply voltage application point;
a capacitor 53 connected between the connection point between the resistor 52 and the ground potential point and forming an integrating circuit together with the resistor 52;
NPN whose base is connected to the connection point with 3 and whose collector is connected to the power supply voltage application point
a transistor 54; a resistor 55 connected between the emitter of the transistor 54 and a ground potential point;
Its cathode is connected to the connection point between the transistor 54 and the resistor 55, and its anode is connected to the two diodes 3 of the test start signal generating section 13 .
Diode 5 connected to the common connection point of 2 and 33
It consists of 6. Next, the operation of the apparatus configured as described above will be explained using the timing chart shown in FIG. In the description, it is assumed that the power supply voltage V _CC level corresponds to a high logic level, and the ground voltage level corresponds to a low logic level. First, when the semiconductor device under test is not inserted into the socket section 1, the test signal TEST supplied from the tester section 2 to the insertion detection section 3 becomes high level, and the transistor 49 of the detection operation control section 14 , which uses this signal as a base input, is turned on. The above transistor 4
9 is on, the coil 16A of the relay device 16 is driven, and the contacts 16a to 16c are closed. Further, when the transistor 49 is on, the transistor 51 following it is off, and the transistor 51 is off.
4 is turned on, and the emitter level of this transistor 54 becomes high level. Further, since no semiconductor device under test is inserted into the socket portion 1, no current flows through the diodes 17 of the two continuity detection portions 11 and 12 , and the transistor 20 is turned off. When this transistor 20 is off, the following transistor 23 is turned off and the transistor 25 is turned on, and the collector levels of the transistors 25 of these two conduction detection sections 11 and 12 are both at a low level as shown in FIG. . When the collector level of the transistor 25 is both at a low level, no current flows through the diode 28 of the test start signal generating section 13 , the transistor 30 is turned off, and its collector level becomes a high level as shown in FIG. . At this time, since the emitter level of the transistor 54 of the detection operation control section 14 is at a high level, current flows through the diode 33 via the resistor 34 and the transistor 35 is turned on. When the transistor 35 is on, no current flows through the capacitor 37 constituting the integrating circuit, and the anode level of the diode 38 becomes a low level. Therefore, at this time, transistor 39 is turned off, transistor 41 following it is turned on, and test start signal STRT becomes low level as shown in FIG. Therefore, the tester section 2 does not operate at this time. Next, the operation when a semiconductor device under test is inserted into the socket portion 1 will be explained. First, when the semiconductor element under test is inserted, if the insertion is not complete and one of the electrodes 15a to 15c of the socket part 1 does not come into contact with the terminal of this semiconductor element, the two continuity detection parts 11 and 12 No current flows through one or both diodes 17. As a result, one or both of the transistors 25 of the conduction detection sections 11 and 12 are turned on, and their collector level becomes low level. The above two continuity detection parts
When one of the transistors 25, 11 and 12 , is on, no current flows through the diode 28 of the test signal generating section 13 , and the transistor 30 is turned off, as in the case where the semiconductor device under test is not inserted. As a result, even if the semiconductor device under test is inserted into the socket 1, if the insertion is not complete, the transistor 41 of the test start signal generating section 13 is turned on and the test start signal STRT remains at a low level. Therefore, the tester section 2 does not operate at this time either. On the other hand, if the semiconductor device under test is completely inserted into the socket portion 1, the electrode 15 will be connected from the terminal that is in contact with the electrode 15b inside the semiconductor device.
A current path from the terminal in contact with electrode 15a and a current path from the terminal in contact with electrode 15c to the terminal in contact with electrode 15a are established, and the resistances 19 of the two continuity detection units 11 and 12 are established. , diode 17
A current flows toward the ground potential through the semiconductor device under test. If the power supply voltage V _CC is set to +5 V and the resistance value of the resistor 19 is set to about 1 MΩ, the current flowing through the semiconductor device under test will be 5 μA or less, and even if this current flows, the semiconductor device under test will The device will not be destroyed. Then, current flows through the diodes 17 of the two continuity detection sections 11 and 12 , and continuity is measured in the semiconductor device under test, so that the transistor 2
5 is turned off and its collector level simultaneously rises to a high level as shown in FIG. When the collector level of the transistor 25 rises to a high level, a forward current flows through the diode 28 of the test start signal generating section 13 , turning on the transistor 30 and raising the collector level as shown in FIG. Go down to a lower level. When the collector level of the transistor 30 falls to a low level, the current that has been flowing through the diode 33 stops flowing and the transistor 35 is turned off. When the transistor 35 is turned off, the capacitor 37 constituting the integrating circuit
A charging current flows through the variable resistor 36, and the terminal level of the capacitor 37, that is, the collector level of the transistor 35, gradually approaches a high level as shown in _FIG. and V of diode 38
When the voltage exceeds _F , this transistor 39 is turned on. That is, the transistor 39 is turned on a predetermined time after the transistor 35 is turned off, and this time difference is determined by the resistance value of the variable resistor 36 and the capacitance value of the capacitor 37 that constitute the integration circuit. When the transistor 39 is turned on, the transistor 41 following it is turned off, and the collector level of this transistor 41 rises to a high level as shown in FIG. Furthermore, when the collector level of the transistor 41 rises to a high level, this rise is detected by a differentiator circuit consisting of a capacitor 43 and a resistor 44, and a high level test start signal is sent to a terminal 46 as shown in FIG.
STRT is obtained. When the high-level test start signal STRT is input, the tester section 2 holds the test signal TEST supplied to the insertion detection section 3 at a low level for a predetermined period, and also detects the semiconductor device under test inserted into the socket section 1. Perform various characteristic measurement tests. At this time, the transistor 49 of the detection operation control unit 14 whose base input is the test signal TEST is turned off, and the coil 16A that has been driven until now is not driven. As a result, the contacts 16a to 16c of the relay device 16 , which have been in the closed state, are now in the open state, and the terminals of the semiconductor device under test inserted into the socket portion 1 are connected only to the tester portion 2. Therefore, even if various characteristic measurement tests are performed in this state, the insertion detection section 3 will not affect the tester section 2. Also, during execution of the above test, the detection operation control unit 14
The transistor 49 is turned off, the transistor 51 following it is turned on, and the transistor 54 following it is turned off, so that the emitter level of this transistor 54 becomes a low level as shown in FIG.
When the emitter level of the transistor 54 is at a low level, no current flows through the diode 33 of the test start signal generating section 13 , so the transistor 35, which has been off until now, remains off. As a result, the integrating circuit consisting of variable resistor 36 and capacitor 37 continues its integrating operation. On the other hand, the above contact point 1
When 6a to 16c are opened, the current that has been flowing through the diodes 17 of the two continuity detection sections 11 and 12 stops flowing, the transistor 25 is turned on, and its collector level becomes low as shown in FIG. Go down. Further, when the collector level of the transistor 25 falls to a low level, the transistor 30, which has been on until now, is turned off and its collector level rises to a high level as shown in FIG. Next, when the execution of the various characteristic measurement tests is completed, the tester section 2 inverts the test signal TEST, which has been kept at a low level, to a high level again.
Then, when the signal TEST rises to a high level, the transistor 49 of the detection operation control section 14 is turned on again, and each contact 16a to 16c of the relay device 16 is turned on again.
is closed. As a result, two continuity detection sections 11 ,
Twelve transistors 25 are both turned off, and their collector levels rise to a high level as shown in FIG. Furthermore, as the collector level of the transistor 25 rises to a high level,
The transistor 30, which has been off until now, is turned on and its collector level drops to a low level as shown in FIG. On the other hand, when the transistor 49 is turned on, the transistor 51 following it is turned off. When the transistor 51 is turned off, a charging current flows through the resistor 52 to the capacitor 53 constituting the integrating circuit, and the terminal level of the capacitor 53 gradually approaches a high level. Further, an emitter current sequentially flows through the transistor 54 which receives the terminal level of the capacitor 53, and the emitter level gradually approaches a high level as shown in FIG. That is, the test start signal TEST
Since the emitter level of transistor 54 rises to a high level a predetermined time after rising to a high level, there is no period during which both the collector level of transistor 30 and the emitter level of transistor 54 are at high level at the end of the test execution. Therefore, during this period, the test start signal STRT will not go high and the measurement test will not be executed again. Furthermore, by pulling out the semiconductor device under test on which the execution of various characteristic measurement tests has been completed from the socket section 1, the two continuity detection sections 11 and 12 are removed.
The current that was flowing through the diode 17 stops flowing. As a result, the transistor 20 is turned off, the transistor 23 that follows it is also turned off, and the transistor 25 that follows it is turned on, and the collector level of this transistor 25, which had been at a high level until now, becomes a low level as shown in FIG. Go down. Furthermore, as the transistor 25 turns on and its collector level drops to a low level, the transistor 30, which has been on until now, turns off and its collector level rises to a high level as shown in FIG. Further, at this time, since the emitter level of the transistor 54 of the detection operation control section 14 is already at a high level, when the collector level of the transistor 30 rises to a high level, current flows through the diode 33 and turns on the transistor 35. As a result, the collector level of this transistor 35 is at the third level.
Descend to low level as shown. Further, when the transistor 35 is turned on, the transistor 39 following it is turned off, and the transistor 41 following it is turned on, and its collector level drops from a high level to a low level as shown in FIG. When the collector level of the transistor 41 falls to a low level, this fall is detected by a differentiating circuit consisting of a capacitor 43 and a resistor 44, but since this detection signal is negative, it flows through a diode 45 to the ground potential point. Therefore, at this time, the test start signal
STRT remains at a low level. In this way, in the above embodiment, there are two continuity detection sections.
11 and 12 detect that the semiconductor device under test has been inserted into the socket 1, and in response to this detection output, a high level test start signal STRT is generated from the test start signal generator 13 , and this signal
Since the tester unit 2 is operated by STRT to perform various characteristic measurement tests of the semiconductor device under test, there is no need to operate a test start switch as in the conventional case, and the operability is extremely high. Become. Furthermore, since the idle time between the insertion of the semiconductor device under test into the socket portion 1 and the execution of the measurement test is extremely short, the measurement test time can be significantly shortened compared to the conventional method. Note that the present invention is not limited to the above-mentioned embodiment; for example, in the above-mentioned embodiment, the socket portion 1
The case has been described in which the two continuity detectors 11 and 12 detect continuity between the three terminals of the semiconductor device under test inserted into the device. It's okay. By detecting continuity at all terminals of the semiconductor device under test, the test start signal STRT will not go to a high level if there is a bend in the terminal, poor contact with the socket part 1, etc. Semiconductor elements that have been determined to be defective due to such causes can be repaired by testing again. Further, in the above embodiments, the case where the circuit is constituted by discrete components has been described, but it goes without saying that a TTL IC or a MOS type IC may be used. As described above, according to the present invention, it is possible to provide a semiconductor testing device that has high operability and can perform a characteristic measurement test of a semiconductor device in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing one embodiment of a semiconductor testing device according to the present invention, FIG. 2 is a detailed view of a part of the device of the above embodiment, and FIG. 3 is a timing chart for explaining the above embodiment. be. 1... Socket part, 2... Tester part, 3... Insertion detection part, 11 , 12 ... Continuity detection part, 13 ...
Test start signal generation section, 14 ...Detection operation control section.

Claims (1)

[Claims] 1. A socket portion into which a semiconductor device under test having multiple terminals is inserted, and a semiconductor device under test between one terminal of the semiconductor device under test inserted into the socket portion and a specific terminal set to a reference potential. At least two connection state detection means for detecting the connection state between the terminal and the socket portion by detecting the current flowing through the inside of the element, and all of the connection state detection means described above detect the connection state between the terminal and the socket portion. a test start signal generating means for generating a test start signal when the test start signal is applied; and a characteristic measuring means for performing various characteristic measurement tests of the semiconductor device under test inserted into the socket section in response to the test start signal. A semiconductor testing device characterized by: