JPS6135585B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention increases the processing capacity of a communication control device,
When selecting the register for the line connection adapter,
The present invention relates to a communication control device that enables quick selection.

An example of a conventional information processing system is shown in FIG.
The communication control unit CCU, which is controlled by the central processing unit CPU, connects the communication line CL via the modem device MDM.
is connected to. The communication control unit CCU contains a microprocessor PU and random access memory.
It has MEM, interface IF, and line connection facility LCF. The line connection mechanism LCF is equipped with, for example, 16 line connection adapters LCA for each line. Each line connection adapter LCA is a register that can be controlled from the processor in order to control the interface with the modem, serial/parallel conversion of transmitted and received data, and control the interface with the processor.
In FIG. 1, eight RGs RG0 to RG7 are used, and a predetermined number of registers among them are used for control according to each function. Further, the line connection adapter LCA includes a decoder DEC, which decodes the register selection address information sent from the processor PU on the bus B1, and selects the registers E0 to E7. Bus B2 is a bidirectional data bus, and a signal line C2 indicates the transfer direction. For example, when C2 is "0", the data is read from the outside to the processor, and when C2 is "1", the data is written from the processor to the outside. In addition, C1 indicates the validity of B2 information, and furthermore, C1 indicates the validity of B2 information.
The interrupt to is indicated by C3. At this time memory
Address assignment and storage information for MEM are as shown in Figure 2. Addresses are indicated in hexadecimal codes from X"0000" to X"FFFF". LCW indicates line control word, 16 lines from LCW0 to LCW15〓〓〓〓〓
The minute uses 256 bytes from X"0000" to X"00FF". Each line control word LCW consists of 16 bytes, the contents of which are shown on the left side of FIG. The 0th byte LMD specifies the line operation mode, line connection adapter type, etc. through initial settings from the central processing unit, and the 1st byte PCD
is a byte that specifies the line transmission control procedure,
Similar to LMD, initial settings are performed, and the second byte, PYN, indicates the line number for the audio adapter. The third byte, CMD, is a byte that stores the line command code and is rewritten every time a command is issued from the central processing unit. The control program CTP is stored in the next addresses X "0100" to X "FEFF", and the control information for the line connection adapter LCA registers is stored in registers RG0 to RG7 from the next addresses They are stored in areas R0 to R7 in correspondence. By accessing the address corresponding to the register at this address, the processor can load information on bus B2 in FIG. 1 to the register, and conversely, load information in the register onto the bus. and X “FF80” to X “FFFF”
can be used as a control register related to the processor PU and interface IF.

When the processor PU accesses the registers in the line connection adapter LCA, the adapter
From the line control word LCW corresponding to LCA, its second
Create a memory address corresponding to the register of the target line from the contents of the byte PYN, that is, the line number, and the register number of the adapter in question, and set that address in the index register normally provided in the processor PU. do. By creating and executing an instruction that uses the contents of the index register as an address, the LCA register can be accessed. Creating the memory address, that is, accessing it using the index register, requires only a processor.
This will increase the load on the PU. For example, the 6th
The specified address in the line connection adapter shown in the figure is an address modification circuit that uses an index register for the address created by the processor.
It is necessary to qualify the IDX to obtain a real address, and every time the line connection adapter LCA is specified, it is converted to a predetermined value starting from address zero, so if these addresses are created frequently, It may take up to about half of the processing time required to control one transmitted/received character.

An object of the present invention is to provide a communication control device that improves the above-mentioned drawbacks, increases processing capacity by adding configurations within the communication control device, and enables register selection of a line connection adapter to be processed in a short time. It's about doing.

Embodiments of the present invention shown in the drawings will be described below. FIG. 3 is a diagram corresponding to FIG. 2 showing the address allocation of the memory used in the embodiment of the present invention. FIG. 4 is a diagram corresponding to FIG. 1, showing the configuration of a communication control device using the memory to which the addresses shown in FIG. 3 are assigned. Further, FIG. 7 is an explanatory diagram of address modification in the embodiment of the present invention shown in correspondence with FIG. 6, and is a diagram illustrating the explanation of FIG. 4 in an easy-to-understand manner.

As the memory address assignment shown in Figure 3,
In the present invention, the area EXR, which was conventionally used as a control register, has the following configuration without providing an area for the individual register control information LCA0 to LCA15 of the line connection adapter shown in FIG. That is, one temporary address area is provided corresponding to the register for controlling the line connection adapter, and in FIG. 3, a part R0 is provided for storing control information shared by the registers of each adapter for the area from addresses X "FF80" to X "FF87". ~R7, and a partial LCN that stores information specifying a certain adapter for the area from X"FF88" to X"FF8F". The addresses for accessing these areas are called temporary addresses because they do not have a one-to-one correspondence with the actual addresses (absolute addresses) of each register in the line connection adapter LCA.

When the control program of the processor PU accesses the register of the line connection adapter, it stores the contents of the line number in the line control word LCW in the register (shown as LCNR in Figure 4) in the modifier circuit IDX before accessing. Set. Next, the processor PU
In the above-mentioned memory, a temporary address is created, the memory is accessed, and predetermined contents are stored. The area LCN stores the contents of the register LCNR, and the areas R0 to R7 store the control contents of each register of the adapter. Next, when actually accessing the register, the lower 4 bits (variable part) of the address are used to directly access the real memory.
The upper 3 bits obtain the modified address in the modification circuit IDX as the contents of the register LCNR. Therefore, by simply issuing a temporary address for the memory area EXR, any register LCA can be quickly accessed using the address information obtained from the contents of the register LCNR and the variable part of the lower 4 bits of the temporary address. If the register of the same line connection adapter is to be changed to a different register, the memory addresses X "FF80" to X "FF87" are made variable without changing the LCN set.

FIG. 4 is a diagram showing a specific example of a device that performs the above-mentioned operation, where LCNR is a line number selection register, A1,
A2 and A3 indicate AND circuits. When the processor PU accesses the memory address X "FF88", bits D4 to D7 of the bus B2 are set in the register LCNR, and the signal S1 is obtained by the decoder DEC based on the address information on the bus B1 and C1 and C2. It will be done. A specific example of the decoder DEC is a logic circuit shown in FIG. The signal S2 is the result of judgment that one of the addresses from X"FF80" to
This is the selection signal for the line connection adapter LCA. Further, the signal S3 indicates that any one of the addresses from X"FF80" to X"FF87" has been accessed. Register LCNR is set via AND circuit A1 by the information on signal S1 and bus B2, and a bit representing the line number appears on bus B4. Bus B3 indicates the lower 3 bits MA13 to MA15 of bus B1, and the variable part address is obtained on bus B5 by signal S3 via AND circuit A3, and the register
Set it as the selected address of RG. The bus B6 indicates the line number, which is the content of the bus B4, by the signal S3, and eventually the LCA line number and register number are obtained on the bus B7. When a line number is set in the register LCNR, a register number prefixed with the line number set in the LCNR is automatically obtained by accessing the temporary address each time the address is set.

In this way, according to the present invention, when selecting the absolute address of the register of the line connection adapter, at least the information about the line number is obtained separately without having to obtain the entire address each time. can be obtained in a short time, and the communication control device has more time for other processing, and its processing capacity can be greatly improved. This method does not require the use of the index register of the processor, and has the effect of facilitating program creation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional information processing system, FIG. 2 is a diagram showing address allocation and stored information in the memory of FIG. 1, and FIG. A diagram showing stored information, FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is a specific circuit diagram of the decoder in FIG. 4.
FIG. 6 is a diagram for explaining address modification in the configuration shown in FIG. 1, and FIG. 7 is a diagram for explaining address conversion in FIG. 4. CPU: central processing unit, CCU: communication control unit, MDM: modem, LCF: line connection mechanism, LCA: line connection adapter, PU: microprocessor, MEM: memory, DEC: decoder , RG0, RG1, ......RG7... register, LCNR... line number selection register. 〓〓〓〓〓

Claims (1)

[Claims] 1. In a communication control device of an information processing system controlled by a central processing unit and connected to a communication line via a modem device, the communication control device is equipped with a memory, an information processing device, and a line connection adapter, and the information processing device in the memory One provisional address area corresponding to the line connection adapter control register is provided in an arbitrary area of the address space accessible by the control program, and the address information is accessed to select the number of the line connection adapter; By obtaining the variable part address information regarding the temporary address area and combining them, a plurality of line connection adapters and control registers in the adapters can be selected simply by accessing the temporary address area by the control program. communication control device.