JPS6135489U - Panel type television receiver - Google Patents
Panel type television receiverInfo
- Publication number
- JPS6135489U JPS6135489U JP11965184U JP11965184U JPS6135489U JP S6135489 U JPS6135489 U JP S6135489U JP 11965184 U JP11965184 U JP 11965184U JP 11965184 U JP11965184 U JP 11965184U JP S6135489 U JPS6135489 U JP S6135489U
- Authority
- JP
- Japan
- Prior art keywords
- test pattern
- display
- pattern data
- oscillator
- television receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
区面は本考案の実施例を示すもので、第１図は第１実施
例の回路構成を示すブ冶ツク図、第２図ａ−Ｃはテスト
パターンの表示例を示す図、第３図は第２実施例の回路
構成を示すブロック図、第４図は第３実施例の回路構成
を示すブロック図、第５図ａ，ｂは内部回路で作成した
カラーテストパターン信号とテストパターン表示画面と
の関係を示す図、第６区はカラーテストパターンの他の
表示例を示す図である。
１１・・・信号ライン、１２・・・Ａ／Ｄ変換回路、１
３・・・同期分離回路、１４．１５・・・コントラスト
調整用可変抵抗、１６・・・制御回路、１７Ａ〜１７Ｃ
・・・切換スイッチ、１８．３０・・・シフトレジスタ
、１９・・・テストパターンデータ記憶用ＲＯＭ，２ｌ
・・・発ｍ！、２２−・・カウ−ンタ、２３・・・カウ
ンタ、２４・・・アドレスカウンタ、２５・・・ラッチ
回路、２６・・・信号電極駆動回路、２７・・・電圧発
生回路、２９・・・液晶表示パネル、３１・・・走査電
極駆動回路、４１・・・カウンタ、４２・・・托進カウ
ンタ、４３・・・デコーダ、５１・・・信号ライン、５
２・・・色復調回路、５３・・・同期分離回路、５４ａ
〜５４ｃ・・・Ａ／Ｄ変換回路、５７・・・発振回路、
５８，５９，６１．６２，６３・・・カウンタ、６４〜
６６・・・デコーダ。The sections show an embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration of the first embodiment, FIGS. is a block diagram showing the circuit configuration of the second embodiment, FIG. 4 is a block diagram showing the circuit configuration of the third embodiment, and FIGS. 5 a and 5 b are color test pattern signals and test pattern display screens created by the internal circuit. The sixth section is a diagram showing another display example of the color test pattern. 11... Signal line, 12... A/D conversion circuit, 1
3... Synchronization separation circuit, 14.15... Variable resistor for contrast adjustment, 16... Control circuit, 17A to 17C
...Selector switch, 18.30...Shift register, 19...Test pattern data storage ROM, 2l
...Running! , 22-... Counter, 23... Counter, 24... Address counter, 25... Latch circuit, 26... Signal electrode drive circuit, 27... Voltage generation circuit, 29... Liquid crystal display panel, 31... Scanning electrode drive circuit, 41... Counter, 42... Transmission counter, 43... Decoder, 51... Signal line, 5
2... Color demodulation circuit, 53... Synchronization separation circuit, 54a
~54c... A/D conversion circuit, 57... oscillation circuit,
58, 59, 61. 62, 63...Counter, 64~
66...Decoder.
Claims (1)
出力信号を基準として水平及び垂直の内部同期信号を発
生する手段と、上記発振器の出力信号からテストパター
ンデータを発生するパターンテータ発生手段と、テレビ
受信信号の表示とテストパターンの表示を切換指定する
手段と、この手段によりテストパターンの表示が指定さ
れた際に上記内部同期信号及び上記パターンデータ発生
手段から出力されるパターンデータにより表示部にテス
トパターンを表示する手段とを具備したことを特徴とす
るパネル型テレビジョン受像機。an oscillator that generates an internal reference frequency signal, means for generating horizontal and vertical internal synchronization signals using the output signal of the oscillator as a reference, pattern data generating means for generating test pattern data from the output signal of the oscillator, and a television set. means for specifying switching between the display of the received signal and the display of the test pattern; and when the display of the test pattern is specified by this means, the test pattern is displayed on the display section using the internal synchronization signal and the pattern data output from the pattern data generation means. 1. A panel type television receiver, comprising means for displaying a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11965184U JPS6135489U (en) | 1984-08-03 | 1984-08-03 | Panel type television receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11965184U JPS6135489U (en) | 1984-08-03 | 1984-08-03 | Panel type television receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6135489U true JPS6135489U (en) | 1986-03-04 |
Family
ID=30678520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11965184U Pending JPS6135489U (en) | 1984-08-03 | 1984-08-03 | Panel type television receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6135489U (en) |
-
1984
- 1984-08-03 JP JP11965184U patent/JPS6135489U/en active Pending
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