JPS6134982A - Manufacture of semiconductor diode - Google Patents

Manufacture of semiconductor diode

Info

Publication number
JPS6134982A
JPS6134982A JP15397084A JP15397084A JPS6134982A JP S6134982 A JPS6134982 A JP S6134982A JP 15397084 A JP15397084 A JP 15397084A JP 15397084 A JP15397084 A JP 15397084A JP S6134982 A JPS6134982 A JP S6134982A
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor diode
manufacturing
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15397084A
Other languages
Japanese (ja)
Other versions
JPH0713966B2 (en
Inventor
Junichi Nishizawa
潤一 西澤
Kaoru Mototani
本谷 薫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP59153970A priority Critical patent/JPH0713966B2/en
Publication of JPS6134982A publication Critical patent/JPS6134982A/en
Publication of JPH0713966B2 publication Critical patent/JPH0713966B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Abstract

PURPOSE:To obtain a high-quality semiconductor diode, by heating a substrate within a growth chamber evacuated to an ultra-high vacuum, and introducing from the outside a gas containing component elements to be grown on the substrate so that monomolecular layers of these elements are epitaxially grown one by one. CONSTITUTION:A gate valve 2 is opened so that a growth chamber is evacuated to about 10<-7>-10<-8>Pa by means of an ultra-high vacuum evacuating unit 3. A GaAs substrate 18 is then heated by a heater 16 to about 300-800 deg.C and a valve 8 is opened for 0.5-10sec to introduce TMG12 into the chamber until the pressure therein becomes about 10<-1>-10<-7>Pa. That TMG is then discharged from the growth chamber 1, and a valve 5 is opened for 2-200sec to introduce AsH3 13 into the chamber 1 until the pressure therein becomes 10<-1>-10<-7>Pa. According to this method, a crystalline monomolecular layer of GaAs can be grown. An impurity can be added in a similar manner as the growth of GaAs: in case of P type impurity, a gas containing Ga of Family III and Zn of Family II, and in case of N type impurity, a gas containing As of Family V and S of Family VIis introduced. Thus, a monomolecular layer added with P or N type impurity can be grown.

Description

【発明の詳細な説明】 [:g!明の技術分野] 本発明は半導体ダイオードの製造方法に関する。[Detailed description of the invention] [:g! Technical field of Ming Dynasty] The present invention relates to a method of manufacturing a semiconductor diode.

[先行技術とその問題点] 従来から半導体の薄膜結晶を得るための気相エピタキシ
ー技術として、有機金属気相成長法(以下、MO−CV
D法と呼ぶ)、分子線エピタキシー法(以下、MFIE
法と呼ぶ)、原子層エピタキシー(以下、ALE法と呼
ぶ)などが知られている。しかし、MO−CVD法はソ
ースとして■族、V族元素を水素ガス等をキャリアとし
て、同時に反応室へ導入し、熱分解によって成長させる
ため、成長層の品質が悪い。また、単分子層オーダーの
制御が困難である等の欠点がある。
[Prior art and its problems] Conventionally, metal organic chemical vapor deposition (hereinafter referred to as MO-CV) has been used as a vapor phase epitaxy technique for obtaining thin film crystals of semiconductors.
D method), molecular beam epitaxy method (hereinafter referred to as MFIE)
(hereinafter referred to as ALE method), atomic layer epitaxy (hereinafter referred to as ALE method), and the like are known. However, in the MO-CVD method, group (I) and V-group elements are introduced as a source and hydrogen gas or the like is used as a carrier at the same time into a reaction chamber and grown by thermal decomposition, resulting in poor quality of the grown layer. Further, there are drawbacks such as difficulty in controlling the monolayer order.

一方、超高真空を利用した結晶成長法としてよく知られ
るlE法は、物理吸着を第一段階とするために、結晶の
品質は化学反応を利用した気相成長法に劣る。GaAs
のようなm−v放間の化合物半導体を成長する時には、
■族、V族元素をソースとして用い、ソース源自体を成
長室の中に設置している。このため、ソース源を加熱し
て得られる放出ガスと蒸発量の制御、および、ソースの
補給が困難であり、成長速度を長時間一定に保つことが
困難である。また、蒸発物の排気など真空装置が複雑に
なる6更には、化合物半導体の化学量論的組成(ストイ
キオメトリ−)を精密に制御することが困難で、結局、
高品質の結晶を得ることができない欠点がある。
On the other hand, the 1E method, which is well known as a crystal growth method using an ultra-high vacuum, uses physical adsorption as the first step, so the quality of the crystal is inferior to the vapor phase growth method using a chemical reaction. GaAs
When growing a compound semiconductor with an m-v radiation period such as
Group ① and Group V elements are used as sources, and the sources themselves are installed in the growth chamber. For this reason, it is difficult to control the amount of released gas and evaporation obtained by heating the source, and to replenish the source, making it difficult to keep the growth rate constant for a long time. In addition, the vacuum equipment becomes complicated due to evacuation of evaporates, etc. 6 Furthermore, it is difficult to precisely control the stoichiometric composition (stoichiometry) of compound semiconductors, and as a result,
There is a drawback that high quality crystals cannot be obtained.

更にALE法は、T、5untolaらがυ、S、P、
 NQ4058430(1977)で説明しているよう
に、半導体元素をパルス状に供給し、基板に付着させる
ことにより結晶を原子層ずつ成長させるものであるが、
半導体の単結晶を成長させることができない。即ち、単
結晶の薄膜を形成させるために、同じグループのM、P
e5saらが用いた方法は、ALE法でなく、1984
年の米真空協会の論文集(J、Vac、Sci、Tec
hnol、A2(1984)418)に発表しているよ
うに前記MBE法によるものである。
Furthermore, the ALE method has been proposed by T,5untola et al. for υ,S,P,
As explained in NQ4058430 (1977), a semiconductor element is supplied in a pulsed manner and attached to a substrate, thereby growing a crystal one atomic layer at a time.
It is not possible to grow single crystals of semiconductors. That is, in order to form a single crystal thin film, M, P of the same group
The method used by e5sa et al. is not the ALE method, but the 1984
Proceedings of the Vacuum Society of America (J, Vac, Sci, Tec
The method is based on the above-mentioned MBE method, as disclosed in J. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. H. Hnol, A2 (1984) 418).

このように、MO−CVD法やMBIE法では化学量論
的組成を満足する高品質の結晶を単分子層オーダーで形
成することが困難な一方、ALE法では単結晶が得られ
ない欠点があった。
As described above, while it is difficult to form high-quality crystals that satisfy the stoichiometric composition on the order of a monomolecular layer using the MO-CVD method and the MBIE method, the ALE method has the disadvantage that a single crystal cannot be obtained. Ta.

[発明の目的] 本発明は上記従来技術の欠点を除き、化学量論的組成を
制御することにより結晶成長層の品質を改善し、単分子
層の精度で成長膜を形成することにより、高品質の半導
体ダイオ−ニドを製造する方法を提供することを目的と
する。
[Objective of the Invention] The present invention eliminates the drawbacks of the prior art described above, improves the quality of the crystal growth layer by controlling the stoichiometric composition, and forms the growth film with the precision of a monomolecular layer. It is an object of the present invention to provide a method for manufacturing quality semiconductor diodes.

[発明の概要] このため、本発明は超高真空に排気した成長槽内で基板
を加熱すると共に光を照射し、その基板、にに成長させ
たい成分元素を含むガスを外部から導入することにより
、成長膜厚を分子層単位の精度で制御し、化学量論的組
成を満たす単結晶を成長させ、高品質の半導体ダイオー
ドが得られるようにしたことを特徴としている。
[Summary of the Invention] Therefore, the present invention involves heating a substrate in a growth tank evacuated to an ultra-high vacuum, irradiating it with light, and introducing a gas containing a component element to be grown onto the substrate from the outside. This method is characterized by controlling the growth film thickness with precision in molecular layer units, growing a single crystal that satisfies the stoichiometric composition, and making it possible to obtain high-quality semiconductor diodes.

[発明の実施例] 以下、本発明の実施例を半導体としてGaAsを用いた
場合を例にとり説明する。
[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described by taking as an example a case where GaAs is used as a semiconductor.

第1図は本発明の一実施例に係る半導体ダイオード製造
装置の構成図を示したもので、■は成長槽で材質はステ
ンレス等の金属、2はグー1−バルブ、3は成長槽1を
超高真空に排気するための排気装置、4はGaCQ3ま
たはTMG(トリメチルガリウム)等のGaを含むガス
を導入するノズル、5はASHsを導入するノズル、6
はTMZ(1−リメチル亜鉛)等のZnを含むガスを導
入するノズル、7はH2S等のSを含むガスを導入する
ノズル、8,9,10.11は前記ノズルを開閉するバ
ルブでガス源12(TMG、 GaC113等)、13
(AsH3)、Ill(DMZ)、15(H2S等)と
の間に設けられたもの、16は基板加熱用のヒーターで
石英ガラスに封入したW(タングステン)線で配線は省
略して図示しているもの、17は測温用の熱電対、】8
はGaAs基板、19は成長槽内の圧力を測定するため
の圧力計であり、20は基板照射用の光源、2jは光源
20用の窓である。ここで、光源20としては水銀ラン
プ、レーザ等を用いることができる。
FIG. 1 shows a configuration diagram of a semiconductor diode manufacturing apparatus according to an embodiment of the present invention, where ■ is a growth tank made of metal such as stainless steel, 2 is a goo 1-valve, and 3 is a growth tank 1. An exhaust device for evacuation to ultra-high vacuum, 4 a nozzle for introducing a gas containing Ga such as GaCQ3 or TMG (trimethyl gallium), 5 a nozzle for introducing ASHs, 6
1 is a nozzle for introducing a gas containing Zn such as TMZ (1-limethylzinc), 7 is a nozzle for introducing a gas containing S such as H2S, and 8, 9, and 10.11 are valves that open and close the nozzles, and are gas sources. 12 (TMG, GaC113, etc.), 13
(AsH3), Ill (DMZ), 15 (H2S, etc.), and 16 is a heater for heating the substrate, and is a W (tungsten) wire sealed in quartz glass, and the wiring is omitted in the illustration. 17 is a thermocouple for temperature measurement, ]8
is a GaAs substrate, 19 is a pressure gauge for measuring the pressure inside the growth tank, 20 is a light source for irradiating the substrate, and 2j is a window for the light source 20. Here, as the light source 20, a mercury lamp, a laser, etc. can be used.

上記構成で、基板18上にGaAsの結晶を成長させる
には、先ずゲートバルブ2を開けて超高真空排気装置3
により成長槽を10−7〜10  ” pascal(
以下、Paと略す)程度に排気する。次に、GaAs基
板18を例えば300〜800℃程度にヒーター1Gに
より加熱した後に、TNG]2を成長槽内の圧力が10
−1〜1O−7Paとなる範囲で0.5〜10秒間バル
ブ8を開けて導入する。次に、そのTMGを成長槽】内
より排気後、 Asll 313を成長491内の圧力
が10−” 〜10−”Paとなる範囲で2〜200秒
間バルブ5を開けて導入する。これにより、 GaAs
の結晶1分子層が成長できる。
With the above configuration, in order to grow a GaAs crystal on the substrate 18, first the gate valve 2 is opened and the ultra-high vacuum pump 3 is opened.
The growth tank was adjusted to 10-7 to 10” pascal (
Hereinafter, it is abbreviated as Pa). Next, after heating the GaAs substrate 18 to, for example, about 300 to 800° C. with the heater 1G, the TNG] 2 is heated to about 300° C. to 800° C.
-1 to 1O-7Pa by opening the valve 8 for 0.5 to 10 seconds. Next, after the TMG is evacuated from the growth tank, Asll 313 is introduced by opening the valve 5 for 2 to 200 seconds so that the pressure within the growth tank 491 is 10-'' to 10-'' Pa. As a result, GaAs
A single molecular layer of crystals can be grown.

一方、不純物の添加は、GaAsの成長と同じようにし
て、n型の場合は■族のGaと■族のZnを含むガスを
導入し、n型の場合は■族のAsと■族のSを含むガス
を導入することによって6達成することができ、それぞ
れp、 n型の不純物添加された1分子層が成長できる
On the other hand, impurity addition is done in the same way as for the growth of GaAs; in the case of n-type, a gas containing Ga of group II and Zn of group II is introduced, and in the case of n-type, a gas containing As of group II and As of group II is introduced. 6 can be achieved by introducing a gas containing S, and one molecular layer doped with p- and n-type impurities can be grown.

このとき、基板18の加熱と同時に光源20から紫外線
を照射するようにすれば、成長温度を400℃以下に低
下させることができ、不純物のオートドーピング乃至は
相互拡散を抑制することができるようになる。
At this time, by irradiating ultraviolet rays from the light source 20 at the same time as heating the substrate 18, the growth temperature can be lowered to 400°C or less, and autodoping or interdiffusion of impurities can be suppressed. Become.

この分子層エピタキシャル成長乃至は光分子層エピタキ
シャル成長は■−v族の成分元素を含むガスを交互に導
入し、化学反応によって成長が進むので化学量論的組成
を完全なものとすることができ、高品質の結晶を1分子
層ずつ成長させることができる。
In this molecular layer epitaxial growth or photomolecular layer epitaxial growth, gases containing group ■-V component elements are introduced alternately, and growth proceeds through chemical reactions, making it possible to perfect the stoichiometric composition. High-quality crystals can be grown one molecular layer at a time.

第2図は第1図の装置を用いた上記エピタキシャル成長
法によってダイオードを製造する場合の製造過程を示し
たもので、同図(a)に示す31はn層(ρ=IX10
−3Ω・〔)のGaAs基板である。この基板31上に
、同図(b)に示すように、上記エピタキシャル成長法
により不純物密度がlXl0”cm  ’で厚さ0.1
μmのn層を成長させる。更に、同図(c)に示すよう
に、n十基板31に対してオーミックコンタクトとなる
Au7GeまたはAu−Ge−Ni層の電極33と、同
図(d)に示すように0層32への電極34とを設けて
ダイオードを形成する。
FIG. 2 shows the manufacturing process when manufacturing a diode by the epitaxial growth method described above using the apparatus shown in FIG. 1, and 31 shown in FIG.
-3Ω·[) GaAs substrate. On this substrate 31, as shown in FIG.
Grow a μm n-layer. Furthermore, as shown in the figure (c), an electrode 33 of Au7Ge or Au-Ge-Ni layer which becomes an ohmic contact with the n0 substrate 31 and an electrode 33 of the Au7Ge or Au-Ge-Ni layer as shown in the figure (d), are connected to the zero layer 32. An electrode 34 is provided to form a diode.

この場合、電w134として0層32に対してオーミッ
クコンタクトとなるAu−、Ge等の合金を用いた場合
にはガンダイオードが形成できる。一方、 Au、 P
t。
In this case, a Gunn diode can be formed if an alloy such as Au- or Ge is used as the electrode w134 to form an ohmic contact with the 0 layer 32. On the other hand, Au, P
t.

W、 Cr、 Tj、N〕、Hf、ll等の周知のショ
ットキーバリアを形成する金属を用いた場合には、良好
なショク1−キーバリアダイオードが形成できる。
When a well-known Schottky barrier forming metal such as W, Cr, Tj, N], Hf, 11 is used, a good Schottky barrier diode can be formed.

第3図は他のダイオードの製造過程を示したもので、第
2図の場合と同様、第1図の装置を用いてGaAs基板
31上に0層35をエピタキシャル成長させ、上下面部
に電極33.34を形成してダイオードを製造する。こ
のとき、0層35を基板31側から表面にかけて不純物
密度分布が高くなるようにエピタキシャル成長させるこ
とにより、可変容量ダイオードいわゆるバラクタダイオ
ードが製造できる。この場合、不純物密度分布を適宜調
整することによって、階段接合、傾斜接合、超階段接合
等の構造が容易に実現できる。また、成長温度は基板に
光を照射することによって350℃とすることができる
ので、不純物の相互拡散、オートドーピング等がなく理
想的な不純物密度分布を得ることができる。
FIG. 3 shows the manufacturing process of another diode. As in the case of FIG. 2, an O layer 35 is epitaxially grown on a GaAs substrate 31 using the apparatus shown in FIG. 1, and electrodes 33 are formed on the upper and lower surfaces. 34 to manufacture the diode. At this time, by epitaxially growing the 0 layer 35 so that the impurity density distribution increases from the substrate 31 side to the surface, a variable capacitance diode, so-called varactor diode, can be manufactured. In this case, by appropriately adjusting the impurity density distribution, structures such as stepped junctions, inclined junctions, and super-stepped junctions can be easily realized. Further, since the growth temperature can be set to 350° C. by irradiating the substrate with light, an ideal impurity density distribution can be obtained without interdiffusion of impurities, autodoping, etc.

尚1以上の実施例において、基板上に成長させ、るエピ
タキシャル成長層はp形であってもよいことは言う迄も
ない。
It goes without saying that in one or more embodiments, the epitaxial layer grown on the substrate may be p-type.

第4図は更に本発明の別の実施例で、p−n接合ダイオ
ードの製造過程を示したものである。第2図の場合と同
様、第1図の装置を用いてGaAs基板31上に0層3
2を形成したのち(第4図(a) 、 (b))、その
上にP”(p=3〜6X10−3Ω・cm)GaAs層
36を形成する(第4図(C))。然る後、n+層31
へはAu −GeあるいはAu −Ge −Niをオー
ミックコンタクトし。
FIG. 4 is another embodiment of the present invention, showing the manufacturing process of a pn junction diode. As in the case of FIG. 2, the 0 layer 3 is formed on the GaAs substrate 31 using the apparatus of FIG.
After forming 2 (FIGS. 4(a) and 4(b)), a P'' (p=3 to 6×10 −3 Ω·cm) GaAs layer 36 is formed thereon (FIG. 4(C)). After that, the n+ layer 31
Make ohmic contact with Au-Ge or Au-Ge-Ni.

電極33を形成する(第4図(d))。一方、p中層3
6へはAu−Zn、Ag−Zn、In −Zn等をオー
ミックコンタクトすることにより、電極36を形成する
(第4図(e))。これにより、p−n接合ダイオード
が製造できる。
An electrode 33 is formed (FIG. 4(d)). On the other hand, p middle layer 3
6, an electrode 36 is formed by making ohmic contact with Au--Zn, Ag--Zn, In--Zn, etc. (FIG. 4(e)). Thereby, a pn junction diode can be manufactured.

第5図は更に本発明の別の実施例で、p +  n +
−n−−n+溝構造有するトンネル注入型の走行時間負
性抵抗ダイオード(タンネットダイオード)の製造過程
を示したものである。第2図の場合と同様、第1図の装
置を用いて、GaAs基板31上にn層Cp =1−2
xlO−3Ω−cm )GaAs層40を0.1−0.
2μm形成したのち(第5図(a) 、 (b))、そ
の上に走行領域となるn(不純物密度1014−5X 
1.0” cm ”−’程度)GaAs層42を形成す
る(第5図(C))。走行領域の厚さWdは、発振周波
数をf、キャリアの飽和速Vs 度をVsとした場合にはWd =□で与えられる。
FIG. 5 shows yet another embodiment of the present invention, in which p + n +
-n--The manufacturing process of a tunnel injection type transit time negative resistance diode (tannet diode) having a -n+ groove structure is shown. As in the case of FIG. 2, using the apparatus of FIG. 1, an n-layer Cp=1-2 is formed on the GaAs substrate 31.
xlO-3Ω-cm) GaAs layer 40 is 0.1-0.
After forming a layer of 2 μm (FIGS. 5(a) and (b)), a layer of n (impurity density 1014-5×
A GaAs layer 42 (about 1.0"cm"-') is formed (FIG. 5(C)). The thickness Wd of the traveling region is given by Wd = □, where f is the oscillation frequency and Vs is the carrier saturation speed.

f Vs = ]、 X 1.07am/seeとしたとき
に、f=]、00G)IzでWdは0.75μmトナリ
、300GHz、500Gl(z、1000GHzでは
それぞれ0.25μm、O,1,5μm、750Aとな
る。
When f Vs = ], It becomes 750A.

次にトンネル注入となるn”(5X]、017〜102
’ rB−″)GaAs層42)p”(5x101”−
102’cm  ’ )GaAs層43を順次形成する
(第5図(d)、 (e))。
Next is tunnel injection n” (5X), 017 to 102
'rB-'') GaAs layer 42) p''(5x101''-
102'cm') GaAs layers 43 are sequentially formed (FIGS. 5(d) and 5(e)).

ここで、n中層42の厚さと不純物密度は、例えば5刈
0’ ” cm  ” 、 300〜500λあるいは
1.X10”cm  ’ 、 100〜300人とすれ
ば良い。p+層の不純物密度は]、X]、019cm−
’以」二、厚さは0.5μn1以下とすることが、放熱
のために望ましい。然る後、P”WI43へはAH−Z
n、Au−Zn、 ’In−Zn等をオーミックコンタ
クトし、その上にAuメッキ層を形成し電(受44を形
成する(第5図(f))。直列抵抗を減少させるために
n子基板を薄くして、全体の厚さを10μm程度以下に
する(第5図(g)。次に、04′層31へはAu−G
eあるいはAu−Ge−Niをオーミックコンタク1〜
し、その上にAuメッキ層を形成し、電極45を形成す
る(第5図(h))。
Here, the thickness and impurity density of the n-middle layer 42 are, for example, 5 cm, 300 to 500 λ, or 1. X10"cm', 100 to 300 people is sufficient. The impurity density of the p+ layer is], X], 019cm-
Second, it is desirable for the thickness to be 0.5 μn1 or less for heat dissipation. After that, AH-Z to P"WI43
n, Au-Zn, 'In-Zn, etc. are made into ohmic contact, and an Au plating layer is formed thereon to form an electrical receiver 44 (Fig. 5(f)). The substrate is made thin so that the total thickness is about 10 μm or less (Fig. 5 (g). Next, Au-G is applied to the 04' layer 31.
e or Au-Ge-Ni with ohmic contact 1~
Then, an Au plating layer is formed thereon to form an electrode 45 (FIG. 5(h)).

これにより、タンネットダイオードが形成できる。また
、なだれ注入によるインバットダイオードも同様にして
製造することができる。
This allows a tannet diode to be formed. In addition, in-vat diodes using avalanche injection can also be manufactured in a similar manner.

このように、分子層ないしは光分子層エピタキシャル成
長法により、大体400℃以下で良好なエピタキシャル
層が形成でき”るので、不純物密度分布の非常に急岐な
タンネットダイオードを形成することができる。
As described above, a good epitaxial layer can be formed at approximately 400° C. or lower by the molecular layer or photomolecular layer epitaxial growth method, so that a tannet diode with a very sharp impurity density distribution can be formed.

尚1以上の実施例においては、半導体材料としてGaA
sを用いた例について説明したが1本発明はこれに限ら
ず、Sl、Geのような元素半導体、InP。
In one or more embodiments, GaA is used as the semiconductor material.
Although an example using s has been described, the present invention is not limited to this, and elemental semiconductors such as Sl and Ge, and InP.

GaPのような化合物半導体あるいはIII −V族化
合物半導体、更にはII−Vl化合物半導体等を用い得
ることは勿論である。また、基板もn子基板に限らず、
p千生導体、半絶縁性のもの、あるいは。
It goes without saying that a compound semiconductor such as GaP, a III-V compound semiconductor, or even a II-Vl compound semiconductor can be used. In addition, the board is not limited to n-child board,
P-thousand conductors, semi-insulating ones, or.

真性半導体であっても良いことは言う迄もない。Needless to say, it may be an intrinsic semiconductor.

[発明の効果] 以ヒのように本発明によれば、半導体の結晶膜を分゛r
一層単位の精度で結晶性良く成長させることができ、ま
た、不純、物の添加も一層ごとに制御することができ、
非71(に急峻な不純物密度分布も得ることができるこ
とから、高品質な半導体ダイオードが製造できるように
なる。
[Effects of the Invention] As described below, according to the present invention, a crystalline film of a semiconductor can be separated.
It is possible to grow crystallinity with high accuracy on a layer-by-layer basis, and it is also possible to control the addition of impurities and substances on a layer-by-layer basis.
Since it is possible to obtain an impurity density distribution as steep as 71, high quality semiconductor diodes can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係る半導体ダイオードの製
造装置の栴成図、第2図〜第5図は第1図の装置により
製造されるダイオードの製造過程説明図で、第2図(a
)〜(d)はガンダイオードないしはショットキーバリ
アダイオードの製造過程説明図、第3図(a)〜(d)
はバラクタダイオードの製造過程説明図、第4図(a)
〜(e)はp−n接合ダイオードの製造過程説明図、第
5図(a)〜(11)はp +  n + −n−一〇
十構造のタンネットダイオードの製造過程説明図である
。 1・・ 金属、2・・・グー1−バルブ、3・・・排気
装量、4,5,6.7・・・ノズル、8,9,10.1
1・・・バルブ。 1.2,13,14.15・・・ ガス源、16・・・
 ヒーター、17  ・・熱電対、18・・・GaAs
基板、19・・・圧力計。 20・・・光源、21・・・窓。 代理人 弁理士  紋 1) 誠  、゛第7図 第2図   第3図 (a)                      
 (a)(b)                  
        (b)(C)           
            (C)(d)       
                (d)第4図 (a) (b) (c) (d) 第5図 に3)                      
    (f)lニ
FIG. 1 is a schematic diagram of a semiconductor diode manufacturing apparatus according to an embodiment of the present invention, FIGS. 2 to 5 are explanatory diagrams of the manufacturing process of a diode manufactured by the apparatus of FIG. 1, and FIG. (a
) to (d) are explanatory diagrams of the manufacturing process of Gunn diodes or Schottky barrier diodes, and Fig. 3 (a) to (d)
Figure 4 (a) is an explanatory diagram of the manufacturing process of a varactor diode.
- (e) are explanatory diagrams of the manufacturing process of a pn junction diode, and Figs. 5 (a) to (11) are explanatory diagrams of the manufacturing process of a tannet diode having a p + n + -n-100 structure. 1... Metal, 2... Goo 1-valve, 3... Exhaust capacity, 4, 5, 6.7... Nozzle, 8, 9, 10.1
1...Valve. 1.2, 13, 14.15... gas source, 16...
Heater, 17...Thermocouple, 18...GaAs
Board, 19...pressure gauge. 20...Light source, 21...Window. Agent Patent Attorney Crest 1) Makoto, Figure 7 Figure 2 Figure 3 (a)
(a)(b)
(b) (C)
(C) (d)
(d) Figure 4 (a) (b) (c) (d) 3) in Figure 5
(f)lni

Claims (8)

【特許請求の範囲】[Claims] (1)真空に排気する成長槽内に外部より結晶成分元素
を含むガスを導入し、基板上に半導体の結晶を成長させ
る方法において、前記成長槽内を超高真空に排気すると
共に、前記基板を加熱し、結晶成長させたい成分元素を
含むガスを所定量導入して1分子層ずつエピタキシャル
成長させることにより、所定膜厚の結晶層を形成し、半
導体ダイオードを製造することを特徴とする半導体ダイ
オードの製造方法。
(1) In a method of growing a semiconductor crystal on a substrate by introducing a gas containing a crystal component element from the outside into a growth tank that is evacuated to a vacuum, the growth tank is evacuated to an ultra-high vacuum, and the A semiconductor diode characterized in that a semiconductor diode is manufactured by heating a semiconductor diode, introducing a predetermined amount of gas containing a component element desired for crystal growth, and epitaxially growing one molecular layer at a time to form a crystal layer with a predetermined thickness. manufacturing method.
(2)特許請求の範囲第1項記載において、前記成長槽
内を10^−^7パスカル以下の圧力に排気すると共に
、前記基板を300〜800℃に加熱し、結晶成長させ
たい半導体の成分元素を含むガスを前記成長槽内の圧力
が10^−^1〜10^−^7パスカルになる範囲で0
.5〜200秒間前記基板上に導入する手法を用いて分
子層を成長させる半導体ダイオードの製造方法。
(2) In claim 1, the inside of the growth tank is evacuated to a pressure of 10^-^7 Pascal or less, and the substrate is heated to 300 to 800°C, and the components of the semiconductor whose crystals are to be grown are heated. The gas containing the element is heated to 0 within the pressure range of 10^-^1 to 10^-^7 Pascals in the growth tank.
.. A method for manufacturing a semiconductor diode, comprising growing a molecular layer using a method of introducing the substrate onto the substrate for 5 to 200 seconds.
(3)特許請求の範囲第1項記載において、前記基板に
光を照射しながらエピタキシャル成長させる半導体ダイ
オードの製造方法。
(3) A method for manufacturing a semiconductor diode according to claim 1, in which the substrate is epitaxially grown while being irradiated with light.
(4)特許請求の範囲第1項記載において、前記エピタ
キシャル成長層の一部の伝導型が基板と同一である半導
体ダイオードの製造方法。
(4) A method for manufacturing a semiconductor diode according to claim 1, wherein a part of the epitaxial growth layer has the same conductivity type as the substrate.
(5)特許請求の範囲第1項記載において、前記エピタ
キシャル成長層の一部の伝導型が基板と反対である半導
体ダイオードの製造方法。
(5) A method for manufacturing a semiconductor diode according to claim 1, wherein a part of the epitaxial growth layer has a conductivity type opposite to that of the substrate.
(6)特許請求の範囲第1項記載において、前記基板が
半絶縁性または真性半導体である半導体ダイオードの製
造方法。
(6) A method for manufacturing a semiconductor diode according to claim 1, wherein the substrate is a semi-insulating or intrinsic semiconductor.
(7)特許請求の範囲第1項記載において、前記エピタ
キシャル成長層の少なくとも一部は不純物密度分布が均
一である半導体ダイオードの製造方法。
(7) A method for manufacturing a semiconductor diode according to claim 1, wherein at least a portion of the epitaxial growth layer has a uniform impurity density distribution.
(8)特許請求の範囲第1項記載において、前記エピタ
キシャル成長層の少なくとも一部は不純物密度分布が均
一でない半導体ダイオードの製造方法。
(8) A method for manufacturing a semiconductor diode according to claim 1, wherein at least a portion of the epitaxially grown layer has an uneven impurity density distribution.
JP59153970A 1984-07-26 1984-07-26 Method for manufacturing GaAs semiconductor diode Expired - Lifetime JPH0713966B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59153970A JPH0713966B2 (en) 1984-07-26 1984-07-26 Method for manufacturing GaAs semiconductor diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59153970A JPH0713966B2 (en) 1984-07-26 1984-07-26 Method for manufacturing GaAs semiconductor diode

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6240803A Division JP2654608B2 (en) 1994-09-09 1994-09-09 Method for manufacturing GaAs semiconductor diode

Publications (2)

Publication Number Publication Date
JPS6134982A true JPS6134982A (en) 1986-02-19
JPH0713966B2 JPH0713966B2 (en) 1995-02-15

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ID=15574053

Family Applications (1)

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455239A (en) * 1987-08-26 1989-03-02 Shinetsu Chemical Co Manufacture of conductive silicone rubber formed article
JPH04147847A (en) * 1990-10-11 1992-05-21 Shin Etsu Chem Co Ltd Silicone rubber laminated product and its manufacture
JPH07326623A (en) * 1994-09-09 1995-12-12 Res Dev Corp Of Japan Manufacture of gaas semiconductor diode

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5898917A (en) * 1981-12-09 1983-06-13 Seiko Epson Corp Atomic layer epitaxial device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5898917A (en) * 1981-12-09 1983-06-13 Seiko Epson Corp Atomic layer epitaxial device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455239A (en) * 1987-08-26 1989-03-02 Shinetsu Chemical Co Manufacture of conductive silicone rubber formed article
JPH04147847A (en) * 1990-10-11 1992-05-21 Shin Etsu Chem Co Ltd Silicone rubber laminated product and its manufacture
US5256480A (en) * 1990-10-11 1993-10-26 Shin-Etsu Chemical Co., Ltd. Silicone rubber laminate and method of making
JPH07326623A (en) * 1994-09-09 1995-12-12 Res Dev Corp Of Japan Manufacture of gaas semiconductor diode

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