JPS6134660A - Priority selection controlling system - Google Patents

Abstract

PURPOSE:To execute in a short time a priority selection of an interruption processing request from an I/O, and also to reduce an interruption processing signal applied to a processing circuit by executing the priority selection of an interruption processing between adaptors of plural I/Os. CONSTITUTION:Adaptors #0-#3 have a circuit for controlling an I/O, and a priority order of an interruption, etc. is determined by this circuit. An interrupting signal is stored in an interruption register IR01, and its output is provided to an OR gate OR01 and OR is executed. This result is outputted to a common part 1 and an AND gate A01, and the common part 1 outputs an interruption receiving signal to the adaptors #0-#3. As a result, the adaptors #0-#3 execute a priority selection of an interruption processing by its signal and reply automatically in response to an interruption reception of a common processing circuit successively from an interruption of a high level. In this way, the priority selection of the interruption processing request from the I/O can be executed in a short time, and an interruption processing signal applied to the processing circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a control system having an interrupt signal, and more particularly to a priority selection control method in which a device that generates an interrupt signal automatically operates over a device with a higher priority. .

(2) Background of the Technology In computer input/output devices, interrupt processing is generally performed frequently in order to perform parallel processing and the like. For example, when outputting a command to print one line to an output device, one
Simultaneously with the completion of printing a line, an interrupt is applied to the processing device, and the processing device uses the interrupt to output a command for printing the next line to the output device again. Further, even when a processing request to the processing device is generated due to some abnormality, the processing device executes the processing by this interruption.

The interrupt signal mentioned above is not necessarily output from a single input/output device, but when multiple input/output devices are connected, interrupt signals may be applied to the processing device from multiple input/output devices at the same time. be. In such a case, the processing device executes processing for the interrupt according to preset priorities.

Furthermore, even within the same input/output device, there may be multiple processes for the interrupt, and these processes also require priority. In such a case, the processing device for the interrupt executes the interrupt according to the preset priority order as described above.

(3) Prior Art and Problems Conventionally, in a system in which a large number of interrupts as described above occur, interrupt processing has been performed in the following priority order. The first interrupt processing involves setting up a common circuit for priority selection processing for a plurality of interrupts, determining priorities in the common circuit, and selectively executing the processing in a processing circuit.

For the second interrupt processing, an interface circuit for priority selection is provided on the input/output device side that generates the interrupt.

This interface circuit compares the priorities among the input/output devices, selects and executes the input/output device with priority.

The above-mentioned first interrupt processing requires a dedicated signal line for each input/output device to send the necessary information as a signal to the common circuit, and a circuit to determine the priority of the signals. I had a growing problem. The second interrupt processing has a problem in that it takes time to determine the priorities because the priorities of the input/output devices are compared on a time-sharing basis.

(4) Purpose of the Invention The present invention is intended to solve the above-mentioned problems, and its purpose is to prioritize interrupt processing requests from input/output devices in a short time, and furthermore, to reduce interrupt processing signals applied to processing circuits. The object of the present invention is to provide a priority selection control method with fewer problems.

(5) Structure of the Invention The present invention is characterized by a control system in which a plurality of adapters each controlled by a microprocessor are connected to a processing circuit.

The adapters are each connected to a common bus that controls the priorities of interrupt signals applied to the processing circuit, and all adapters process the signals applied from the adapters to the common bus in the same way as a program for determining the priority. Each table has a table, interrupts to the processing circuit are made in common, and a corresponding high-level adapter operates based on the priority determination -i-Fulni base for interrupt responses of the processing circuit. The priority selection control method is characterized by:

(6) Examples of the invention The present invention will be described in detail below using two drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Note that all lines made up of multiple lines are represented by normal lines.

Adapters #0 to #3 include, for example, a circuit that controls input/output devices, and this circuit determines the priority order of interrupts and the like. Adapters #0 to #3 each have a circuit according to an embodiment of the present invention. Note that, as will be described later, some connections differ depending on the priority. In the following, the operation will first be explained using adapter #0.

An interrupt signal applied from a circuit not shown is stored in the interrupt register IRo. Adapter #0 has four levels of interrupt requests, and register IRa is a 4-bit register. The output is added to ORQI + If
! Reasonable. Orage part ○Ro+ is a circuit for setting the output to 1'' when at least a level interrupt occurs (1'') among these four level interrupts. Then, the output is applied to the common section 1 and the AND gate Ao+. (OR gate ORθ1 is the oven collector output, and all outputs of adapters #0 to #3 are common to common part 1.
join. ) By this input, the common unit 1 detects that an interrupt has occurred from any adapter. However, even if the common unit 1 detects the occurrence of an interrupt, it cannot detect which adapter the interrupt is from based on its input signal. Which adapter is the interrupt from?

Further, the common unit 1 outputs an interrupt acceptance signal to all adapters #0 to #3 to detect what kind of interrupt it is. Each adapter #0 to #3 outputs data for interrupt processing to the common unit 1 according to the signal, and the adapter with the higher level outputs first. In addition, the highest level is 0.0 with an adapter. Adapter #1.
Adapter #2. Adapter #3, which generated one interrupt request the highest, responds to the aforementioned signal.

Then, the interrupt processing is performed, and thereafter, interrupt processing is performed for successively lower levels. Regarding the response to the above-mentioned interrupt acceptance signal, each adapter must detect whether or not it is at the highest level among the adapters that request two interrupt processing, that is, generate an interrupt. Interrupt acceptance cannot respond to signals.

Each adapter #0 to ## shown in Figure 1 detects this.
This is the third circuit.

In the following, the case where an interrupt occurs from adapter #0 will be explained first. When interrupt priority selection processing (table rewriting operation) is possible, the center reset flip-flop RO
Since 2 is reset, its output "0" is inverted by the inverter 1 I, and 1" is the AND gate A.
Adds to the input of o+. By this, and gate Ao+
is turned on. A signal of "1" applied from the OR gate ORθ1 sets the set/reset flip-flop Ro+ via the AND gate Ao+. By setting the center reset flip-flop Ro+, the output becomes "1" and outputs to other adapters that an interrupt has occurred.

On the other hand, all the inputs of the OR gate 0RO2 of adapter #0 are grounded (“0” is input), so the output is also “0”, and 1” is sent to the ant game 1-1 through imper ro2.
It is added to the first input of An2. Furthermore, since the center reset flip-flop RO3 has been reset at this time, it outputs "0". And Impark Io3~I
It becomes "1" through o5 and is applied to the second input of AND gate AO2. Antogame)・Since "1" is added to the first and second inputs of An2 as mentioned above, the third input
The signal (“1” at this time) of the center reset flip-flop Ro+ that is applied to the input of the AND gate A
Set-reset flip-prop R[13 via O2
and sends the set-reset flip-flop RO3. The output of this center reset flip-flop Ro3 becomes "1" and the Nantes gate NAo
Turn on I.

On the other hand, when an interrupt request is generated from the adapter, its level and the processor selection processing start address (table creation start address) corresponding to the adapter are stored in register IRo2.

Since NAθ1 (Nando Game) is turned on by the above-described operation, the inverted value of the address is output to the address bus BA. At this time, since the output of the aforementioned set-reset flip-flop Ro3, ie, 1'' is applied to the inverter Io7, the AND gate AO3 to which the output is applied outputs 0''.

and gate ka 4. An fi, or gate OR
3. Inverter Io [I constitutes a circuit that selects the output of register TRo 2 and the output 6 of inverter Ill and 6. When the output of AND gate AO3 is “0”,
“1” is passed through inverter Ioa to AND gate AO4
The register IRo2 is turned on and the output of the register IRo2 is output to the processor circuit Mo+. Also, and gate AO3
When the output of is "1", 1" is added to the AND gate Aoa.

AND gate AoI is turned on, and address bus BA
The value obtained by inverting the contents of (at inverter Io6) is output to the processor circuit Mo+. Note that this inversion is because the address bus BA is used to transmit a negative logic signal, and if it is logical, an AND gate may be used, and in this case, the inverter Io6 is not necessary.

In the above operation, since An3 is outputting "O", the register IR is in the processor circuit Mo+.
o The output of 2 is added.

Since 1'' is added to the inverter I[13 as described above, in this state, O'' is output as the address switching signal As. When the address switching signal line As is 0'', 9. For example, in adapter #3, inverter I34 is set to 0.
is added, so 1'' is input to one side of the AND gate.

Also, when an interrupt request occurs from the upper level, the OR circuit 0R
Since the output of the AND gate A32 becomes "1", 0" is added to the AND gate A32 via the inverter 132, and even if two interrupt requests occur, the output of the AND gate becomes 0". Therefore, the center reset flip-flop R33 is
Therefore, this output also becomes “θ”, and the inverter 13? "1" is added to the other input of AND gate A33 via.

Therefore, all the inputs of the controller A33 are 1" and its output is also ul", so the AND gate A35 is turned on and the data on the address bus is applied to the processor circuit M31. The same goes for other adapters, all address bus AB.
Outputs the above value to the processor circuit.

As is clear from the above operation, when an interrupt request is generated from the highest level adapter, the selection processing start address is added to the processor circuit for all lower adapters, and a table representing the order of processing requests is created.

Further, if an interrupt request is generated from an intermediate adapter, and no interrupt request is generated from a higher level than that adapter, the selection processing start address is added to all the adapters.

Although adapter #0 and adapter #3 are not shown in FIG. 1, the other adapters have similar circuits and are connected in the same way. Note that the processing line RQ o ” RQ 3
is the OR gate ORn 2 of the corresponding adapter.
(n is 0 to 3) (only processing lines RQo to RQ 3 of the upper level adapter are connected),
Only this point differs depending on the level of each adapter. As a result, the selection processing start address outputted from each adapter is inputted sequentially from the higher level adapter, and the processors Mo+ to M31 included in each adapter start processing from that address.

Since the processors M o + to M31 all have the same program, adding the start address results in exactly the same operation, and the tables created as a result are also the same. In addition, Nantes Gate NAo1~NA
31. Inverter TO3-133. Or Gate ORo
+ ~OR31 is an open collector output, and Nant gate NAQI ~NA31. And Gate Ao4
~Ao5. OR gate 0R03~0R33 inverter I
O6-136 are circuits with the number of bits representing the start address. Note that the set/reset flips Ra +, Ro2+ Ro 3 of adapter #0 are reset when the processor Mo+ finishes creating the table.

Figure 2 is a chart of interrupt requests in the case of 8 adapters)
(Figure fa1) and the contents of the created table (Figure (b)). First, level 2 is generated from adapter #2, followed by level 4 from adapter #1. Adapter #5
level 2. Level 3 of adapter #6 is occurring sequentially. A processing request is applied to common section 1 at the same time as the level 2 interrupt request generated by adapter #3, but a response to the processing request is made at point 2. When an interrupt acceptance signal is output from the common section, each adapter refers to the table, and the adapter with the highest level responds. In the case of FIG. 2, adapter #1 responds first. Then, that processing is performed, and the processing is sequentially performed on lower-level adapters.

As mentioned above, the reason why it is possible to respond to an interrupt acceptance signal sequentially from the high-level adapters is because all adapters have the same table, which determines whether or not each adapter can respond to the interrupt acceptance signal. This is because the determination is made by referring to .

Note that in FIG. 2+a), the interrupt requests to each adapter are not made at the same time, but when they are made at the same time, they are registered in the table in order from the higher level.

Furthermore, the priority order of one interrupt processing is not based on the adapter number and its internal level, for example, 4 levels, but it is also possible to set a separate priority order when referring to a table.

(7) Effects of the Invention As described above, the present invention prioritizes interrupt processing among the adapters of multiple input/output devices, and automatically responds to interrupt acceptance of the common processing circuit in order from higher level interrupts. According to the present invention, it is possible to obtain a priority selection method that performs priority selection in a short time without requiring a common processing circuit to perform priority selection of interrupt processing requests. Furthermore, since only one interrupt signal line is added to the common processing circuit, a comparison circuit or the like is not required, and a priority selection system with a simple common processing circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 ta+ is a chart of an interrupt request, and FIG. 2(b) is a diagram of the contents of a table created by an interrupt. IRo1~lR311IRo2~lR32...Regisfu, Ro1~R3II Ro2~R32,
RO3~R33...Set reset flip prop, Ao I~A31゜Ao2ゞA32
．． A exit 3ゞA33. AO4ゞA34. 805~A35・
...and gate. 0R01~oR3110R02~0R32....ORGATE+To+~I:+1. [02-13
2. IO3~132. TO4-I34゜roaNI:+
+++ ro6~136. To7~137.108~
T311...Inverter. Mo+~M3+... Processor circuit. BA--address bus, RQ o-RQ
3... Processing line.

Claims (1)

[Claims] In a control system in which a plurality of adapters each controlled by a microprocessor are connected to a processing circuit, the adapters are each connected to a common bus that controls the priority of interrupt signals applied to the processing circuit, and the adapters are connected to a common bus that controls the priority of interrupt signals applied to the processing circuit. All adapters have the same program and the same priority determination table for processing signals applied by the adapter, interrupts to the processing circuits are common, and interrupt responses of the processing circuits are processed according to the priority order. A priority selection control method characterized in that a corresponding high-level adapter operates based on a ranking determination table.