JPS613436A - Manufacture of package for mounting semiconductor element - Google Patents

Manufacture of package for mounting semiconductor element

Info

Publication number
JPS613436A
JPS613436A JP59124656A JP12465684A JPS613436A JP S613436 A JPS613436 A JP S613436A JP 59124656 A JP59124656 A JP 59124656A JP 12465684 A JP12465684 A JP 12465684A JP S613436 A JPS613436 A JP S613436A
Authority
JP
Japan
Prior art keywords
melting point
paste
point glass
low
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59124656A
Other languages
Japanese (ja)
Inventor
Takashi Kinoshita
高志 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59124656A priority Critical patent/JPS613436A/en
Publication of JPS613436A publication Critical patent/JPS613436A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H01L2224/83047—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable the formation of a good glass-mount by a method wherein a paste of low-melting-point glass is printed or dripped to the die-attach surface in a cavity of a ceramic substrate and then pressed with a plane sunstrate which does not react with the paste. CONSTITUTION:A layer 8' of paste of low-melting-poing glass or poor flatness formed by printing or dripping is pressed under a required amount of pressure to the direction of an arrow from above with an Si plate 11 which does not react with the low melting poing glass. Thereafter, the die-attach surface is formed by drying and sintering said layer 8'. This manner produces an excellent flatness of the die-attach surface and allows no inclination of a pellet in mounting and no levitation of part of the pellet. Even by a mounting system with a belt furnace, an excellent mount can be formed without pellet slides.

Description

【発明の詳細な説明】 本発明は半導体素子搭載用パッケージの製造方法に関し
、特にダイアタッチ面が低融点ガラス層よ〕なる半導体
素子搭載用パッケージの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a package for mounting a semiconductor element, and more particularly to a method of manufacturing a package for mounting a semiconductor element whose die attach surface is a low melting point glass layer.

半導体素子（以下ベレットと言う）１ベレ、ト搭載用パ
、ケージのセラミック基体に搭載するには、　Ａｕ−８
ｉ共晶系の合金が多く用いられていたが、近年は低融点
ガラスによシペレ、ト金セラミック基体に融着する方法
（以下ガラスマウントと言５）も多く用いられてきた。To mount a semiconductor element (hereinafter referred to as a pellet) on the ceramic substrate of the cage, use Au-8.
Although eutectic alloys have been widely used, in recent years, a method in which low-melting glass is fused to a gold ceramic substrate (hereinafter referred to as glass mount 5) has also been widely used.

それに伴ない、セラミック基体のダイアタッチ面の材質
は金属膜層に変わシ、低融点ガラス層が多く用いられる
ようになった。Along with this, the material of the die attach surface of the ceramic substrate has changed to a metal film layer, and a low melting point glass layer has come to be used more often.

まず始めに、一般的なガラスマウント技術を第１図に基
づき説明する。つまり、セラミック基体１のキャビティ
２内のダイアタッチ面３の上にあらかじめ低融点ガラス
層４を形成しておき、ベレット５を接着するのである。First, a general glass mounting technique will be explained based on FIG. That is, the low melting point glass layer 4 is formed in advance on the die attach surface 3 in the cavity 2 of the ceramic substrate 1, and the pellet 5 is bonded thereto.

実際には、マウンターのヒータープロ、りでセラミック
基体１を加熱し、低融点ガラス層４を溶融し、ペレット
５を矢印の方向に所定量加圧し、接着するのである。量
産向きの方法としては、セラミック基体１の低融点ガラ
ス層４上の所定位置にあらかじめベレット５をセ、トシ
ておき、その後ベルト炉等の加熱体を通過させ、前記低
融点ガラス層４を溶融し、ペレット５をセラミック基体
ｌに接着するのである。In practice, the ceramic substrate 1 is heated by the heater heater of the mounter, the low melting point glass layer 4 is melted, and the pellets 5 are pressed by a predetermined amount in the direction of the arrow to be bonded. As a method suitable for mass production, a pellet 5 is placed in advance at a predetermined position on the low melting point glass layer 4 of the ceramic substrate 1, and then passed through a heating element such as a belt furnace to melt the low melting point glass layer 4. Then, the pellet 5 is bonded to the ceramic substrate l.

さて、前記したガラスマウント技術において使用されて
いる。ガラスマウント用パッケージの従来よりの製造方
法を第２図（ａ）、　（ｂ）に示す。第２図（ａ）は低
融点ガラス印刷法によるガラスマウント用パッケージの
製造方法であシ、また同図（ｂ）は低融点ガラス滴下法
による製造方法である。つ′１り。Now, it is used in the glass mount technique described above. A conventional manufacturing method for a glass mount package is shown in FIGS. 2(a) and 2(b). FIG. 2(a) shows a method for manufacturing a glass mount package using a low melting point glass printing method, and FIG. 2(b) shows a manufacturing method using a low melting point glass dropping method. One.

第２図（ａ）においては、キャビティ２を有するセラミ
ック基体ｌの上面に、マスク６１に備えた印刷用メツシ
ュアを所定の位置にセットし、ペースト状低融点ガラδ
８を供給しつつ、印刷用ノ・ケ９を矢印Ａの方向に所定
量加圧した状態で、矢印Ｂの方向に移動させること罠よ
って、ダイアタッチ面３の上圧ペースト状低融点ガラス
８を印刷するのである。また、第２図（ｂ）においては
、キャビティ２の上方よ）滴下用注射針１０でペースト
状低融点ガラス８をダイアタッチ面３の上に滴下するの
である。第２図（ａ）、　（ｂ）の両方の場合共、この
後、ベルト炉等の加熱体を通過させ、ペースト状低融点
ガラス８を乾燥ならびに焼結させている。In FIG. 2(a), a printing mesh provided in a mask 61 is set at a predetermined position on the upper surface of a ceramic substrate l having a cavity 2, and a pasty low melting point glass δ
8, pressurize the printing plate 9 by a predetermined amount in the direction of arrow A, and move it in the direction of arrow B. Accordingly, press the paste-like low melting point glass 8 on the die attach surface 3. is printed. In addition, in FIG. 2(b), the paste-like low melting point glass 8 is dropped onto the die attach surface 3 using the dropping injection needle 10 (from above the cavity 2). In both cases of FIGS. 2(a) and 2(b), the paste-like low melting point glass 8 is then dried and sintered by passing through a heating body such as a belt furnace.

しかしながら、従来の製造方法であると、以下に示す様
な欠点金有している。それ拡セラミック基体のダイアタ
ッチ面上の低融点ガラス層の平面度が悪＜、ｔた。厚み
の均一さに欠けてｂる。それゆえ、マウンターによる半
導体ペレット接着時に、ペレットの一部が浮いてしまっ
たり、ペレットが傾いてしまったシすることが多く見ら
れた。However, conventional manufacturing methods have the following drawbacks. The flatness of the low melting point glass layer on the die attach surface of the expanded ceramic substrate was poor. The thickness lacks uniformity. Therefore, when attaching semiconductor pellets using a mounter, it was often seen that part of the pellets floated or the pellets were tilted.

また、ベルト炉での半導体ペレット接着時には、ペレッ
トズレが生じることが多く見られた。Furthermore, when bonding semiconductor pellets in a belt furnace, pellet displacement often occurred.

この様な不十分なマウント状態であると１次工程のボン
ディングにおいて歩留が大きく低下したり、製品になっ
た後、ペレットクラ、りの要因になる等１重大な欠点を
有している。Such an insufficient mounting condition has one serious drawback, such as greatly reducing the yield in the bonding process in the first step and causing pellet cracking and corrosion after the product is manufactured.

本発明の目的は従来方法の欠点を解消すべく、良好なガ
ラスマウントが可能となる。ガラスマウント用パッケー
ジの製造方法を提供することにある。An object of the present invention is to overcome the drawbacks of conventional methods, and to make it possible to mount a glass with good quality. An object of the present invention is to provide a method for manufacturing a package for glass mounting.

本発明の特徴は、キャビティを有するセラミ。The feature of the present invention is ceramic having a cavity.

り基体の該キャビティ内ダイアタッチ面にペースト状低
融点ガラスを印刷または滴下する工程と。a step of printing or dropping paste-like low melting point glass on the die attachment surface in the cavity of the substrate;

前記ダイアタッチ面上のペースト状低融点ガラス層を低
融点ガラスと反応性の無い平面基板たとえばシリコン板
等で面押しする工程表しかる後に−前記ペースト状低融
点ガラス層を乾燥ならびに焼結する工程とを有する半導
体素子搭載用パッケージの製造方法にある。Step of pressing the paste-like low-melting point glass layer on the die attach surface with a flat substrate, such as a silicon plate, which has no reactivity with the low-melting-point glass; After that, a step of drying and sintering the paste-like low-melting point glass layer. A method of manufacturing a package for mounting a semiconductor element, comprising:

次に本発明のパッケージの製造方法の実施例を説明する
。Next, an embodiment of the package manufacturing method of the present invention will be described.

第３図（ａ）において印刷法または滴下法によって形成
された平面度が悪いペースト状低融点ガラス層８′を、
第３図［ｂ）に示す様に低融点ガラスと反応性の無いシ
リコン板１１で上方よ）矢印の方向に所定量の加圧力で
面押しする。この後、ペースト状低融点ガラス層８′を
乾燥、焼結し、平面度の良好なダイアタッチ面を形成す
る方法である。In FIG. 3(a), a paste-like low melting point glass layer 8' with poor flatness formed by a printing method or a dropping method is
As shown in FIG. 3(b), a silicon plate 11 that is not reactive with low melting point glass is pressed upward in the direction of the arrow with a predetermined amount of pressure. Thereafter, the paste-like low melting point glass layer 8' is dried and sintered to form a die attach surface with good flatness.

なお、印刷法による低融点ガラス層形成の場合、ペース
ト状低融点ガラス印刷→面押し→ペースト状低融点ガラ
ス乾燥を複数回くり返した後にペースト状低融点ガラス
を焼結させることによシ、ダイアタ、チ面上に所望の厚
みを有する低融点ガラス層を形成させることができる。In addition, in the case of forming a low melting point glass layer by the printing method, the process of printing paste low melting point glass → surface pressing → pasty low melting point glass drying is repeated several times, and then sintering the paste low melting point glass. , a low melting point glass layer having a desired thickness can be formed on the top surface.

本発明に基づくガラスマウント用パッケージの製造方法
であると、ダイアタッチ面の平面度がすぐれておフ、マ
ウント時にペレットが傾いたフ。The method for manufacturing a package for glass mounting according to the present invention has excellent flatness of the die attach surface, and prevents the pellet from being tilted during mounting.

ペレットの一部が浮いたちすることがない、また、ベル
ト炉を用いたマウント方式であってもペレ。Part of the pellets will not float, and even if the mounting method uses a belt furnace, the pellets will not float.

トズレが生じることがなく、良好なマウントが成される
という利点を有している。It has the advantage that no displacement occurs and a good mount is achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は一般的なガラスマウント技術を説明する断面図
である。第２図（ａ）、　（ｂ）はガラスマウント用パ
ッケージの従来製造方法金示す断面図である。 第３図（ａ）、　（ｂ）は本発明に基づくガラスマウン
ト用パッケージの製造方法の一実施例金示す断面図であ
る。 図において、１・・・・・・セラミック基体、２・・・
・・・キャピテイ、３・・・・・・ダイアタッチ面、４
−・・・・・低融点ガラス層、５・−・・・・半導体ベ
レット、６・・・・・・マスク、７・・・・・・メツシ
ー、８・・・・・・ペースト状低融点ガラス、８′・・
・・・−ペースト状低融点ガラス層、９・・・・・・印
刷用ハケ、１０・・・・・・滴下用注射針、１１・・・
・・・面押し用シリコン板。 第１図 第２図 （ａ−） （ｂ） 第３図FIG. 1 is a cross-sectional view illustrating a general glass mounting technique. FIGS. 2(a) and 2(b) are cross-sectional views showing a conventional manufacturing method for a glass mount package. FIGS. 3(a) and 3(b) are cross-sectional views showing one embodiment of the method for manufacturing a glass mount package according to the present invention. In the figure, 1...ceramic substrate, 2...
... Capity, 3 ... Die attach surface, 4
-...Low melting point glass layer, 5...Semiconductor pellet, 6...Mask, 7...Metsy, 8...Paste low melting point Glass, 8'...
...- Paste-like low melting point glass layer, 9... Printing brush, 10... Injection needle, 11...
...Silicone plate for surface pressing. Figure 1 Figure 2 (a-) (b) Figure 3

Claims (1)

【特許請求の範囲】[Claims] キャビティを有するセラミック基体の該キャビティ内ダ
イアタッチ面にペースト状低融点ガラスを印刷または滴
下する工程と、前記ダイアタッチ面上のペースト状低融
点ガラス層を低融点ガラスと反応性の無い平面基板で面
押しする工程と、しかる後に前記ペースト状低融点ガラ
ス層を乾燥ならびに焼結する工程とを有することを特徴
とする半導体素子搭載用パッケージの製造方法。A step of printing or dropping paste-like low-melting point glass on the die attach surface inside the cavity of a ceramic substrate having a cavity, and forming a paste-like low-melting point glass layer on the die attach surface with a flat substrate that has no reactivity with the low-melting point glass. A method for manufacturing a package for mounting a semiconductor element, comprising the steps of surface pressing, and then drying and sintering the paste-like low melting point glass layer.
JP59124656A 1984-06-18 1984-06-18 Manufacture of package for mounting semiconductor element Pending JPS613436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59124656A JPS613436A (en) 1984-06-18 1984-06-18 Manufacture of package for mounting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59124656A JPS613436A (en) 1984-06-18 1984-06-18 Manufacture of package for mounting semiconductor element

Publications (1)

Publication Number Publication Date
JPS613436A true JPS613436A (en) 1986-01-09

Family

ID=14890799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59124656A Pending JPS613436A (en) 1984-06-18 1984-06-18 Manufacture of package for mounting semiconductor element

Country Status (1)

Country Link
JP (1) JPS613436A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210650A (en) * 1986-03-11 1987-09-16 Nec Corp Package for semiconductor device
JPS6476730A (en) * 1987-09-18 1989-03-22 Nec Corp Mounting structure of semiconductor element
US5060179A (en) * 1989-11-14 1991-10-22 Roland Corporation Mathematical function-generating device for electronic musical instruments
JP2007235791A (en) * 2006-03-03 2007-09-13 Epson Toyocom Corp Piezoelectric device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210650A (en) * 1986-03-11 1987-09-16 Nec Corp Package for semiconductor device
JPS6476730A (en) * 1987-09-18 1989-03-22 Nec Corp Mounting structure of semiconductor element
US5060179A (en) * 1989-11-14 1991-10-22 Roland Corporation Mathematical function-generating device for electronic musical instruments
JP2007235791A (en) * 2006-03-03 2007-09-13 Epson Toyocom Corp Piezoelectric device

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