JPS6134289B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency band division filter, and has a configuration in which delay means driven by a clock signal are connected in combination to vary the frequency of the clock signal. A frequency band division filter that can obtain signals in multiple frequency bands that have frequency amplitude characteristics and frequency delay characteristics, that is, waveform transmission and sharp cutoff characteristics, and that can easily vary the crossover frequency of signals in a predetermined frequency band. The purpose is to provide.

The present applicant previously proposed in Japanese Patent Application No. 52-107196 ``Frequency Band Dividing Filter'' a frequency band dividing filter that has good cutoff characteristics as a dividing filter, and good amplitude and delay characteristics after synthesis. This dividing filter has a delay line filter having a predetermined frequency band and a delay circuit connected in parallel to an input terminal, and further includes means for calculating and extracting the output of the delay line filter and the output of the delay circuit. and extracting a high frequency signal from the means and extracting a low frequency signal from the delay line filter,
At least the frequency phase characteristic of the frequency amplitude characteristic and the frequency phase characteristic of the delay line filter is configured to be substantially equal to the characteristic of the delay circuit in at least the frequency pass band of the predetermined frequency pass band of the delay line filter and its cutoff frequency. There is.

This division filter performs calculations using a delay line filter and a delay circuit that have flat delay characteristics over the entire frequency band, so it can perform calculations more reliably than calculations using a low-pass filter and delay circuit. Moreover, since the delay line filter can be easily constructed using IC technology, it has the advantage that the circuit can be easily miniaturized. However, when configuring a multi-way speaker system, it is necessary to have a crossover frequency that is convenient for the speaker unit being used, but this division filter has problems such as the inability to easily vary the crossover frequency. .

The present invention solves the above problems, and each embodiment thereof will be described below with reference to the drawings.

FIG. 1 shows a block system diagram of a first embodiment (two channels) of a frequency band division filter according to the present invention. In the figure, an audio signal input from an input terminal 1 is supplied to a delay line filter (transversal filter) 2 and a delay circuit 3, which will be described later.The delay line filter 2 waves a predetermined frequency band and delays the signal by a predetermined time. is taken out as it is from the output terminal 4 as the low-frequency side output signal L, and is also supplied to the coefficient arithmetic circuit 5 having coefficients K ₁ and K ₂ and multiplied by the coefficient K ₂ . The time-delayed signal is supplied to the coefficient arithmetic circuit 5, multiplied by a coefficient _K1 , and added to the signal multiplied by a coefficient _K2 from the delay line filter 2, and then output from the output terminal 6 on the high frequency side. It is taken out as signal H. At this time, in the arithmetic circuit 5, the delay circuit 3
The output from the delay line filter 2 and the output from the delay line filter 2 are multiplied by coefficients K ₁ and K _2, respectively, so that the output becomes approximately zero in the passband of the delay line filter 2.

Here, the delay line filter 2 is composed of cascade-connected delay units 7 ₁ to 7 ₆ , coefficient units 8 ₁ to 8 ₇ branch-connected to each terminal of the delay units 7 ₁ to 7 ₆ , and an adder 9 . There is. Delay devices ₇₁ to ₇₆ are composed of circuits that can be easily integrated into ICs such as CCD (charge coupled device) and BBD (bucket brigade device), and the delay time between each tap is set to be the same. , coefficient units 8 ₁ to 8 ₇ are constructed as attenuators whose coefficients are determined by resistance values. As shown in FIG. 2, the coefficients of each coefficient unit ₈₁ to ₈₇ are the largest, with the coefficient of the central coefficient unit ₈₄ being the largest.
The coefficient units 8 ₁ and 8 ₇ at both ends are set so that the coefficients become smaller sequentially, and the sum of the coefficients is set to be 1. On the other hand, the delay circuit 3 is a delay device 7 similar to the delay devices 7 ₁ to 7 ₆ of the delay line filter.
It is composed of ₇ to ₇₉ . A clock pulse is supplied from a clock signal oscillator 15 to each of the delay devices 7 ₁ to 7 ₉ of the delay line filter 2 and the delay circuit 3, and each of the delay devices 7 ₁ to _{7 9} generates a delay time according to the frequency of this clock signal. The input signal is delayed and extracted by using the input signal.

When a signal such as an impulse is applied to the input terminal of the delay line filter 2 configured in this manner, it is sequentially delayed by the delay devices ₇₁ to ₇₆ at a delay speed corresponding to the frequency of the clock signal from the clock signal oscillator 15. The signals taken out from each delay device are multiplied by respective coefficients in coefficient multipliers ₈₁ to ₈₇ , and then added in an adder 9, and a signal with a waveform as shown in FIG. 3 is output from an output terminal 4. The signal is extracted as a waveform signal with the horizontal axis of FIG. 2 as time. In other words, the waveform indicated by each coefficient in FIG. 2 represents the time waveform itself of the impulse response of this delay line filter.

The frequency vs. gain characteristic of a filter that exhibits such an impulse response is as shown in the curve in Figure 4, and in the low frequency band (up to about 300Hz), the phase difference between both terminals of each delay device 7 ₁ to 7 ₆ There is almost no gain, and the gain is approximately the sum of each coefficient, i.e. 1 (0 dB)
Above 300Hz, the phase difference between the outputs of each tap increases and the gain gradually attenuates. Also, the frequency vs. delay characteristic of this delay line filter 2 is the delay time from the input to the input of the coefficient unit with the maximum coefficient, regardless of the frequency band, as shown in the curve in Figure 4. In this case, the delay time is 1.8 ms. be. That is, the delay line filter 2 shown in FIG. 1 operates as a low-pass filter with a constant delay time over substantially the entire frequency band, and is more effective than a low-pass filter alone or a cascade connection of a low-pass filter and a phase shift circuit. The delay time can be constant over the entire band, and can be the same as the delay characteristic (generally constant over the entire band) of the delay circuit 3. In the embodiment shown in FIG. 1, the number of taps is 7, but in order to obtain the characteristics shown in FIG. There is a need. In this case, the delay time between each tap must be sufficiently shorter than the period of the highest frequency handled, and the number of taps must be increased to create a filter with a lower cutoff frequency.

On the other hand, when a signal is applied to the input terminal of the delay circuit 3, the delay circuits ₇₇ to ₇₉ output the clock signal oscillator 15.
The signals are sequentially delayed at a delay speed corresponding to the frequency of the clock signal, and are supplied to the arithmetic circuit 5 together with the output of the delay line filter 2. In this case, the coefficients of the coefficient units 8 _{to 4} of the delay line filter 2 are set to the largest value, so by setting the number of stages of the delay unit of the delay line filter 2 to 6 and the number of stages of the delay circuit 3 to 3, both The amount of delay can be made equal, and calculations can be made between signals having the same amount of delay.

Here, if at least the phase characteristic of the phase characteristic and the amplitude characteristic of the delay line filter 2 is set to be approximately equal to the above-mentioned characteristic of the delay circuit 3 in at least the pass band of its frequency pass band and cut-off frequency, the The output signal and the output signal from the delay line filter 2 are reliably calculated in the calculation circuit 5. Therefore, as shown in FIG. 5, it is possible to obtain a split filter with good low-frequency side cutoff characteristics (curve) and high-frequency side cutoff characteristics (curve).

Here, in order to vary the crossover frequency in FIG. 5, the clock signal oscillator 1 in FIG.
5 is used as a multivibrator, for example, and a variable resistor or the like is varied to vary its output oscillation frequency, the delay times of the delay devices 7 ₁ to 7 ₆ of the delay line filter 2 and the delay circuits 7 ₇ to 7 ₉ of the delay device 3 are as follows. Change uniformly. At this time, the frequency delay characteristic of the delay line filter 2 changes in inverse proportion to the clock signal frequency, and its frequency amplitude characteristic changes in proportion to the clock signal frequency, while the slope of the curve is the same, and the cutoff frequency changes in proportion to the clock signal frequency. , the frequency delay characteristic of the delay circuit 3 changes in inverse proportion to the clock signal frequency. Therefore, the delay circuit 3 and the delay line filter 2
If the delay time of is varied at the same ratio, the arithmetic circuit 5 subtracts the signals whose delay characteristics (phase characteristics) are changed equally, so the frequency amplitude characteristics have the same curve pattern and are cut off. The frequency changes proportionally to the clock signal frequency. Therefore, the delay circuit 3 and the delay line filter 2
If the frequency of the clock signal that drives the clock signal is similarly varied, as shown in FIG. 6, only the crossover frequency can be varied while maintaining the frequency characteristic pattern shown in FIG. 5. The characteristics shown in FIG. 6 are those obtained by using a frequency twice the clock signal frequency in the case of FIG.

Next, considering the amplitude and delay characteristics of this divided filter after synthesis, if the transfer characteristic of delay line filter 2 is LP and the transfer characteristic of delay circuit 3 is D, then If the signals that are The purpose is achieved.

FIG. 7 shows a block system diagram of a second embodiment of the frequency band division filter according to the present invention. In the same figure,
Components that are the same as those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. This embodiment provides a circuit that can reliably drive any number of BBDs or CCDs. The delay circuit 3 and the delay line filter 2 are constructed of BBDs or CCDs as described above, but if commercially available ICs are used, the number of stages of the delay circuit 3 and the number of stages of the delay circuit of the delay line filter 2 are not necessarily the same. It is not necessarily a predetermined ratio. Therefore, for example, as shown in FIG. 7, if a four-stage delay circuit 3' that can obtain a predetermined amount of delay with three stages must be used, the output oscillation frequency of the oscillator 15 in FIG. The output oscillation frequency from the oscillator 15' whose output oscillation frequency is four times that of
The signal is supplied to the delay circuit 3' through the frequency divider ₁₀₁ which divides the frequency by 1/3 to drive the delay circuit 3', while the oscillator 1
It is sufficient to drive the delay line filter ₂ by supplying it to the delay line filter 2 via a frequency divider 102 that divides the output oscillation frequency from the output oscillation frequency 5' into 1/4. At this time, the clock frequency driving the delay circuit 3' is 4/3 of that in the case of Figure 1.
Since the number of stages is 3/4 times that in the case of FIG. 1, the resulting delay time is the same as in the case of FIG. 1, and the characteristics shown in FIG. 5 can be obtained. In this embodiment, when the crossover frequency is to be varied, the output oscillation frequency of the oscillator 15' may be appropriately varied in the same manner as explained in FIG. Since its operation and effects are the same as those shown in FIG. 1, the explanation thereof will be omitted. In this embodiment, the ratio of the clock frequency of the delay circuit 3' to the clock frequency of the delay line filter 2 only needs to be 4:3; for example, two clock signal oscillators may be used to supply each clock signal. can also achieve a similar purpose.

FIGS. 8A and 8B show block diagrams of a third embodiment of the frequency band division filter according to the present invention. This embodiment suppresses and extracts noise caused by carrier signals such as FM broadcasting. When delaying by a clock signal, distortion occurs if the input contains a signal with a frequency higher than half the clock signal frequency. In other words, in general, when handling frequencies of 20Hz to 20KHz as audio signals, no problem will occur if the clock frequency is set to 40KHz or higher, but when receiving FM stereo broadcasts, etc., the 38KHz carrier signal of the stereo broadcast will be included. In this case, distortion may occur. Therefore, as shown in FIG. 8A, low-pass filters 11 ₁ and 11 ₂ for removing the 38KHz carrier signal are connected to the input side of the delay circuit 3 and the input side of the delay line filter 2, respectively, and If a low-pass filter 11 is connected to the connection point between the delay circuit 3 and the delay line filter 2 as shown in FIG. 2, a signal without distortion caused by the carrier signal can be extracted. Here, low-pass filters 11 ₁ and 11 ₂
If they have substantially the same characteristics, the calculation of the calculation circuit 5 will not be affected.

9A and 9B show block diagrams of a fourth embodiment of the frequency band division filter according to the present invention. When the delay is performed by a clock signal, the output of the delay device generally includes the clock signal. If the frequency of the clock signal is set above the audible range, there is no need to worry about hearing it, but doing so will give unnecessary signals to the speaker or amplifier, so it is often better to remove the clock signal. . Therefore, as shown in FIG. 9A, low-pass filters 12 ₁ and 12 ₂ that wave signals below the clock signal frequency band may be connected to the output sides of the delay circuit 3 and the delay line filter 2, respectively. As shown in FIG. B, by connecting low-pass filters 12 ₁ and 12 ₂ to the output side of the arithmetic circuit 5 and the output side of the delay line filter 2, respectively, it is possible to extract a signal that does not include a clock signal. Here, low-pass filter 12 ₁ and 1
2 and ₂ have substantially the same characteristics, the calculation of the arithmetic circuit 5 and the characteristics of the filter after synthesis are not affected.

FIG. 10 shows a block system diagram of a fifth embodiment (three channels) of the frequency band division filter according to the present invention. In the figure, the characteristics of each set of delay circuits 3 ₁ and 2 ₂ and delay line filters 2 ₁ and _{2 2} are set similarly to the characteristics of the filters shown in FIG. The phase characteristics of 2 with the same subscript
It is set to be the same as the phase characteristic after the division filter is synthesized. Also, at least the phase characteristics of the amplitude characteristics and phase characteristics of the delay line filters 2 ₁ and 2 ₂ are set to be approximately equal to the above-mentioned characteristics of the delay circuits 3 ₁ and 3 ₂ in at least the pass band of the frequency pass band and cutoff frequency. and any 2
The circuits having the same phase characteristics are also connected to the outputs of the dividing filters. On the other hand, the delay circuits 3 ₁ , 3' ₁ and the delay line filter 2
₁ is supplied with a clock pulse from a clock signal oscillator 15. 13 ₁ , 13 ₂ is an adder;
4 is a midrange signal output terminal.

Here, as explained in the first embodiment, when the output oscillation frequency of the oscillator 15 is varied, the two-part filter of the delay circuit 3 ₁ and the delay line filter 2 ₁ maintains the frequency characteristic pattern. Only the crossover frequency can be made variable as it is, and on the other hand, the frequency characteristics of the delay circuit _3'1 can also be made variable. In this case, the amplitude characteristics and delay characteristics after combining the two-divided filters of the delay circuit 3 ₁ and the delay line filter 2 ₁ become the characteristic D of the delay circuit 3 ₁ as explained in the first embodiment, so the delay circuit 3 ' If the frequency characteristics of ₁ are changed in the same way as the characteristics of the two-division filter with the same subscript, among the high frequency signal, middle frequency signal, and low frequency signal output from output terminals 6, 14, and 4, respectively. The crossover frequency between the high frequency signal and the mid frequency signal can be changed.

In the embodiment shown in FIG. 10, if the number of BBD stages used in the delay circuit ₃₁ and the number of BBD stages used in the delay circuit _3'1 are different, the number of stages is different as in the second embodiment shown in FIG. It is sufficient to drive each of them with the same clock frequency ratio as the ratio of . Further, in this embodiment, the delay line filter ₂₂ may be a general low-pass filter, or conversely, the delay circuit ₃₂ and the delay line filter ₂₂ may be driven by the oscillator 15, and the delay circuits ₃₁ , 3 may be driven by the oscillator 15. ' ₁ and delay line filter 2
₁ may be driven by an oscillator, or both may be driven by respective oscillators.

Further, although the delay circuit and delay line filter in the above embodiment have been explained using a BBD configured to shift an analog value by a clock signal, A-D
A delay circuit that converts an analog signal into a digital quantity, delays it with a shift register, etc., and converts it back into D-A, or a delay circuit that modulates an analog signal with Δm (delta-em), delays it as a digital quantity with a shift register, etc., and then demodulates it. etc., and the object of the present invention can be achieved as long as a delay device whose delay time can be varied with the frequency of the clock signal is used.

Furthermore, for the purpose of reducing noise, the filters shown in FIGS. 8A and B may be combined with the filters shown in FIGS. 1 and 7, or the filters shown in FIGS. 9A and B may be combined with the filters shown in FIGS. The filter shown in FIG. 7 may be used in combination, or the filter shown in FIGS. 8A, B and 9 A, B may be used in combination with the filter shown in FIGS. 1 and 7.

In addition, the impulse response of the delay line filter is not only the triangular wave pulse (Fig. 3) as in the above embodiment, but also a raised cosine pulse, a raised cosine pulse, etc. depending on the desired filter characteristics.
It may be arbitrarily selected by appropriately setting the coefficients of the coefficient unit constituting the rectangular wave pulse delay line filter.

In addition, in the explanation so far, the delay line filter has been shown as a non-recursive type (also called a non-recursive or transversal type) that does not include feedback, but a cyclic type (also called a recursive type) that includes feedback. If it is possible to obtain the desired filter characteristics,
The filter 2 may be such a delay line filter.

As described above, the frequency band division filter of the present invention has coefficients that are symmetrical with respect to the center tap of the delay devices at the output from each connection point of the plurality of delay devices connected in cascade to the input terminal. a delay line filter that multiplies these outputs and adds these outputs to take out the output, a delay circuit consisting of a plurality of delay devices connected in cascade to the above input terminal, and a clock signal of a predetermined frequency is supplied to each of the above delay devices. A clock signal oscillator and an arithmetic circuit that calculates and extracts the outputs of the delay line filter and delay circuit are provided, and by varying the frequency of the clock signal, a predetermined band that is extracted from the delay line filter and the arithmetic circuit is provided. Since the crossover frequency of the frequency signal is configured to be variable, the calculation is performed using a delay means with flat delay characteristics over the entire frequency band, so the calculation is more reliable than calculations using a low-pass filter, etc. As a result, it is possible to obtain a filter with good cutoff characteristics over a wide frequency band, and moreover, compared to the previously proposed filter, only the crossover frequency can be easily varied while keeping the cutoff characteristics of the filter unchanged. As a result, when configuring a multi-way speaker system, it is possible to arbitrarily set a convenient crossover frequency for the speaker unit, and the delay line filter can be used with BBD, CCD, etc.
Since it can be easily configured using IC technology, it is easy to downsize the circuit, and the characteristics of the entire filter after synthesis are
Since the amplitude characteristics and delay characteristics are equal to those of only a flat delay circuit, it is possible to obtain signals in multiple frequency bands with flat amplitude characteristics, delay characteristics, and delay characteristics even if a delay line filter with any characteristics is used as the delay line filter. Since the difference between the output of the delay circuit and the output of the delay line filter can be obtained by subtracting signals that are substantially in phase with each other, it is much easier than subtracting signals that are out of phase as in the conventional example. Therefore, the high frequency signal component exhibits a sharper cut-off characteristic than the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of a first embodiment of the frequency band division filter according to the present invention, FIG. 2 is a diagram for explaining the relationship between the coefficient unit of the delay line filter shown in FIG. 1 and its coefficients, 3 is an output waveform diagram for explaining the impulse response of the delay line filter shown in FIG. 1, FIG. 4 is a cutoff characteristic and delay characteristic diagram of the delay line filter shown in FIG. 1, and FIG. FIG. 6 is a cut-off characteristic diagram of the filter shown in FIG. 1 when the clock frequency is varied, and FIGS. FIG. 7 is a block system diagram of second to fifth embodiments. 1... Input terminal, 2, 2 ₁ , 2 ₂ ... Delay line filter, 3 _, 3 ₁ , 3 2 , 3' ₁ , 3'... Delay device, 7 ₁ to 7 ₉ ... Delay device, 4, 6, 14...Output terminal, 5...Arithmetic circuit with coefficient, ₈₁ to ₈₇ ...
Coefficient unit, 9, 13 ₁ , 13 ₂ ... Adder, 10
₁ , 10 ₂ ... frequency divider, 11, 11 ₁ , 11 ₂ ,
12 ₁ , 12 ₂ ...low-pass filter, 15, 15'
...Clock signal oscillator.

Claims (1)

[Claims] 1 A frequency band dividing filter that divides a signal coming from an input terminal into a plurality of frequency bands and extracts the signal, which outputs the signal from each connection point of a plurality of delay devices connected in cascade to the input terminal. A delay line filter that multiplies a coefficient that is symmetrical to the center tap of the delay device and adds these outputs to take out the output, and a delay circuit that includes a plurality of delay devices connected in cascade to the input terminal. , a clock signal oscillator that supplies a clock signal of a predetermined frequency to each of the delay devices, and an arithmetic circuit that calculates and extracts the output of the delay line filter and the output of the delay circuit, and the frequency of the clock signal is variable. A frequency band dividing filter characterized in that the crossover frequency of the predetermined band frequency signals respectively output from the delay line filter and the arithmetic circuit is varied.