JPS6134275B2 - - Google Patents
Info
- Publication number
- JPS6134275B2 JPS6134275B2 JP15629080A JP15629080A JPS6134275B2 JP S6134275 B2 JPS6134275 B2 JP S6134275B2 JP 15629080 A JP15629080 A JP 15629080A JP 15629080 A JP15629080 A JP 15629080A JP S6134275 B2 JPS6134275 B2 JP S6134275B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- electrode
- type layer
- light emitting
- multicolor light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 description 16
- 239000011701 zinc Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 229910015363 Au—Sn Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
Description
【発明の詳細な説明】 本発明は多色発光素子の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a multicolor light emitting device.
第１図は、GaP（ガリウム隣）多色発光素子を
示し、１はキヤリア濃度が0.5〜10×1017cm-3であ
るＮ型GaP結晶基板であり、該結晶基板１の一主
面２の結晶方位は１１１Ｂ面である。 FIG. 1 shows a GaP (next to gallium) multicolor light emitting device, in which 1 is an N-type GaP crystal substrate with a carrier concentration of 0.5 to 10×10 17 cm −3 , and one main surface 2 of the crystal substrate 1 The crystal orientation of is the 111B plane.
３〜６は上記結晶基板１の一主面２上に順次エ
ピタキシヤル成長させて積層したGaPからなる第
1N型層、第1P型層、第2P型層、第2N型層であ
る。 3 to 6 are GaP layers formed by sequential epitaxial growth on one principal surface 2 of the crystal substrate 1;
They are a 1N type layer, a 1st P type layer, a 2nd P type layer, and a 2nd N type layer.
第1N型層３はTe（テルル）を不純物として含
み、５〜10×1017cm-3のキヤリア濃度を有する。
第1P型層４はZn（亜鉛）を不純物として含み、
１〜５×1017cm-3の濃度を有すると共に更にＯ
（酸素）を含み発光中心としてのZn−Ｏペアを有
している。従つて第1N型層３と第1P型層４との
境界には赤色発光接合７が存在することとなる。 The first N-type layer 3 contains Te (tellurium) as an impurity and has a carrier concentration of 5 to 10×10 17 cm −3 .
The first P-type layer 4 contains Zn (zinc) as an impurity,
It has a concentration of 1 to 5 × 10 17 cm -3 and also O
(oxygen) and has a Zn-O pair as a luminescent center. Therefore, a red light-emitting junction 7 exists at the boundary between the first N-type layer 3 and the first P-type layer 4.
第2P型層５はZnを不純物として含み、５〜10
×1017cm-3のキヤリア濃度を有し、第2N型層６は
Ｓ（硫黄）を不純物として含み、１〜20×1016cm
-3のキヤリア濃度を有する。更に第2P型層５及び
第2N型層６は共に発光中心としてのＮ（窒素）
を含んでいるので第2P型層５と第2N型層６との
境界には緑色発光接合８が存在することとなる。 The second P-type layer 5 contains Zn as an impurity, and contains 5 to 10
The second N -type layer 6 contains S (sulfur) as an impurity, and has a carrier concentration of 1 to 20 × 10 16 cm
It has a carrier density of -3 . Furthermore, both the second P-type layer 5 and the second N-type layer 6 contain N (nitrogen) as a luminescent center.
Therefore, a green light-emitting junction 8 exists at the boundary between the second P-type layer 5 and the second N-type layer 6.
９は上記第2N型層６表面にAu−Sn（金−錫）
を蒸着させてなる円形の第１電極、１０は上記結
晶基板１裏面にAu−Snを蒸着させてなる円形の
第２電極、１１は第2N型層６より深く、第1N型
層３に達しない深さの段部１２にAu−Zn（金−
亜鉛）を蒸着させてなる第３電極である。 9 is Au-Sn (gold-tin) on the surface of the second N-type layer 6.
10 is a circular second electrode formed by vapor-depositing Au-Sn on the back surface of the crystal substrate 1; 11 is deeper than the second N-type layer 6 and reaches the first N-type layer 3; Au-Zn (gold-
The third electrode is formed by vapor-depositing zinc.
従つて第３電極１１を共通正電極として第１電
極９−第３電極１１間に順方向バイアスをかけれ
ば緑色発光接合８付近で緑色発光が生じ、第２電
極１０−第３電極１１間に順方向バイアスをかけ
れば赤色発光接合７付近で赤色発光が生じる。ま
た、第１電極９−第３電極１１間及び第２電極１
０−第３電極１１間に夫々順方向バイアスをかけ
両接合８，７に流れる電流を夫々調整することに
より赤から緑までの種々の発光色を得ることが可
能である。 Therefore, if the third electrode 11 is used as a common positive electrode and a forward bias is applied between the first electrode 9 and the third electrode 11, green light will be emitted near the green light emitting junction 8, and light will be emitted between the second electrode 10 and the third electrode 11. When a forward bias is applied, red light emission occurs near the red light emitting junction 7. Moreover, between the first electrode 9 and the third electrode 11 and between the second electrode 1
By applying a forward bias between the 0 and 3rd electrodes 11 and adjusting the current flowing through both junctions 8 and 7, it is possible to obtain various emitted light colors from red to green.
第２図はGaP多色発光素子の製造方法における
従来の工程を示す。 FIG. 2 shows conventional steps in a method for manufacturing a GaP multicolor light emitting device.
第２図Ａは第１の工程を示し、Ｎ型GaP結晶基
板１３の結晶方位が１１１Ｂ面である一主面１４
上にGaPからなる第1N型層１５、第1P型層１
６、第2P型層１７、第2N型層１８を順次エピタ
キシヤル成長させて積層してなるGaP多色発光素
子基板１９を準備する。 FIG. 2A shows the first step, in which one main surface 14 of the N-type GaP crystal substrate 13 has a crystal orientation of 111B plane.
A first N-type layer 15 made of GaP and a first P-type layer 1 on top.
6. A GaP multicolor light emitting device substrate 19 is prepared by epitaxially growing a second P type layer 17 and a second N type layer 18 in order.
第２図Ｂは第２の工程を示し、上記素子基板１
９表面にAu−Znを蒸着してなる円形の第１電極
２０を一定間隔で形成すると共に、上記素子基板
１９裏面にAu−Znを蒸着してなる円形の第２電
極２１を一定間隔で形成する。 FIG. 2B shows the second step, in which the element substrate 1
9, circular first electrodes 20 made by vapor depositing Au-Zn are formed at regular intervals, and circular second electrodes 21 made by vapor depositing Au-Zn are formed at regular intervals on the back surface of the element substrate 19. do.
第２図Ｃは第３の工程を示し、素子基板１９表
面にホトレジ等によりエツチングマスク２２を形
成する。 FIG. 2C shows the third step, in which an etching mask 22 is formed on the surface of the element substrate 19 by photoresist or the like.
第２図Ｄは第４の工程を示し、隣り合う第１電
極２０間に存在するエツチングマスク２２の一部
をホトエツチング等により除去し紙面垂直方向に
延在する幅Ａの開口２３を形成する。 FIG. 2D shows a fourth step, in which a portion of the etching mask 22 existing between adjacent first electrodes 20 is removed by photoetching or the like to form an opening 23 having a width A extending in the direction perpendicular to the plane of the paper.
第２図Ｅは第５の工程を示し、上記素子基板１
９表面のエツチングマスク２２の施されていない
開口２３部に王水等によりエツチングを施し紙面
垂直方向に延在する溝２４を形成する。 FIG. 2E shows the fifth step, in which the element substrate 1
The opening 23 on the surface 9 where the etching mask 22 is not formed is etched with aqua regia or the like to form a groove 24 extending in the direction perpendicular to the plane of the paper.
このときエツチング方向は結晶基板１３に向か
う方向だけでなく素子基板１９表面と平行となる
方向にも存在し、従つて上記溝２４はエツチング
マスク２２下まで拡張される。また、上記溝２４
は第2N型層１８より深く、第1N型層１５に達し
ない深さＢに形成される。 At this time, the etching direction exists not only toward the crystal substrate 13 but also in a direction parallel to the surface of the element substrate 19, so that the groove 24 is extended to below the etching mask 22. In addition, the groove 24
is formed at a depth B that is deeper than the second N-type layer 18 and does not reach the first N-type layer 15.
第２図Ｆは第６の工程を示し、上記溝２４底面
に第３電極２５をAu−Znを蒸着することにより
形成する。 FIG. 2F shows a sixth step, in which a third electrode 25 is formed on the bottom surface of the groove 24 by depositing Au--Zn.
上記蒸着方向は図中矢印で示す如く水平に載置
された素子基板１９表面に対して略垂直となる方
向より行なう。このとき溝２４がエツチングマス
ク２２下まで拡張されており、従つてエツチング
マスク２２の一部が溝２４に対してひさしとなり
溝２４の側壁へ第３電極２５が形成されない。 The vapor deposition is performed in a direction substantially perpendicular to the surface of the element substrate 19 placed horizontally, as shown by the arrow in the figure. At this time, the groove 24 is extended to the bottom of the etching mask 22, and therefore, a part of the etching mask 22 serves as an overhang for the groove 24, and the third electrode 25 is not formed on the side wall of the groove 24.
第２図Ｇは第７の工程を示し、エツチングマス
ク２２を除去する。 FIG. 2G shows the seventh step, in which the etching mask 22 is removed.
第２図Ｈは最終工程を示し、溝２４の一方の測
壁つまり図中−間に沿つてダイシングを行な
い第１図の素子を分離形成する。 FIG. 2H shows the final step, in which dicing is performed along one wall of the groove 24, that is, along the center line in the figure, and the elements shown in FIG. 1 are separated and formed.
上記第２図の工程において開口２３の幅Ａは
100〜150μｍ、溝２４の深さＢは30μｍ程度であ
り、溝２４の深さＢに対して開口２３の幅Ａが狭
く、従つて溝２４の底面は平坦とならず、このよ
うな面に蒸着形成された第３電極２５表面も平坦
とならない。 In the process shown in FIG. 2 above, the width A of the opening 23 is
The depth B of the groove 24 is about 30 μm, and the width A of the opening 23 is narrower than the depth B of the groove 24, so the bottom surface of the groove 24 is not flat. The surface of the third electrode 25 formed by vapor deposition is also not flat.
このような平坦でない第３電極２５表面に金属
細線をボンデイングしようとしても困難であり、
失敗率もかなり高くなる。 It is difficult to bond a thin metal wire to such an uneven surface of the third electrode 25;
The failure rate is also quite high.
そこで溝２４の底面を平坦にする方法として開
口２３を充分広くすることが考えられるが、ただ
単に開口２３を広くするだけでは最終的なチツプ
サイズが大きくなり、従つて一枚の素子基板１９
から製造される発光素子数が減少してしまうとい
う問題が生じる。 Therefore, one possible method for flattening the bottom surface of the groove 24 is to make the opening 23 sufficiently wide, but simply making the opening 23 wide will increase the final chip size, and therefore, it will be difficult to make one element substrate 19.
A problem arises in that the number of light emitting elements manufactured from the above method decreases.
本発明は上記の点に鑑みてなされたもので、以
下一実施例に基づき本発明を詳述する。 The present invention has been made in view of the above points, and will be described in detail below based on one embodiment.
第３図は本発明における一実施例の多色発光素
子の製造工程を示す。 FIG. 3 shows the manufacturing process of a multicolor light emitting device according to an embodiment of the present invention.
第３図Ａは本実施例における第１の工程を示
し、一主面３０が１１１Ｂ面であるＮ型GaP結晶
基板３１上にGaPからなる第1N型層３２、第1P
型層３３、第2P型層３４、第2N型層３５を順次
エピタキシヤル成長させて積層してなるGaP多色
発光素子基板３６を準備する。 FIG. 3A shows the first step in this embodiment, in which a first N-type layer 32 made of GaP, a first P
A GaP multicolor light emitting element substrate 36 is prepared by sequentially epitaxially growing a type layer 33, a second P type layer 34, and a second N type layer 35 and stacking them.
第３図Ｂは第２の工程を示し、素子基板３６表
面（第2N型層３５表面）にAu−Snを蒸着して円
形の第１電極３７を形成すると共に素子基板３６
裏面にAu−Snを蒸着して円形の第２電極３８を
形成する。 FIG. 3B shows the second step, in which Au-Sn is vapor-deposited on the surface of the element substrate 36 (the surface of the second N-type layer 35) to form a circular first electrode 37 and
A circular second electrode 38 is formed by depositing Au-Sn on the back surface.
このとき第１電極３７は２個を１組として一定
間隔で形成され、第２電極３８は第１電極３７と
対向する素子基板３６の裏面に形成されている。 At this time, the first electrodes 37 are formed in sets of two at regular intervals, and the second electrodes 38 are formed on the back surface of the element substrate 36 facing the first electrodes 37.
第３図Ｃは第３の工程を示し、素子基板３６表
面にホトレジ等によりエツチングマスク３９を形
成する。 FIG. 3C shows the third step, in which an etching mask 39 is formed on the surface of the element substrate 36 by photoresist or the like.
第３図Ｄは第４の工程を示し、隣接する第１電
極３７の組の間のエツチングマスク３９をホトエ
ツチング等により除去し、紙面垂直方向に延在す
る幅A′の開口４０を設ける。 FIG. 3D shows a fourth step, in which the etching mask 39 between adjacent sets of first electrodes 37 is removed by photoetching or the like to form an opening 40 having a width A' extending in the direction perpendicular to the plane of the paper.
上記開口４０の幅A′は第２図に示した従来例
の溝２４の幅Ａに比して約２〜３倍である300μ
ｍ程度である。 The width A' of the opening 40 is 300μ, which is about 2 to 3 times the width A of the groove 24 of the conventional example shown in FIG.
It is about m.
第３図Ｅは第５の工程を示し、上記素子基板３
６表面のエツチングマスク３９が施されていない
開口４０に王水等によりエツチングを施し紙面垂
直方向に延在する溝４１を形成する。 FIG. 3E shows the fifth step, in which the element substrate 3
Etching is performed using aqua regia or the like on the openings 40 on the surface 6 where the etching mask 39 is not applied to form grooves 41 extending in the direction perpendicular to the plane of the paper.
上記溝４１は上記第２図Ｅの工程において形成
された溝２４と同様にエツチングマスク３９下ま
で拡張され、かつ第2N型層３５より深く、第1N
型層３２に達しない深さB′、つまり第２図に示し
た溝２４の深さＢと同じく約30μｍに形成され
る。 The groove 41 extends below the etching mask 39 like the groove 24 formed in the step shown in FIG.
It is formed to a depth B' that does not reach the mold layer 32, that is, about 30 μm, which is the same as the depth B of the groove 24 shown in FIG.
従つて、第２図に示した従来例に比して幅B′が
深さＡに対して充分大きく、開口４０の真下に位
置する溝４１の底面は平坦となる。 Therefore, compared to the conventional example shown in FIG. 2, the width B' is sufficiently larger than the depth A, and the bottom surface of the groove 41 located directly below the opening 40 is flat.
第３図Ｆは第６の工程を示し、溝４１の底面に
Au−Znを蒸着して第３電極４２を形成する。 FIG. 3F shows the sixth step, in which the bottom surface of the groove 41 is
The third electrode 42 is formed by depositing Au-Zn.
上記蒸着は素子基板３６を水平に載置し素子基
板３６表面に垂直となる方向より行なう。このと
き溝４１がエツチングマスク３９下まで拡張形成
されているためエツチングマスク３９の一部が溝
４１に対してひさしとなるので第３電極４２は溝
４１の側壁に形成されることなく平坦な溝４１の
全底面に表面が平坦となるように形成される。 The above vapor deposition is carried out in a direction perpendicular to the surface of the element substrate 36 with the element substrate 36 placed horizontally. At this time, since the groove 41 is extended to the bottom of the etching mask 39, a part of the etching mask 39 serves as an overhang for the groove 41, so the third electrode 42 is not formed on the side wall of the groove 41, but instead is formed in a flat groove. 41 so that the entire bottom surface thereof is flat.
第３図Ｇは第７の工程を示し、エツチングマス
ク３９を除去する。 FIG. 3G shows the seventh step, in which the etching mask 39 is removed.
第３図Ｈは本実施例の最終工程を示し、溝４１
の略中心線つまり図中−間及び組となつてい
る第１電極３７と第１電極３７との間を溝４１の
延在方向と平行となる方向、つまり図中−間
に沿つて夫々ダイシングを行ない第１図の素子を
分離成形する。 FIG. 3H shows the final step of this embodiment, in which the groove 41
Dicing is performed along the approximate center line of the figure, that is, the direction parallel to the direction in which the groove 41 extends, that is, between the first electrodes 37 and the pair of first electrodes 37, that is, along the middle line of the figure, respectively. The elements shown in FIG. 1 are separately molded.
本実施例では第３電極４２は平坦となると共に
第３図Ｈに示す如く−間及び−間に沿つ
て夫々ダイシングを行なうため、得られた素子は
第２図で得られた素子に比して第３電極４２が平
坦であり、かつ素子の大きさも従来の素子（350
μｍ角の寸法）と比して決して大きくならない。 In this example, the third electrode 42 becomes flat and is diced along the - and - spaces as shown in FIG. Therefore, the third electrode 42 is flat, and the size of the element is similar to that of the conventional element (350 mm).
It never becomes larger than the size (in μm square).
尚、上記実施例では第１電極３７をダイシング
線−の両側に個別に設けたが第４図に示す如
くダイシング線−を跨がるように一体に設け
ても最終的には第１図の素子に分離成形されるこ
とは明白である。 In the above embodiment, the first electrodes 37 were individually provided on both sides of the dicing line, but even if they were provided integrally across the dicing line as shown in FIG. 4, the final result would be as shown in FIG. It is clear that the elements are separately molded.
以上の説明から明らかな如く、本発明によれば
多色発光素子の溝底面に形成された電極は平坦と
なり、従つて上記電極にワイヤボンドする際に失
敗率が低くなる。また例えば本発明により直径50
mmのGaP多色発光素子基板から得られる素子数は
第２図に示した従来方法の場合と同じ１万個程度
となり素子基板の利用効率も低下することがな
い。 As is clear from the above description, according to the present invention, the electrode formed on the bottom surface of the groove of the multicolor light emitting element becomes flat, and therefore the failure rate when wire bonding to the electrode is lowered. For example, according to the present invention, diameter 50
The number of devices obtained from a GaP multicolor light emitting device substrate of mm is about 10,000, which is the same as in the conventional method shown in FIG. 2, and the utilization efficiency of the device substrate is not reduced.
第１図はGaP多色発光素子の断面図、第２図Ａ
〜Ｈは従来のGaP多色発光素子の製造方法を示す
工程別断面図、第３図Ａ〜Ｈは本発明によるGaP
多色発光素子の製造方法の一実施例を示す工程別
断面図、第４図は本発明の他の実施例を示す断面
図である。
３６……（GaP）多色発光素子基板、３７……
第１電極（電極手段）、４１……溝、４２……第
３電極。
Figure 1 is a cross-sectional view of a GaP multicolor light emitting device, Figure 2A
~H are cross-sectional views showing each step of the conventional GaP multicolor light emitting device manufacturing method, and Figures 3A~H are GaP according to the present invention.
FIG. 4 is a cross-sectional view showing another example of the present invention. 36... (GaP) multicolor light emitting element substrate, 37...
First electrode (electrode means), 41... groove, 42... third electrode.
Claims (1)
基板表面に一定間隔で電極手段を形成する工程
と、隣接する上記電極手段の間に溝を形成する工
程と、該溝の底面に電極を形成する工程と、上記
溝の略中心線に沿いダイシングすると共に上記電
極手段の略中央を溝の延在方向と平行となる方向
にダイシングする工程とからなることを特徴とす
る多色発光素子の製造方法。 ２ 上記電極手段は上記ダイシング工程前に一体
に形成されていることを特徴とする特許請求の範
囲第１項記載の多色発光素子の製造方法。 ３ 上記電極手段は上記ダイシング工程前にダイ
シング線の両側に個別に形成されていることを特
徴とする特許請求の範囲第１項記載の多色発光素
子の製造方法。[Claims] 1. A step of preparing a multicolor light emitting element substrate, a step of forming electrode means at regular intervals on the surface of the element substrate, a step of forming grooves between the adjacent electrode means, The method is characterized by comprising a step of forming an electrode on the bottom surface of the groove, and a step of dicing along the approximate center line of the groove and dicing approximately the center of the electrode means in a direction parallel to the extending direction of the groove. A method for manufacturing a multicolor light emitting device. 2. The method of manufacturing a multicolor light emitting device according to claim 1, wherein the electrode means is integrally formed before the dicing step. 3. The method of manufacturing a multicolor light emitting device according to claim 1, wherein the electrode means are individually formed on both sides of the dicing line before the dicing step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15629080A JPS5779687A (en) | 1980-11-05 | 1980-11-05 | Manufacture of polychromic luminous element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15629080A JPS5779687A (en) | 1980-11-05 | 1980-11-05 | Manufacture of polychromic luminous element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5779687A JPS5779687A (en) | 1982-05-18 |
| JPS6134275B2 true JPS6134275B2 (en) | 1986-08-06 |
Family
ID=15624570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15629080A Granted JPS5779687A (en) | 1980-11-05 | 1980-11-05 | Manufacture of polychromic luminous element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5779687A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0743958U (en) * | 1993-05-06 | 1995-10-09 | 俊雄 半田 | Shogi set with pockets |
-
1980
- 1980-11-05 JP JP15629080A patent/JPS5779687A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0743958U (en) * | 1993-05-06 | 1995-10-09 | 俊雄 半田 | Shogi set with pockets |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5779687A (en) | 1982-05-18 |
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