JPS6133019A - Frequency divider - Google Patents

Abstract

PURPOSE:To keep the duty of a clock frequency at 0.5 despite of the variation of said clock frequency by forming the titled device of a counter circuit, 1/2 dividing circuit, shift register circuit, and an exclusive OR circuit, etc. CONSTITUTION:A counter circuit 1 uses a signal to be divided as an input and delivers an output signal 4 produced by dividing a clock frequency down to 1/2(2N+1) to a 1/2 dividing circuit 6. A frequency dividing circuit 2 divides the signal 4 down to 1/2 and set the duty at 0.5 to deliver it to a shift register 7 and an exclusive OR circuit 8. A shift register circuit 7 delays an output signal 9 of the circuit 6 by N bits and delivers it to the circuit 8. The circuit 8 outputs an output signal 11 having a clock frequency 1/2(2N+1) and duty (N+1)/(2N+1). Thus the duty of the signal 11 is set <=0.5+ or -0.15 regardless of the clock frequency with a divider of >=1/5 division.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a frequency divider used, for example, in a PCM TV transmission device, to modify the duty of an output signal of the frequency divider. It is something.

[Prior art]

A conventional frequency divider of this type is shown in FIG. Figure 1 is a block diagram showing a conventional frequency divider;
The figure is a signal waveform diagram of each part in the frequency divider of FIG. 1. In each figure, a 1-digit counter circuit, 2 a retriggerable monostable flip-flop circuit, 3 a divided signal input to the counter circuit 1, 4 an output signal of the counter circuit 1, and 5
is the output signal of the retriggerable monostable flip-flop circuit 2.

In the frequency divider configured as shown in FIG. 1, the counter circuit 1 receives the frequency-divided signal 3 as an input and outputs an output signal 4 obtained by dividing the clock frequency by 1/(2N+1).

However, the duty of output signal 4 is 2N/(2N+1)
becomes. When the branch signal is used as a signal, the duty of this signal must be 0.5±0.15 or less. The retriggerable monostable flip-flop circuit 2 inputs the output signal 4 of the counter circuit 1, applies a trigger at the rising edge of this input signal, resets the CR time constant, and adjusts the pulse width to a duty of 0.5. A pulse-like output signal 5 set to .

Conventional frequency dividers are configured as described above, so when the clock frequency changes, it is necessary to reset the CR time constant, which has the disadvantage of making the operation complicated. .

[Summary of the invention]

This invention was made for the purpose of improving the drawbacks of the conventional ones as described above, and includes a counter circuit, a 1/2 frequency divider circuit,
By configuring a frequency divider with a shift register circuit, an exclusive OR circuit, etc., even if the clock frequency changes, the clock frequency can be divided to 1/(2N+1>) without adjustment.
This provides a frequency divider that can set the duty to 0 or 5.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing a frequency divider according to an embodiment of the present invention, and FIG. 4 is a signal waveform diagram of each part of the frequency divider shown in FIG. In each figure, 1 is a counter circuit, 6
is a 1/2 frequency divider circuit, 7 is a shift register circuit, and 8 is an exclusive OR circuit.

Further, 3 is a frequency-divided signal input to the counter circuit 1, 4 is an output signal of the counter circuit 1, 9 is an output signal of the 1/2 frequency divider circuit 6, 10 is an output signal of the shift register circuit 7, 11
is the output signal of the exclusive OR circuit 8.

In the frequency divider configured as shown in FIG. 3 above, a counter circuit 1 receives a frequency-divided signal 3 as an input, and divides an output signal 4 obtained by dividing the clock frequency by 1/(2N+1) by 1/2. Output to circuit 6. This 1/2 frequency divider circuit 6 divides the clock frequency of the output signal 4 of the counter circuit 1 into 1/2, sets the duty to 0.5, and outputs it to the shift register circuit 7 and the exclusive OR circuit 8. do. The shift register circuit 7 inputs the divided signal 3 and the output signal 9 of the 1/2 frequency divider 6, and receives the output signal 9 of the 1/2 frequency divider 6 by N bits.
is delayed and output to the exclusive OR circuit 8.

This exclusive OR circuit 8 inputs the output signal 9 of the 1/2 frequency divider circuit 6 and the output signal 10 of the shift register circuit 7, has a clock frequency of 1/(2N+1), and a duty of (N+1)/( 2N+1) output signal 11 can be output. In this way, in the frequency divider according to the present invention, the duty of the output signal 11 is 0.5±0.15 or less in a frequency divider with a frequency division of 175 or more, and this characteristic is independent of the above-mentioned clock frequency. It is something that becomes.

〔Effect of the invention〕

As explained above, in this invention, the frequency divider is configured by a counter circuit, a 1/2 frequency divider circuit, a shift register circuit, an exclusive OR circuit, etc.
+1), there is no adjustment even if the clock frequency changes, and the four clock frequency can be divided by 1/(2N+1') and the duty factor can be set to 0.5, making it easy to operate. This makes it simple and easy, and provides excellent effects such as obtaining highly accurate frequency division characteristics.

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram showing a conventional frequency divider, Fig. 2 is a signal waveform diagram of each part in the frequency divider of Fig. 1, and Fig. 3 shows a frequency divider according to an embodiment of the present invention. The block diagram shown in FIG. 4 is a signal waveform diagram of each part in the frequency divider of FIG. 3. In the figure, 1... Counter circuit, 2... Retriggerable monostable flip-flop circuit, 3φ... Divided signal, 4, 5, 9, 10, 11... Output signal, 6... 1
/2 frequency divider circuit, 7... shift register circuit, 8...
It is an exclusive OR circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In the frequency divider, input the frequency-divided signal to the input terminal of the counter circuit and the clock input terminal of the shift register circuit, and connect the output terminal of the counter circuit to the input terminal of the 1/2 frequency divider circuit, The output terminal of this 1/2 frequency divider circuit is connected to one end of the data input terminal of the shift register circuit and the input terminal of the exclusive OR circuit, and the output terminal of the shift register circuit is connected to the input terminal of the exclusive OR circuit. A frequency divider, which is connected to the other end of the terminal, and obtains a frequency-divided signal output from the output terminal of the exclusive OR circuit. (2) In the frequency divider, when dividing the frequency by 1/(2N+1), the delay amount in the shift register circuit is N
2. The frequency divider according to claim 1, wherein the frequency divider is a bit.