JPS6132588A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6132588A
JPS6132588A JP15436284A JP15436284A JPS6132588A JP S6132588 A JPS6132588 A JP S6132588A JP 15436284 A JP15436284 A JP 15436284A JP 15436284 A JP15436284 A JP 15436284A JP S6132588 A JPS6132588 A JP S6132588A
Authority
JP
Japan
Prior art keywords
layer
inp
laser
bipolar transistor
clad layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15436284A
Other languages
Japanese (ja)
Inventor
Ichiro Nakao
中尾　一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15436284A priority Critical patent/JPS6132588A/en
Publication of JPS6132588A publication Critical patent/JPS6132588A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To improve yield by further growing each layer for a bipolar transistor onto a stepped-section substrate type semiconductor laser. CONSTITUTION:A stepped section is formed onto an n type InP substrate 21, and an n-InP clad layer 22, an InGaAsP active layer 23 and a p-InP clad layer 24 for a laser L are shaped. An n-InP collector layer 25, a p-InGaAsP base layer 26 and an n-InP emitter layer 27 for a bipolar transistor T are formed continuously, and an electric element isolation diffusion region 28 is shaped up to the p-InP clad layer 24. Consequently, a region surrounded by the isolation diffusion region 28 and the p-InP clad layer 24 is isolated electrically, thus integrating a plurality of electric elements. A diffusion region 29 for injecting currents in the laser L is shaped up to the p-clad layer 24. Accordingly, the TS type semiconductor laser and the bipolar transistor are unified, thus simplifying a manufacturing process, then improving yield.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体レーザと電気素子を一体化する半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device that integrates a semiconductor laser and an electric element.

従来例の構成とその問題点 半導体レーザと電気素子を一体化する構造としては、埋
込み半導体レーザと、ヘテロバイポーラトランジスタや
、半導体レーザとＭＩ　５ＦＥＴや、半導体レーザとＭ
ＥＳＦＲ：Ｔなどが提案されている。しかし、ＭＩ　５
ＦＥＴやＭＥＳＦＥＴは長波長光源用のＩｎＰ系材料の
場合困難である。また、埋込み半導体レーザとへチロバ
イポーラトランジスタの場合、特性上はよい結果が得ら
れているが、エピタキシャル成長を２回行彦う必要があ
り素子製作上不利である。Conventional configurations and their problems Structures that integrate a semiconductor laser and an electric element include a buried semiconductor laser and a hetero bipolar transistor, a semiconductor laser and an MI 5FET, and a semiconductor laser and an M
ESFR:T etc. have been proposed. However, MI 5
It is difficult to use InP-based materials for FETs and MESFETs for long wavelength light sources. In addition, in the case of a buried semiconductor laser and a heterobipolar transistor, although good results have been obtained in terms of characteristics, it is necessary to perform epitaxial growth twice, which is disadvantageous in terms of device fabrication.

第１図（ａ）〜（ｄ）にその製造プロセスを示す。第１
図（、）で、ＩｎＰ基板１上に、１回目のエピタキシャ
ル成長を行なう。１回目のエピタキシャル成長として活
性層２、クラッド層３、キャップ層４を連続成長する。The manufacturing process is shown in FIGS. 1(a) to 1(d). 1st
In the figure (,), first epitaxial growth is performed on an InP substrate 1. As a first epitaxial growth, an active layer 2, a cladding layer 3, and a cap layer 4 are successively grown.

この後エピタキシャル成長を中断した後、第１図（ｂ）
のように、レーザとなる部分のみを残し、他の部分を取
シ除く。次に第１図（Ｃ）に示すように、２回目のエピ
タキシャル成長として、レーザ部の光および電流をとじ
込めるだめの埋込み層とへテロバイポーラトランジスタ
形成層を兼ねて分離層６．コレクタ用の層６．ペース用
の層７、エミッタ用の層８を連続成長する。さらにＰ型
拡散領域９，１ｏを形成し、層６，７．８よりなるコレ
クタ、ベース、エミッタを形成し、第１図（ｄ）に示す
ようにトランジスタの電極１２　、１３゜１４、レーザ
の電極１６の形成を行なってヘテロバイポーラトランジ
スタを形成する。第１図では駆動回路とレーザの一体化
がなされ効率的な工程となっているが、１回目のエピタ
キシャル成長の後メサエッチングのプロセスが入る。こ
のようにエピタキシャル成長を２回に分けて行なうと歩
留りが低下し、このことが、この構造の欠点となってい
る。After stopping the epitaxial growth, Fig. 1(b)
Leave only the part that will become the laser and remove the other parts. Next, as shown in FIG. 1(C), as a second epitaxial growth, a separation layer 6. is formed which also serves as a buried layer for trapping light and current in the laser section and a hetero bipolar transistor formation layer. Layer for collector 6. A layer 7 for a paste and a layer 8 for an emitter are successively grown. Furthermore, P-type diffusion regions 9 and 1o are formed, and the collector, base and emitter consisting of layers 6 and 7.8 are formed, and as shown in FIG. Electrodes 16 are formed to form a hetero bipolar transistor. In FIG. 1, the driving circuit and laser are integrated, resulting in an efficient process, but a mesa etching process is performed after the first epitaxial growth. Performing the epitaxial growth in two steps in this manner reduces the yield, which is a drawback of this structure.

発明の目的 本発明は、半導体レーザと電気素子の一体化構造におい
て、製作の簡易な高歩留りの半導体装置を提供すること
を目的とする。OBJECTS OF THE INVENTION An object of the present invention is to provide a high-yield semiconductor device that is easy to manufacture and has an integrated structure of a semiconductor laser and an electric element.

発明の構成 半導体レーザと電気素子の一体化構造において、Ｔ　Ｓ
　（Ｔｅｒｒａｃｅｄ　５ｕｂｓｔｒａｔｅ　）型すな
わち段差基板型半導体レーザ上にさらにバイポーラトラ
ンジスタ用の各層を成長させることによシ、歩留りを向
上させた半導体装置である。またバイポーラトランジス
タをペテロ構造にすることにより、電流増幅率を向上さ
せた半導体装置である。ＴＳ型半導体レーザとは段差を
有する基体上に多層エピタキシャル成長を行ない。この
段差によって形成される段差還移領域に電流を流すこと
によって発振を行なわせる形のレーザ構造である。Structure of the Invention In the integrated structure of a semiconductor laser and an electric element, T S
This semiconductor device has an improved yield by growing layers for bipolar transistors on a (terraced five substrate) type semiconductor laser, that is, a stepped substrate type semiconductor laser. Furthermore, it is a semiconductor device in which the current amplification factor is improved by making the bipolar transistor into a Peter structure. A TS type semiconductor laser is a semiconductor laser in which multilayer epitaxial growth is performed on a substrate having steps. This is a laser structure in which oscillation is performed by passing a current through a step reduction region formed by this step.

実施例の説明 第２図に本発明の実施例の断面構造を示す。ｎ型ＩｎＰ
基板２１上に段差を形成した後、レーザＬ用のｎ　−Ｉ
ｎＰクラッド層２２、ＩｎＧａＡｓＰ活性層２３、ｐ−
ＩｎＰクラッド層２４を形成する。そして、連続的にバ
イポーラトランジスタＴ用のｎ　−ＩｎＰコレクタ用層
２６、ｐ−ＩｎＧａＡｓ＋Ｐベース用層２６、ｎ−Ｉｎ
Ｐエミッタ用層２７を連続的に形成した後、電気素子分
離拡散領域２８をｐ−ＩｎＰクラッド層２４まで形成す
る。これによシ分離拡散領域２８とｐ−ＩｎＰクラッド
層２４で囲まれた領域は電気的に分離され、複数の電気
素子を集積化できる。さらにレーザＬの電流注入用拡散
領域２９をｐ−クラッド層２４まで行なう。さらにベー
ス電極取り出し用拡散領域３ｏの形成を行なう。DESCRIPTION OF EMBODIMENTS FIG. 2 shows a cross-sectional structure of an embodiment of the present invention. n-type InP
After forming a step on the substrate 21, the n-I for the laser L is
nP cladding layer 22, InGaAsP active layer 23, p-
An InP cladding layer 24 is formed. Then, the n-InP collector layer 26 for the bipolar transistor T, the p-InGaAs+P base layer 26, the n-In
After continuously forming the P emitter layer 27, an electrical element isolation diffusion region 28 is formed up to the p-InP cladding layer 24. As a result, the region surrounded by the isolation diffusion region 28 and the p-InP cladding layer 24 is electrically isolated, and a plurality of electrical elements can be integrated. Furthermore, a diffusion region 29 for current injection of the laser L is formed up to the p-cladding layer 24. Furthermore, a diffusion region 3o for taking out the base electrode is formed.

さらに、半導体レーザとバイポーラトランジスタを分離
するだめの分離エツチングをｎ−ＩｎＰクラッド層２２
まで行って溝３６を形成する。この工程により、層２６
．２６．２７の一部よりなるコレクタ２５Ｃ，ベース２
６Ｂ、エミッタ２７Ｅが形成される。さらにコレクタ電
極取り出しエツチングを行なった後、エミッタ、コレク
タ、ベースおよびレーザ電極３１〜３４を形成する。Furthermore, the n-InP cladding layer 22 is etched to separate the semiconductor laser and the bipolar transistor.
to form the groove 36. This step results in layer 26
．． Collector 25C, base 2 consisting of part of 26.27
6B and an emitter 27E are formed. Further, after performing etching to take out the collector electrode, the emitter, collector, base, and laser electrodes 31 to 34 are formed.

なお第２図では段差の低い部分にトランジスタＴを形成
しているが、段差の高い部分に形成してもよい。Note that in FIG. 2, the transistor T is formed in a portion with a low step, but it may be formed in a portion with a high step.

なお、ここでは材料としてＩｎＰ、ＩｎＧａＡｓＰを用
いているが、ＧａＡｓ、Ａ４ＧａＡｓなど他の化合物半
導体でもよい。Note that although InP and InGaAsP are used as materials here, other compound semiconductors such as GaAs and A4GaAs may be used.

このようにこの構造を用いれば２２　、２３　、２４゜
２６．２６．２７の各層を連続的に１回のエピタキシャ
ル成長で製作できる。このように連続形成できることは
、エピタキシャル成長を２回にわけて１回目の成長と２
回目の成長の間に他の製作工程を必要とする従来の場合
よシ、はるかに高歩留りとなる。As described above, by using this structure, each layer of 22°, 23°, 24°, 26°, 26°, and 27° can be successively manufactured by one epitaxial growth. The fact that continuous formation is possible in this way means that epitaxial growth can be divided into two stages, the first growth and the second.
Yields are much higher than in the conventional case, which requires other fabrication steps between growths.

ｉた、バイポーラトランジスタのベース層２６をエミツ
タ層２７の禁制帯幅より小さい組成としているので、ト
ランジスタとしての電流増幅率を大きくできる。Additionally, since the base layer 26 of the bipolar transistor has a composition smaller than the forbidden band width of the emitter layer 27, the current amplification factor of the transistor can be increased.

なお、ベース層２６はｐ−ＩｎＰでもかまわない。Note that the base layer 26 may be made of p-InP.

発明の効果 本発明は、ＴＳ型半導体レーザとバイポーラトランジス
タを一体化することにより製作工程の簡単にし、高歩留
りとすることができる。特にバイポーラトランジスタを
ヘテロ接合バイポーラトランジスタとすることにより電
流増幅率を向上できる。Effects of the Invention According to the present invention, by integrating a TS type semiconductor laser and a bipolar transistor, the manufacturing process can be simplified and the yield can be increased. In particular, the current amplification factor can be improved by using a heterojunction bipolar transistor as the bipolar transistor.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（、）〜（ｄ）は従来のバイポーラトランジスタ
とレーザの製造工程図、第２図は本発明の一実施例のト
ランジスタとレーザの一体化断面構造図である。 ２１・・　ＩｎＰ基板、２２・・・・ｎ型１ｎＰクラッ
ド層、２３−・・活性層、２４・・−・・ｐ型ＩｎＰク
ラッド層、２５・・・・ｎ型ＩｎＰコレクタ用層、２６
・・・・ｐ型ＩｎＧａＡｇＰベース用層、２７　・＝　
−ｎ型ＩｎＰエミッタ用層、２８　・・分離拡散領域、
２９・・レーザ注入拡散領域、３０・・・・ベース拡散
、３６・・・・分離エツチング溝、３１〜３５・・電極
。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図1(a) to 1(d) are manufacturing process diagrams of a conventional bipolar transistor and laser, and FIG. 2 is a sectional view of an integrated transistor and laser according to an embodiment of the present invention. 21... InP substrate, 22... n-type 1nP cladding layer, 23-... active layer, 24... p-type InP cladding layer, 25... n-type InP collector layer, 26
... p-type InGaAgP base layer, 27 ・=
-n-type InP emitter layer, 28...separation diffusion region,
29... Laser injection diffusion region, 30... Base diffusion, 36... Separation etching groove, 31-35... Electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (2)

【特許請求の範囲】[Claims] （１）基板上に形成した階段上の段差と、前記段差上に
第１の導電型を有する第１のクラッド層、この第１のク
ラッド層上に形成された活性層、この活性層の上に形成
され第２の導電型を有する第２のクラッド層を有する半
導体レーザと、前記第２のクラッド層上に形成された第
１の導電型を有する第３の半導体層、前記第３の半導体
層上に形成された第２の導電型を有する第４の半導体層
、前記第４の半導体層上に形成された第１の導電型を有
する第５の半導体層を有するバイポーラトランジスタと
を備えたことを特徴とする半導体装置。(1) A step on a staircase formed on a substrate, a first cladding layer having a first conductivity type on the step, an active layer formed on the first cladding layer, and an active layer formed on the active layer. a semiconductor laser having a second cladding layer formed on the second cladding layer and having the second conductivity type; a third semiconductor layer having the first conductivity type formed on the second cladding layer; a bipolar transistor having a fourth semiconductor layer having a second conductivity type formed on the fourth semiconductor layer, and a fifth semiconductor layer having the first conductivity type formed on the fourth semiconductor layer. A semiconductor device characterized by: （２）第４の半導体層は、第３もしくは第４の半導体層
より小さな禁制帯幅を有することを特徴とする特許請求
の範囲第１項に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the fourth semiconductor layer has a smaller forbidden band width than the third or fourth semiconductor layer.
JP15436284A 1984-07-25 1984-07-25 Semiconductor device Pending JPS6132588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15436284A JPS6132588A (en) 1984-07-25 1984-07-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15436284A JPS6132588A (en) 1984-07-25 1984-07-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6132588A true JPS6132588A (en) 1986-02-15

Family

ID=15582496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15436284A Pending JPS6132588A (en) 1984-07-25 1984-07-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6132588A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487192A2 (en) * 1990-11-19 1992-05-27 Mitsubishi Denki Kabushiki Kaisha Opto-electronic integrated circuit having a transmitter of long wavelength
JPH06283829A (en) * 1993-12-30 1994-10-07 Sony Corp Shielded signal line

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487192A2 (en) * 1990-11-19 1992-05-27 Mitsubishi Denki Kabushiki Kaisha Opto-electronic integrated circuit having a transmitter of long wavelength
US5311046A (en) * 1990-11-19 1994-05-10 Mitsubishi Denki Kabushiki Kaisha Long wavelength transmitter opto-electronic integrated circuit
JPH06283829A (en) * 1993-12-30 1994-10-07 Sony Corp Shielded signal line

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