JPS6132567A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To capture a small number of unnecessary carriers intruding into a pore type capacitance element sufficiently by constituting a carrier capture region up to depth in the same extent as the bottom of the pore type capacitance element. CONSTITUTION:An n<-> type well region 9 is formed to a predetermined main surface section in a peripheral circuit region 6 in a substrate 1, and used for shaping a MISFET with p<+> type source region 25 and drain region 25. An n<-> type semiconductor region 10 is employed for constituting a carrier capture region 8, and depth up to a bottom from a main surface thereof is shaped in depth in the same extent as the well region 9. The carrier capture region 8 is constituted by the semiconductor region 10 and an n<+> type semiconductor region. A space between the semiconductor region 10 and a capacitance element C in the peripheral section of a memory cell array 2 is separated at a value approximating a space between the capacitance element C formed at the central section of the memory cell array 2 and a capacitance element C adjacent to said capacitance element C. The space prevents an intrusion into the capacitance element C of a small number of unnecessary carriers captured by the carrier capture region 8.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as ZC).
The present invention relates to a technique that is effective when applied to a dynamic random access memory (hereinafter referred to as a DRAM).

[Background technology] A DRAM memory cell is a semiconductor substrate (hereinafter referred to as a semiconductor substrate).

The shadow W of unnecessary minority carriers existing in the substrate
receive.

It has been proposed to form a carrier trapping region for trapping unnecessary minority carriers in the periphery of a memory cell array (Japanese Unexamined Patent Publication No. 58-63939).

On the other hand, in order to improve the degree of integration of DRΔM, holes extending inward from the main surface of the substrate (hereinafter referred to as pores) are formed, and the pores are used to form capacitive elements of memory cells (hereinafter referred to as pore-type capacitive elements). There is a composition (4., 1984-
]2739 publication).

The inventors of the present invention discovered a problem that the carrier trapping region proposed above cannot sufficiently trap unnecessary minority carriers that enter the pore-type capacitive element.

The above problem arises due to the following reasons.

The carrier trapping region V1 is formed to a depth of about 0.3 to 064 [μm] from the main surface of the substrate using the process of forming the source region and drain region of the MISFET.

Therefore, the carrier trapping region cannot trap unnecessary minority carriers generated at a depth of about 3 to 5 [μm].

[Objective of the Invention] An object of the present invention is to provide technical means capable of sufficiently capturing unnecessary minority carriers that enter a pore-type capacitive element.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

By configuring the carrier trapping region to a depth comparable to the bottom of the pore type capacitive element, unnecessary minority carriers can be sufficiently captured.

The configuration of the present invention will be explained below along with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

Furthermore, in the cross-sectional view, the insulating film provided between each conductive layer is not shown in order to make it easier to see the configuration of the main parts of the IC.

[Example I] Figure 1 shows an example of the present invention! FIG. 2 is an equivalent circuit diagram of a memory cell array of a folded pin 1-line type DRAM for explaining.

In FIG. 1, SA and SA st are sense amplifiers, and a pair of bit lines B L 1t and BLI2 or BL2+ and BL 2□ (hereinafter referred to as , the direction in which the bit lines extend is called the row direction).

Qs I and Qs 2 are MTS FE for short circuit
T, and one end of it is P1- wire BL+ J or BL
21, and the other end is connected to bit line BL12 or BL
22, and by setting the gate electrode to a high potential (Vcc) by the word line WLs, the bit line BL
Short-circuit +r and BL12 or bit lines BL21 and BL22 to connect bit lines BE, +t and BLI2 or BL
The potentials of 21, BL, and 22 are set to about half of the high potential (Vcc).

The potential that is about half of the high potential (Vcc) becomes a reference level potential when the sense amplifiers S A + and S A 2 read out electrical signals.

MIj, MI2. Mts, M21, M22 and M23
are memory cells, respectively, and store information written to the DRAM. Memo'J f! /! /
M is MISFET Q+ s, Q+ 2 , Q.

3.Q21. Q22 and Q23 and capacitive element CIj+
CI2. Cr2. It consists of a series circuit with C21, C22 and C23. The MISFETQ has one end connected to the bit line BL and a gate electrode connected to the word line WL. One end of capacitive element C is MI 5FET
Q, and the other end is connected to a high potential (Vcc) power supply terminal.

Next, the layout of the memory cell array, sense amplifier region, carrier capture region, etc. in the DRAM of this embodiment will be explained.

FIG. 5 is a plan view for explaining the layerer 1- of the DRAM of this embodiment.

In FIG. 5, reference numeral 1 denotes a substrate made of P-type silicon single crystal. Reference numeral 2 denotes a memory cell array, which is partitioned and provided on a predetermined main surface of the substrate 1, and has a plurality of memory cells M arranged therein.

Reference numeral 3 denotes a word line selection circuit area, which is provided on the main surface between the memory cell arrays 2 on the substrate l, and is connected to the word lines WL,
A plurality of word line selection circuits are arranged to select the word line W L s, and an operation circuit is arranged to set the word line W L s to a high potential (Vcc).

Reference numeral 4 denotes a bit line selection circuit area, which is provided on the main surface of the memory cell array 2 on the substrate 1 in a different area from the above, and has a plurality of bit line selection circuits for selecting the bit lines BL.

Reference numeral 5 denotes a sense amplifier region, which is provided on the main surface of the outer periphery of the memory cell array 2 of the substrate 1, in which a plurality of sense amplifiers SA are arranged.

6 is a peripheral circuit area, which includes memory cell array 2 on substrate 1;
There are steps on the main surface of the outer periphery, and an input cover sofa circuit, an output buffer circuit, a main amplifier circuit, etc. are provided. Reference numeral 7 denotes a bonding pad, which is arranged in multiple stages on the outer periphery of the substrate 1. 8 is a carrier capture area, which includes the memory cell array 2, the word line selection circuit area 3, the bit line selection circuit area 4, the sense amplifier area 5, and the peripheral circuit area 6.
It is set up between. The carrier capture region 8 captures unnecessary minority carriers that enter from the outer periphery of the memory cell array 2 of the substrate 1 into the memory cell array 2, and captures unnecessary minority carriers that become the information stored in the capacitive element C constituting the memory cell M. This is to alleviate the decrease caused by the intrusion of carriers.

Next, the specific structure of this embodiment will be explained using FIGS. 2 to 4.

2A is a cross-sectional view taken along the nA-mA cutting line in FIG. 3, FIG. 3 is a plan view showing the main part of the memory cell array in FIG. 5, and FIG. 2B is the peripheral circuit in FIG. 5. FIG. 4 is a sectional view showing a main part of region 6, and is a sectional view taken along the line mV-IV in FIG. 3.

In FIGS. 2 to 4, reference numeral 9 denotes an n-type well region, which is provided on a predetermined main surface of the peripheral circuit region 6 (FIG. 5) of the substrate 1, and includes a P+-type source region 25 and a drain region. It is used to form a MISFET equipped with 25. The well region 9 is formed, for example, after selectively forming a mask for impurity introduction on the upper part of the substrate l.
N-type impurity (phosphorus) was added to 4×10”2 using ion implantation technology with an energy of about 125 [k e y].
The n-type impurity is introduced into the main surface of the substrate 1 at a dose of about [atoms/cd], and the n-type impurity is
It is formed by diffusing into the inside of the substrate l using a thermal diffusion technique of 20.0 ['C]. The depth from the main surface of the well region 9 to its bottom is approximately 3 to 4 [μm]. The mask for impurity introduction is, for example, a silicon oxide film formed by oxidizing the surface of the substrate 1 by thermal oxidation technology, and a nitride film formed on top of the silicon oxide film by chemical vapor deposition technology (hereinafter referred to as CVD technology). using a membrane.

lO is an n-type semiconductor region, and carrier trapping region 8
It is for configuring. In order to eliminate the need for a dedicated manufacturing process for forming the semiconductor region 10,
It is formed by the same manufacturing process as that for forming the well region 9. Therefore, the depth of the semiconductor region IO from its main surface to the bottom is 3 to 4 [μm] like the well region 9.
] to a depth of approximately The semiconductor region 10 is formed to have a width of approximately 6 to 7 [μm]. The carrier trapping region 8 includes a semiconductor region 10 and an n+ type semiconductor region 2.
It consists of B. As shown in FIG. 3, the semiconductor region 28 is the semiconductor region 10 at the corner of the memory cell array 2.
Formed on the main surface of.

Furthermore, a depletion layer is generated at the junction between the substrate 1 and the semiconductor region 10. This depletion layer is formed in the semiconductor region 10 at a power supply type (
Vcc) was applied.

On the other hand, the distance between the semiconductor region 10 and the capacitive element C in the peripheral part of the memory cell array 2 is as follows:
Separate the distance between the two.

The purpose of the interval is to prevent unnecessary minority carriers captured by the carrier trapping region 8 from entering the capacitive element C, and also to prevent the carrier trapping region 8 from absorbing charges accumulated in the capacitive element C. be.

Further, the semiconductor region 10 and the MIS provided outside the semiconductor region 10
FETs, particularly MISFETs each having a source region and a drain region made of an n+ type semiconductor region, are also spaced apart from each other by about the same distance as the capacitive elements C provided in the center of the memory cell array 2. As described above, the semiconductor region 10 and the MISFET are separated from each other by the semiconductor region 1.
This is to prevent unnecessary leakage current from flowing between the MTSFET and the MTSFET.

Reference numeral 11 denotes a channel stopper region, which is provided on a predetermined main surface under the field insulating film 12 of the substrate
It consists of a type semiconductor region or a P+ type semiconductor region. Note that the n+ type channel stopper region 11 does not necessarily need to be provided.

The field insulating film 12 is a silicon oxide film formed by oxidizing the surface of the substrate 1 using a thermal oxidation technique.

The semiconductor region l is formed using the manufacturing process for forming the well region 9.
Since the upper surface of O is formed flat, the upper surface of field isolation 1# film 12 above it can be formed flat. Therefore, the conductive layer provided above the field insulating film 12 and the insulating film can be formed by planarizing them.

13 is a pore formed in a predetermined main surface of the memory cell array 2; an insulating film 14 provided to cover the entire inner wall of the pore 13; and a conductive layer 1 provided to fill the inside of the pore 13.
5 and the substrate 1 form a capacitive element C. By applying a fixed potential, for example, a power supply potential (Vcc) to the conductive layer 15, the substrate 1 is removed from the interface between the insulating film 14 and the substrate 1.
A depletion layer is formed that extends inside.

The pores 13 are formed by selectively etching the main surface of the substrate 1 using anisotropic etching technology, so that the depth from the main surface of the substrate 1 to the bottom of the pores 13 is approximately 3 to 5 μm. Form it so that it becomes.

The insulating film 14 is, for example, a silicon oxide film formed by oxidizing the inner wall of the pore 13 using a thermal oxidation technique, and has a film thickness of 300 angstroms (hereinafter referred to as below).

[A]). Or pore 13
A silicon oxide film of about 100 [A] is formed by thermal oxidation on the inner wall of the silicon oxide film, a silicon nitride film of about 120 [A] is formed by CVD technology to cover the silicon oxide film, and then a silicon nitride film of about 120 [A] is formed by thermal oxidation technology. The insulating film 14 is formed by forming a silicon oxide film of about 30 [A] by oxidizing the nitride film. The conductive layer 15 is made of C
After a polycrystalline silicon layer is formed by VD technology so as to be buried in the pores 13, unnecessary portions of the polycrystalline silicon layer are selectively removed so that the upper surface thereof becomes flat.

By forming the gearia capture region 8 with the semiconductor region IO and the depletion layer, the depletion layer captures unnecessary minority carriers generated at a depth of about 4 to 5 [μm] from the main surface of the substrate 1. can. Therefore, the pore type capacitive element C
It is possible to reduce unnecessary minority carriers that enter the depletion layer that constitutes the . In particular, it is possible to reduce unnecessary minority carriers that enter the depletion layer of the pore-type capacitive element C that constitutes the memory cells in the peripheral part of the memory cell array 2. As a result, the amount of charge, which is information stored in the pore type capacitive element C, is
Since changes due to the intrusion of unnecessary minority carriers can be alleviated, the time during which the pore type capacitive element C can retain the amount of charge, that is, the information retention time can be improved.

Reference numeral 16 denotes a conductive layer, which is electrically connected to the conductive layer 15 and provided above the field isolation I# film 12 of the memory cell array 2, and is a MISF (described later) constituting the memory cell M.
A hole is provided above the main surface of the substrate 1 on which the ETQ is provided. The conductive layer 16 is supplied with a high potential (
Vcc) and is used to apply a high potential to the conductive layer 15. The conductive layer 16 is, for example, +i, cV
A polycrystalline silicon layer made using the D technology is formed to a thickness of approximately 6000 to 8000 [Δ] so as to cover the entire surface of the -L portion of the substrate. Impurities to 1020 [atoms/C11f,]
After introducing the polycrystalline silicon layer, unnecessary portions of the polycrystalline silicon layer are selectively removed.

An insulating film 17 is provided on the conductive layer 16 so as to cover it, and insulates the conductive layer 16 from a conductive layer to be described later which is used as a gate electrode or word line WL of the MISFET.

The insulating film 17 is a silicon oxide film obtained by oxidizing the conductive layer 16 by thermal oxidation technology, and the film thickness is 30 mm.
00 to 4000[A1]. By forming the insulating film 17, the final film thickness of the conductive layer 16 is 4.
It will be about 000 to 5000 [A].

Reference numeral 18 denotes an insulating film, which is used as a gate insulating film, an n+ type semiconductor region 19 used as a source region or a drain region, a conductive layer 20 used as a gate electrode, and a MISFET of the memory cell M (Q in FIG. 1).
). The insulating film 18 is a silicon oxide film obtained by oxidizing the surface of the substrate 1 by thermal oxidation technology, and is formed to have a thickness of about 300 [A1].

The semiconductor region 19 is formed by introducing n-type impurities into the main surface of the substrate l by ion implantation using the conductive layer 20 as a mask for impurity introduction.

The conductive layer 20 is formed using a polycrystalline silicon layer formed by CVD technology. After forming the polycrystalline silicon layer to a thickness of about 3000 to 4000 [A] on the upper part of the substrate l, covering the insulating films 17 and 18, an insulating layer is formed. Predetermined upper portions of membranes 17 and 18 are
As shown in the figure, unnecessary portions of the polycrystalline silicon layer are selectively removed so as to extend in the column direction. or.

A polycrystalline silicon layer with a thickness of about 2000 [A1] is formed by CVD technology, and a molybdenum silicide layer with a thickness of 2000 to 3000 [A1] is formed by sputtering technology on top of the polycrystalline silicon film.
[The polycrystalline silicon layer and the molybdenum silicide layer are selectively removed as described above,
A conductive layer 20 is formed. Conductive layer 20 is used as word line WL.

Reference numeral 21 denotes an insulating film, which is used as a gate insulating film, and includes a source region and a drain region consisting of an n' type semiconductor region 22 provided in a pattern as shown in FIG.
Together with the conductive layer 23 used as a gate electrode, it constitutes a short circuit MISFETQs. The insulating film 21, the semiconductor region 22 and the conductive layer 23 are
They are formed by the same manufacturing process as that for forming the insulating film 18, the semiconductor region 19, or the conductive layer 20, respectively.

The shorting MISFETQs is in a conductive state, that is.

When carriers are moving from the source region to the drain region, the carriers are rapidly accelerated by the electric field near the drain and have large energy (become so-called hot electrons). MISFE for short circuit by carrier with its large energy
Silicon atoms in the channel region of T are excited, thereby generating unnecessary minority carriers. The unnecessary minority carriers enter the inside of the memory cell array 2, but since the semiconductor region 10 is used and the carrier trapping region 8 is provided at the outer periphery of the memory cell array 2, the intrusion of unnecessary minority carriers can be sufficiently reduced. .

Reference numeral 24 denotes an insulating film, which is used as a gate insulating film and is provided in the peripheral circuit region 6 together with a p-type semiconductor region 25 used as a source region or a drain region and a conductive layer 26 used as a gate electrode. Complementary MI
It constitutes an SFET (hereinafter referred to as CMISFET).

The insulating film 24 and the conductive layer 26 are formed by the same manufacturing process as the process of forming the insulating film 1B or the conductive layer 20, respectively. The semiconductor region 25 is formed by introducing a p-type impurity, such as boron, into the main surface of the peripheral circuit region 6 of the substrate 1 by ion implantation using the conductive layer 26 as a mask for impurity introduction.

An insulating film 27 is provided over the insulating films 17, 18, 21, 24 and the field insulating film 12, covering the conductive layers 20, 23 and 26.

The insulating film 27 is formed using, for example, a silicon oxide film formed by CVD technology, and has a thickness of about 6000 to 8000 [Δ].

Reference numeral 28 denotes a II' type semiconductor region, which is formed in a pattern as shown in FIG.
electrically connected to 0. The semiconductor region 28 is applied to the semiconductor region 10 at a potential higher than the reference potential of the IC, for example, 5.0 [V].
This is used to apply the power supply potential (VcC) of . Further, the semiconductor region 28 has a carrier trapping region 8
It is also used to collect unnecessary minority carriers captured by the semiconductor region IO.

Semiconductor region 28 is formed by the same manufacturing process as that for forming semiconductor region 19 in order to eliminate the need for a dedicated manufacturing process for forming it.

A conductive layer 31 is electrically connected to a predetermined semiconductor region 19 or 22 through a connection hole 32 formed by selectively removing the insulating films 1B, 21, and 27, and is electrically connected to a predetermined semiconductor region 19 or 22.
A predetermined upper part of the pin 7 is provided extending in the row direction, and is used as the pin 1-line BL. The conductive layer 31 is, for example,
Using an aluminum layer or an aluminum layer containing silicon by vapor deposition technology, the film thickness is between 6000 and 80 mm.
00 [A] approximately. The conductive layer 30 is formed by the same manufacturing process as the process of forming the conductive layer 31.

A conductive layer 33 is provided extending over the insulating film 27. The conductive layer 33A has one end connected to a predetermined semiconductor region 25 through a connection hole 34 formed by selectively removing the insulating films 24 and 27, and the other end connected to a high potential (Vcc).
Connect to the power terminal of the The conductive layer 33B has one end connected to a predetermined semiconductor region 2 through a contact hole 34 different from the above-mentioned one.
5, and the other end is connected to an n+ type semiconductor region used as a source region or drain region of another MISFET (not shown). The conductive layer 33 is formed by the same manufacturing process as the process of forming the conductive layer 31.

35 is an insulating film, and conductive layers 30, 31, and 33 are
1 is provided on top of the insulating film 27, and conductive layers 30 and 31
and 33 as a protective film.

[Example TI] FIG. 7 is a plan view showing the main part of the peripheral part of the memory cell array 2 of FIG. 5 in order to explain Example 2, and FIG. FIG. 3 is a cross-sectional view taken along a cutting line.

In FIGS. 6 and 7, an n+ type semiconductor region 36
is provided extending from a predetermined main surface portion of the semiconductor region IO,
Further, a predetermined portion thereof is electrically connected to a conductive layer 30 through a connection hole 29 as in Example I. Semiconductor region 36
is for applying a power supply potential higher than the reference potential of the IC, for example, 5.0 [V], to the semiconductor region 10 in a good manner.

As the distance from the connection between the conductive layer 30 and the semiconductor region 1O increases, the potential of the semiconductor region 1o becomes lower than the power supply potential (Vcc). This potential drop is due to a potential drop inside the semiconductor region 10. In order to reduce this potential drop, the present embodiment is characterized in that a semiconductor region 36 having an extremely high impurity concentration for low resistance is provided inside the semiconductor region IO. Since the resistance value of the semiconductor region 36 is negligibly small compared to the resistance value of the semiconductor region 1O, the high potential supplied by the conductive layer 30 can be applied to the semiconductor region 10 approximately evenly. Therefore, unnecessary minority carriers can be captured favorably even in the carrier capture region 8 that is far from the connection portion between the semiconductor region 10 and the conductive layer 30.

Further, the semiconductor region 36 is used as a transmission path for transporting unnecessary minority carriers captured by the carrier capture region 8 to the outside of the substrate l.

The semiconductor region 36 is formed by the manufacturing method described in His Holiness.

In the thermal oxidation process for forming the field insulating film 12 after forming the well region 9, the semiconductor region 10, and the channel stopper region 11, the main surface of the substrate 1 where the semiconductor region 36 is to be provided is oxidized. Then, the pores 13, the insulating film 14, the conductive layers 15, 16, the insulating film 17, the insulating films 18, 24, and the conductive layers 20, 23, and 26 are sequentially formed as in Examples 1 and 18]. Next, in order to eliminate the need for a dedicated manufacturing process for forming semiconductor region 36, semiconductor region 36 is formed using the same manufacturing process as that for forming semiconductor regions 19 and 22.

[Example ■] In this Example ■, a conductive layer (hereinafter referred to as conductive layer I) extending in the column direction and the row direction is provided above the semiconductor region 36 of Example ■ so as to surround the memory cell array 2. This is an example. Therefore, Example (2) will be explained using FIGS. 6 and 7, which were used to explain Example (2).

The conductive layer I is formed by the manufacturing process for forming the conductive layers 30, 31, and 33 of Example 2 before forming these conductive layers. That is, the conductive layer I is formed using, for example, an aluminum layer formed by vapor deposition or an aluminum layer containing silicon (with a film thickness of 6000 to 800 nm).
0 [A] Degree number - Form. Conductive layer I in semiconductor region 36
is formed by selectively removing the insulating films 18 and 27, and is electrically connected through the contact hole. On the side of the connection hole, a plurality of conductive layers 20 are formed between the conductive layers 20 in the part where the conductive layer 1 extends in the row direction, and a plurality of conductive layers 20 are formed at regular intervals in the part where the conductive layer 1 extends in the direction. Form. After forming the conductive layer r, an insulating film 35 is formed, and then the conductive layers 30 and 3 are formed.
1 and 33.

The conductive layer 30 is connected to the conductive layer I through a connection hole formed by selectively removing the inside of the insulating film 35. The connection hole Mf is formed at a corner of the conductive layer I, for example.

Next, an insulating film covering the conductive WIs 30 and 31 is formed. This insulating film is formed using, for example, a silicon oxide film produced by CVD technique 1, and has a thickness of about 10,000 [Δ].

By forming the conductive layer (2), the resistance value of the conductive layer I is smaller than the resistance value of the semiconductor region 36 (v).

A potential higher than the reference potential of the IC is applied to the semiconductor region 10, for example, 5.0. [V] Good power supply potential (vCC) t: +:p
Can be added. Further, since a plurality of connection holes between the conductive layer 1 and the semiconductor region 36, that is, a plurality of connection holes, are provided, the high potential can be applied to the semiconductor region 10 very well.

[Example ■] Example ■ is an example in which the impurity concentration of the semiconductor region 10 is higher than that of the well region 9 in Example ■. Therefore, Example 2 will be explained using FIG. 2A used to explain Example I.

The well region 9 is 4×10” [ato
It is formed by introducing an n-type impurity of about 100 ms/c.

The semiconductor region 10 is formed using n-type impurities of, for example, 4×10”j[a t orns/cn
f].

Impurities for forming well region 9 and semiconductor region 1
The 11-type impurities for forming 0 and 11-type impurities are introduced into the main surface of the substrate 1 through different ion injection processes. Then, the r1 type impurity is diffused into the substrate l using the same thermal diffusion process.

Since the concentration of type II impurities inside the semiconductor region 10 is increased, the resistance value of the semiconductor region 10 can be reduced. Furthermore, a depletion layer extending from the semiconductor region 10 is formed deep within the base #i1. Therefore, carrier capture area 8
is larger than the carrier trapping region 8 formed by the semiconductor region IO having the same impurity concentration as the well region 9.
Unnecessary minority carriers generated deep in the substrate 1 can be captured.

[Embodiment V] Another embodiment (■) of the present invention is an MIS constituting a memory cell.
A carrier trapping region of a DRAM in which the source region and drain region of an FET are made of p+ semiconductor regions will be described.

The substrate of Example 2 (hereinafter referred to as substrate V) is of n-type. ρ− on the main surface of the outer periphery of the memory cell array on the substrate ■
1' of Example I.

A layerer 1 similar to the conductor region 10 is formed. , the semiconductor region (■) is a vertical area provided on the main surface around the substrate (■).
II!, which is formed by the same manufacturing process as that for forming the well region of the mold (hereinafter referred to as well region ①)). l'
: The conductor region (2) and the well region (2) are formed by introducing a T) type impurity, for example, boron, into the main surface of the substrate (2) and then diffusing the P type impurity into the substrate (2) using thermal diffusion technology. do. The P-type impurity is 4
The +21'-conductor region V introduced into the substrate ■ with a dose of about 012 [a+ o m s / t:nf ] is
Similar to the well region (■), the area is 3 to 4 [μ
Form to a depth of about 1.0 ml. Similar to the semiconductor region 28 of Example I, the semiconductor region (2) is a P-type semiconductor region (hereinafter referred to as a semiconductor region Vp) on the main surface of the corner of the memory cell array.
). The semiconductor region VP is connected to the conductive layer through a connection hole formed by selectively removing the insulating film in the 4 part 1], and the conductive layer is connected to the reference potential of the IC (for example, O [V]). Connecting 1. Note that a high potential (for example, 5.0 [V]) is applied to the substrate (2).

The semiconductor region (2) forms a carrier trapping region together with the semiconductor region vp.

The capacitive element C constituting the memory cell M is constructed using pores as in Example I. The conductive layer provided inside the pores is
Connect to a conductive layer at low potential (eg, O[V]).

1. The carrier trapping region traps unnecessary minority carriers (holes) in the substrate V. To reduce unnecessary minority carriers entering a memory cell array.

[Embodiment (2)] FIG. 8 is a plan view of the DR and AM for explaining the second embodiment (2).

In FIG. 8, 37 is a substrate bias circuit, which is provided in a predetermined part of the peripheral circuit area 6, and applies a negative potential to the substrate 1, for example, -2.5 to -3.0 [V]. It is for applying.

The carrier capture region 8A is the substrate bias circuit 3 of the substrate 1.
7 is provided on the outer periphery of the substrate bias circuit, especially this Jl
This is to capture unnecessary minority carriers injected into the substrate 1 from the rectifier circuits of .

The carrier capture area 8A has the same structure as the carrier capture area 8' described in Example 2 or Example II. Therefore, although not shown, the carrier trapping region 8A has a potential higher than the reference potential of the IC, for example, 5.0
It is connected to the power supply potential of [V]. By providing the carrier trapping region 8A close to and surrounding the substrate bias circuit 37, unnecessary minority carriers injected into the substrate 1 from the substrate bias circuit 37 can be captured well. The unnecessary minority carriers are isotropically diffused into the substrate 1 from the substrate bias circuit 37, and penetrate deeper into the substrate 1 as they move away from the JA plate bias circuit 37. Therefore, the closer the gear capture region 8A is to the substrate bias circuit region 37, the better the unnecessary minority carriers generated therefrom can be captured.

[Embodiment (2)] Another embodiment (2) of the present invention will be described with reference to FIG. 9. FIG. 9 is a plan view of a DRAM for explaining this embodiment (2).

The carrier trapping region 8B is provided on the outer periphery of the substrate bias circuit 37, except for the portion of the carrier trapping region 8A on the side of the bonding pad 7 described in Example (2). Injected into the inside of the substrate 1 from the substrate bias circuit 37,
Unnecessary minority carriers that diffuse toward the bonding pad 7 side do not affect the pore type capacitive element C. therefore.

The carrier trapping region 8B is not provided on the side of the bonding pad 7 of the substrate bias circuit 37.

The carrier capture region 8C is provided so as to surround the outer periphery of the memory cell array 2 and the bit line selection circuit region 5.

Unnecessary minority carriers entering the inside of the memory cell array 2 can be reduced by the carrier trapping region 8C.

[Embodiment (2)] Another embodiment (2) of the present invention will be described using FIG. 10.

FIG. 10 is a plan view of a DRAM for explaining the present embodiment (2).

In the DRAM of this embodiment (2), the sense amplifier region 5 is provided between the memory cell array 2 and the bit line selection circuit region 4.

As shown in FIG. 1O, the carrier capture region 8D is designed to shield the memory cell array 2 which is closer to the peripheral circuit region 6 where the substrate bias circuit 37 is provided from the sense amplifier region 5 and the peripheral circuit region 6. It is provided for.

The carrier trapping region 8D particularly reduces unnecessary minority carriers generated from the substrate bias circuit 37 and entering the memory cell array 2.

Further, the carrier trapping region 8D provided between the memory cell array 2 and the sense amplifier region 5 prevents unnecessary minority carriers generated by operating the sense amplifiers from entering the memory cell array 2. In DR, AM, which uses a dummy cell to read out information written in a memory cell, minority carriers are injected into the substrate from the capacitive element constituting the dummy cell.

The minority carrier becomes an unnecessary minority carrier, and D
Since this may cause rough 1 to errors in the RAM, in a DRAM equipped with dummy cells, the dummy cells are provided between the carrier capture region 8D and the sense amplifier region 5.

The carrier trapping region 8D reduces unnecessary minority carriers injected from the capacitive elements constituting the dummy cells from entering the memory cell array 2.

"Example 2" Another example 2 of the present invention will be described with reference to FIG. 11.

FIG. 11 is a plan view of the DRAM for explaining the doctor of this embodiment.

In FIG. 11, the carrier trapping region 8E is provided at the outer periphery of each of the sense amplifier region 5 and the word line selection circuit region 3, and is also provided between the peripheral circuit region 6 and the memory cell array 2. It is. Carrier capture area 8
E captures unnecessary minority carriers generated from the peripheral circuit region 6, sense amplifier region 5, and word line selection circuit region 3. Unnecessary minority carriers generated from the bit line selection circuit region 4 are captured by the carrier capture region 8E at the outer periphery of the sense amplifier region 5. The unnecessary minority carriers are generated primarily from the channel region of the MTSFET by operating the MISFET provided in the peripheral circuit region 6 and the like.

By providing the carrier trapping region 8E, unnecessary minority carriers entering the memory cell array 2 can be reduced.

[Example X] Another Example X of the present invention will be described using FIG. 12.

FIG. 12 is a plan view of a DRAM for explaining the first embodiment.

In FIG. 12, the carrier capture area 8F is.

It is provided in a U-shape on the outer periphery of the memory cell array 2.

The carrier capture region 8F is not intended to be limited to a U-shape, but to shield the memory cell array 2 from the peripheral circuit region 6, sense amplifier region 5, word line selection circuit region 3, and bit line selection circuit region 4. That's fine.

The carrier trapping regions 8B, 8C18D, 8E, and 8F of Examples (2), (2), (2), and X are configured similarly to the carrier trapping region 8 of Example I.

Alternatively, the carrier trapping regions 8B, 8C18D, 8E, and 8F are configured in the same manner as the carrier trapping region 8 of Example (2).

[Effects] According to the novel technical means disclosed in the present application, the following effects can be obtained.

(1) 3 to 4 [ILm] on the outer periphery of the memory cell array
A semiconductor region having a depth of approximately can sufficiently capture unnecessary minority carriers generated in the range from the main surface of the substrate to the depth of the pores constituting the pore-type capacitor, so that they do not invade the pore-type capacitor. Unnecessary minority carriers can be reduced.

(2) Due to the above (1), it is possible to reduce the change in the amount of charge that becomes the information stored in the pore type capacitor, thereby improving the time from writing to rewriting information, the so-called refresh time. be able to.

(3) According to (2) above, the frequency of rewriting information written to DRAM can be reduced, so the time required for comprehensive rewriting is reduced, and therefore,
The effective operating speed of DRAM can be improved.

Hereinafter, the present invention has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. .

For example, in the present invention, an insulating film is provided on the main surface of the substrate,
A flat conductive layer provided with a high potential (V
cc) and a depletion layer formed on the main surface of the substrate below the capacitive element, and a MISFET.
Needless to say, it is extremely effective if applied to a DRAM equipped with a memory cell consisting of a series circuit with the following.

[Brief explanation of the drawing]

1 is an equivalent circuit diagram of a DRAM memory cell array, FIG. 2A is a sectional view taken along the HA-HA line in FIG. 3, and FIG. 2B is a main part of the peripheral circuit area in FIG. A sectional view shown. 3 is a cross-sectional view showing a main part of the peripheral part of the memory cell array of FIG. 5 in order to explain Example I; FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3; FIG. 5 is a plan view for explaining the I-no-out of the DRAM of Example (2), FIG. 6 is a cross-sectional view taken along the Vl-Vl cutting line in FIG. 7, and FIG. 7 is for explaining Example (2). 5, FIG. 8 is a plan view of a 1'l RAM for explaining embodiment (2) of the present invention, and FIG. DRA for explaining embodiment ■ of the invention
FIG. 10 is a plan view of M, and FIG.
FIG. 11 is a plan view of the DRA for explaining the embodiment ① of the present invention.
FIG. 12 is a plan view of DRA M for explaining Embodiment X of the present invention.
FIG. 1. Substrate, 2.. Memory cell array, 3.. Word line selection circuit area, 4. Bit line selection circuit area, 5..
Sense amplifier area, 6... Peripheral circuit area, 7... Ponding pad, 8.8A, 8B, 8C18D, 8E
and 8F...carrier capture region, 9...well region, 10...semiconductor region, 11...channel stopper region, 12...field insulating film, 13...pore, 1
4.17.18.21.24.27 and 35... Insulating film, i 5.16.20.23.26.30°31 and 33... Conductive layer, 19.22.25, 28 and 3
6. Semiconductor region, 29.32 and 34... connection hole,
37...Substrate bias circuit. Figure 4 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1. A memory cell array provided on a semiconductor substrate of a first conductivity type, a well region provided on a main surface portion of the semiconductor substrate separated from the memory cell array, and an outer peripheral portion of the memory cell array on the semiconductor substrate. a carrier trapping region provided on at least a part of the main surface of the semiconductor integrated circuit device, wherein the carrier trapping region has a depth comparable to that of the well region and is of a second conductivity type. A semiconductor integrated circuit device configured using a semiconductor region. 2. The memory cell array is constructed by forming a plurality of memory cells each consisting of a series circuit of an insulated gate field effect transistor and a capacitive element on the semiconductor substrate. The semiconductor integrated circuit device described above. 3. The capacitive element includes an insulating film provided in contact with the main surface of the semiconductor substrate, a conductive layer provided on the insulating film, and a conductive layer provided on the semiconductor substrate from the boundary between the semiconductor substrate and the insulating film. 3. The semiconductor integrated circuit device according to claim 2, further comprising a depletion layer formed inside. 4. The capacitive element includes a pore formed extending inward from the main surface of the semiconductor substrate, an insulating film covering the inner wall of the pore, and an insulating film embedded in the pore. 3. The semiconductor integrated circuit device according to claim 2, further comprising: a conductive layer formed by the insulating film, and a depletion layer formed inside the semiconductor substrate from an interface between the insulating film and the semiconductor substrate.