JPS61156860A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive the increase in integration and the improvement in reliability by a method wherein a means of preventing the diffusion of electrons is provided around a diffused layer which is the output terminal of a substrate bias generation circuit. CONSTITUTION:The titled device is provided with a groove 6 in a substrate 1 as the means of preventing the diffusion of electrons, so that it may surround an n<+> type layer 5 which is the output terminal of the substrate bias generation circuit 4. Setting the depth of the groove 6 at a suitable value makes the groove 6 serve as a barrier against the diffusion of electrons injected out of the n<+> type layer 5 into the substrate 1. As a result, they are effectively prevented from reaching a diffused electron memory cell array region 9 in the substrate. In practical use, when the groove 6 is deepened about twice as much as the layer 5 or more than it, the diffusion of electrons can be prevented much effectively, and the distance X between the memory cell array 9 and the substrate bias generation circuit 4 can be largely reduced. Besides, the malfunction of peripheral circuits due to the diffusion of electrons from said generation circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device incorporating a substrate bias generation circuit.

[Technical background of the invention and one problem thereof] Memory cells of MoS type dynamic RAM (d-R, AM), which is a volatile memory device among semiconductor memory devices, are as follows:
Usually, as shown in FIG. 13, it is composed of - MOS transistors Q and one memory capacitor CM. This memory cell stores information in the form of a memory capacitor CMk: charge. If the charges stored in this memory cell leak or if charges enter from outside, the information in the memory cell will be destroyed.

On the other hand, in JRAMs, substrate bias is A generation circuit is built in. This substrate bias generation circuit is normally composed of an emission circuit O8C, a driver DR, and a charge pump circuit CP driven by this, as shown in FIG.・Pump circuit CP is a capacitor C
and a MOS transistor Q1, which functions as a pump valve.
It consists of Q2. The semiconductor substrate is p-type, and a single positive power supply V
When using cc (=5V), charge pump circuit C
A negative body bias voltage VBB (-3
(approximately V) is obtained.

When dRAM becomes highly integrated, a problem arises in that carriers injected into the substrate from the above-described substrate bias generation circuit reach the memory cell array region and destroy information in the memory cells. FIG. 15 is a diagram for explaining the situation. In the figure, 1 is a p-type Si substrate,
9 is a memory cell array region, 2 is an n-type layer which is a substrate side electrode of a cell capacitor, and 3 is a capacitor electrode commonly provided to all memory cells, a so-called cell plate. 4 is a substrate bias generation circuit (SSB) as shown in FIG. 14, and 5 is an n1 type layer which is an output terminal diffusion layer thereof. 10 is a field insulating film, and a p+ type layer 11 is formed thereunder as an inversion prevention layer.

As described above, the n+ type layer 5 is forward biased between negative substrate biases. As a result, electrons are injected from the n+ type layer 5 into the substrate 1. The electrons injected into the substrate 1 recombine with holes, which are majority carriers in the substrate, and disappear. However, as dRAM becomes highly integrated and the distance X between the memory cell array area wi9 and the substrate bias generation circuit 4 becomes small, the electrons injected from the n1 type layer 5 reach the memory cell array area 9. This will destroy cell information. If the substrate 1 has a high resistance, the diffusion length of electrons within the substrate 1 will be correspondingly long, and the effect will be greater.

Conventionally, in order to solve this problem, the distance X between the memory cell array area and the substrate bias generation circuit has been designed to be sufficiently larger than the diffusion length of one electron in the substrate. . Specifically, in terms of chip layout, the substrate bias generation circuit is placed as close to the corner of the chip as possible, or wasted space is created in order to increase X. This reduces the degree of freedom in design layout for dRAMs, which are becoming increasingly highly integrated, and is a major obstacle in reducing the chip size.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor memory device with higher integration and improved reliability.

[Summary of the invention]

The present invention prevents carriers injected from the diffusion layer into the substrate from diffusing into the peripheral element region, in addition to a field insulating film for element isolation, around the diffusion layer that is the output terminal of the substrate bias generation circuit. It is characterized by having a means.

〔Effect of the invention〕

According to the present invention, when applied to a ClRAM, it is possible to reduce the distance between the substrate bias generation circuit and the memory cell array area, and prevent cell data from being destroyed by carriers injected into the substrate from the substrate bias generation circuit. can.

Further, according to the present invention, effects can be obtained not only in dRAM but also in preventing malfunctions in peripheral circuits and preventing increases in leakage current. That is, by reducing the leakage current to the diffusion layer 70-tainter node (for example, a decoder section, bootstrap capacitor, etc.) of the peripheral circuit, a drop in the 70-ting potential is prevented.
Malfunctions of peripheral circuits are prevented. Further, an increase in standby current and an increase in input terminal current due to carrier diffusion to other peripheral circuit diffusion layers is prevented, thereby reducing the burden on design specifications.

Therefore, according to the present invention, the degree of freedom in designing the layout of the memory cell array and peripheral circuits is increased, the chip size can be reduced, and a highly integrated and highly reliable semiconductor memory device can be realized. .

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows the configuration of one embodiment in correspondence with FIG. 15. Portions corresponding to those in FIG. 15 are given the same reference numerals and detailed explanations will be omitted. In this embodiment, a groove 6 is provided so as to surround the n+ type layer 5, which is the output terminal of the substrate bias generation circuit 4, as a means to prevent electron diffusion.

When such a groove 6 is provided, the groove 6 becomes a barrier against diffusion of electrons injected from the n+ type layer 5 into the substrate 1 by setting its depth to an appropriate value. As a result, diffused electrons within the substrate can be effectively prevented from reaching the memory cell array region 9. More specifically, electrons injected into the substrate 1 from the n+ type layer 5 pass under the groove 6 and reach the memory cell array region 9. If the path indicated by the broken line in FIG. 1 is equal to or less than the electron diffusion length within the substrate, it is certain.

In practice, if the depth of the groove 6 is about twice or more than the depth of the n+ type layer 5, electron diffusion can be sufficiently effectively prevented, and the memory cell array region 9 and the substrate bias generation circuit can be 4 can be made significantly smaller than in the past. Further, malfunction of peripheral circuits due to diffusion of electrons from the substrate bias generation circuit is prevented. This increases the degree of freedom in design, resulting in highly integrated and reliable products.
RAM can be obtained.

FIG. 2 shows another embodiment. In this embodiment, a deep n+ type layer 7 is formed around the n+ type layer 5 as a means to prevent electron diffusion. A positive voltage, for example a power supply Vcc, is applied to this n+ type layer. 12 indicates a depletion layer extending from the n+ type layer 7 to the substrate 1.

In this way, when the n+ type layer 7 connected to Vcc is provided, the electrons injected from the n+ type layer 5 into the substrate 1 and diffused are
When it enters the depletion layer 12 extending from the n+ type layer 7 to the substrate 1, it is accelerated by the electric field and is effectively collected in the n+ type layer 7. Therefore, in this embodiment as well, electrons injected from the n+ type layer 5 are effectively prevented from reaching the memory cell array region 9. As a result, the memory cell array area 9 and the substrate bias generation circuit 4 can be connected to each other without destroying the cell data.
The distance X between them can be made sufficiently small. Further, the operation of peripheral circuits can be stabilized.

FIG. 3 shows yet another embodiment. In this example, n+
As a means to prevent diffusion of electrons injected from the mold layer 5,
A p+ type layer 8 is provided in contact with and surrounding the n+ type layer 5. This p+' type layer 8 does not necessarily need to be in contact with the n+ type layer, but as shown in FIG.
It is sufficient if it is formed in the vicinity of the mold layer so as to surround it, or it may be surrounded as shown in FIG. This p+ type layer 8 is formed by, for example, ion implantation. 9/
This is a high boron concentration layer of cIR3.

With this structure, electrons injected from the n+ type layer 5 into the substrate 1 are effectively recombined with holes in the highly concentrated p+ type H'B and disappear. That is, within the p+ type layer 8, the p− type substrate 1
Since the diffusion length of electrons is shorter than that of the first embodiment, the number of electrons reaching the memory cell array region 9 can be sufficiently reduced even if the distance X between the memory cell array region 9 and the substrate bias generation circuit 4 is smaller than before. As a result, the same effects as in the previous embodiment can be obtained.

The present invention is not limited to the above embodiments. For example, the groove 6 in FIG. 1 and the n+ type 11 in FIG.
7 may be combined to form a structure as shown in FIG. Similarly, the embodiments shown in FIGS. 1 and 3 can be combined to form a structure as shown in FIG. 7, and the embodiments shown in FIGS. 1 and 5 can be combined to form a structure as shown in FIG. It is also possible to
The embodiments shown in the figures can also be combined to form a configuration as shown in FIG. 9. Furthermore, it is also possible to combine all of the embodiments shown in FIGS. 1 to 3 to form a configuration as shown in FIG. 10.

If you use (or combine) these methods to prevent electron diffusion, the effect will be doubled.

FIG. 11 is an example of an overall plan layout diagram when the present invention is applied to a dRAM. 21 is a memory chip, 2
2 is a chip bed area. The memory chip 21 includes core circuits such as a memory cell array 13, a row decoder 14, and a column decoder 15, as well as various peripheral circuits indicated by diagonal lines (
16 (including input/output circuits) are formed. 17 is a substrate bias generation circuit, and its output terminals are a plurality of diffusion layers 18 G181, 182 . ,...) are placed around the chip. Each diffusion layer 18 is commonly connected by a wiring 20. 23 is a VBB terminal of the chip bed 22. Then, a first
Groove 1.9 (191, 192,...) as shown in the figure
is formed. As shown in the figure, the grooves 19 may form a complete closed circuit or may partially surround the diffusion layer.

Note that the output stage transistor (
The drain diffusion layer of the transistor (corresponding to transistor Q2 in FIG. 12) is also one of the output terminal diffusion layers.

Therefore, a groove is formed around this output terminal diffusion layer as well as the other output terminal diffusion layers. The structure of that part is, for example, as shown in FIGS. 12(a) and 12(b). (a) is a plan view of the output stage transistor section, (b) is its A-A-
FIG. 23 is polycrystalline silicon, gate electrode,
24 and 25 are n+ type source and drain regions, and grooves 6 are formed to surround the entire transistor region in order to prevent diffusion of electrons injected into the substrate 1 from the drain region 25, which is an output terminal diffusion layer. are doing.

With the above configuration, as described above, the diffusion of carriers injected into the substrate from the output terminal diffusion layer 18 is prevented, so that cell data is prevented from being destroyed and malfunctions in peripheral circuits are prevented. , a highly integrated and highly reliable JRAM is obtained.

Although the embodiment of the MO8 type dRAM has been described above, the present invention can also be applied to other semiconductor memory devices incorporating a substrate bias generation circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part structure of a dRAM according to one embodiment of the present invention, FIGS. 2 to 10 are diagrams showing the main part structure of a dRAM according to other embodiments, and FIG. 1.1 is a diagram showing one embodiment. 12(a) and 12(b) are diagrams showing the structure of the output stage transistor section of the substrate bias generation circuit. FIG. 13 is a diagram showing the memory cell configuration of ClRAM.
Figure 15 shows the circuit configuration of the substrate bias generation circuit.
The figure is a diagram showing the main part configuration for explaining the problems of the conventional dRAM. DESCRIPTION OF SYMBOLS 1...p-type Sil board, 2...n+ type layer (cell/capacitor substrate side electrode), 3...cell plate, 4
...Substrate bias generation circuit, 5...N1 type layer (output end diffusion layer), 6...Groove, 7...N+ type layer, 8...
p+ type layer, 9... memory cell array region, 10...
Field insulating film, 1...p+ type layer for preventing inversion, 21
...Memory chip, 22...Chip bed, 13.
...Memory cell array, 14...Row decoder, 15
... Column decoder, 16... Peripheral circuit, 17...
・Substrate bias generation circuit, 18...output terminal diffusion layer,
19...Groove, 20...Wiring, 23...VBB terminal. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure sm. ] Figure 6 Figure 7vA Section 12 Figure 13 SS Figure 15

Claims (1)

[Scope of Claims] (1) In a semiconductor memory device in which a substrate bias generation circuit is formed on a semiconductor substrate together with a memory cell array and peripheral circuits, the substrate bias generation circuit provides a substrate bias voltage of opposite polarity to a power supply voltage. A semiconductor memory device characterized in that a means is provided around a diffusion layer which is an output terminal to prevent carriers injected from the diffusion layer into a substrate from diffusing into a peripheral element region. (2) The semiconductor memory device according to claim 1, wherein the means for preventing diffusion of carriers is a groove dug in the substrate. (3) The semiconductor memory device according to claim 2, wherein the depth of the groove is at least twice the depth of the diffusion layer that is the output terminal of the substrate bias generation circuit. (4) The semiconductor memory device according to claim 1, wherein the means for preventing carrier diffusion is a diffusion layer to which a reverse bias potential is applied with respect to the substrate. (5) Claim 1, wherein the means for preventing carrier diffusion is a highly impurity concentration diffusion layer of the same conductivity type as the substrate, which is formed so as to surround the diffusion layer that is the output terminal of the substrate bias generation circuit. The semiconductor storage device described above. (6) The semiconductor memory device according to claim 1, wherein the memory cell array is an arrangement of dynamic memory cells.