JPS613247A - Logical lsi - Google Patents

Abstract

PURPOSE:To facilitate the logical design of a logical part including order control by providing plural microprogram sequencers and microprogram memories on the same chip and thus constituting the logical LSI. CONSTITUTION:When the 1st entry input is supplied to an address generation part PLA, transfer gates G1-G8 are opened to generate the 1st microprogram address, which is sent to a decoder DEC to read out a microinstruction, thereby outputting various control signals and a next address. The transfer gates G1- G8 are turned off and G11-G18 are turned off with some of the control signals. Conseqently, the next address is supplied to the decoder DEC to read a next microinstruction out. Thus, a series of microinstructions are read out and supplied to respective parts of logical circuits constituting a system outside the chip from an output terminal DO, thereby performing sequential control.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to a microprogram control technology and a configuration method of a programmable control logic LSIC large-scale integrated circuit, such as a sequential control technology. This invention relates to a technique that is effective for use in configuring the control unit of a control system that performs.

[Background Art] Conventionally, methods for configuring the control section of a microprocessor include a random logic method and a microprogram method (F, published by Sanpo Publishing Co., Ltd. in April 1978).
(See pages 11 to 24 of ``Micro Programs and Control Equipment'').

For example, when developing and designing highly versatile large-scale logic t, sr such as controllers for peripheral devices such as microcomputers and disk controllers, the microprogram method is often adopted (Nikkei Electronics, 1982 August 3011, No. 189-1
(See page 9).

In addition to this, when developing and designing a controller with relatively low versatility that sequentially controls a robot or a specific system, LSI such as TTL logic, gate array, or PLA (programmable logic array) is required. Control boards are often designed by combining them to form logic circuits. In such a case, the configuration of the control section that controls the logic circuit on the board is a random logic system, which has the disadvantage that the logic design becomes extremely complicated.

[Object of the Invention] An object of the present invention is to provide a logic LSI that facilitates logic design when configuring a logic unit including order control.
Our goal is to provide the following.

Another object of the present invention is to provide an extremely versatile microprogram logic LSI in which the length and number of control words can be arbitrarily set.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, a microprogram that stores a macroprogram, such as a microprogram sequencer consisting of a programmable logic array and a multiplexer that outputs a predetermined microprogram address based on an externally supplied signal. By configuring a logic LSI by providing a plurality of blocks and memories on the same chip, logic design, which was conventionally done using a random logic method, can now be performed using a microprogram method, and this makes it possible to perform sequential control. In addition to making it easy to modify the logic of the included logic section, it is also possible to store microprograms with any word length or number of words by combining multiple microprogram memories on the same chip in parallel or serially. The present invention achieves the above object of providing a highly versatile microprogram type logic LSI.

[Embodiment] FIG. 1 shows an embodiment of the programmable logic section sr according to the present invention.

In the figure, each circuit block surrounded by a chain line A is constructed on one semiconductor chip (substrate) such as single crystal silicon.

Inside the semiconductor chip A, there are a plurality of microprogram memories MPM, ~M that can store microprograms.
P M n and each microprogram memory MPM,
A plurality of microprogram sequencers MPS and ~MPSn are provided corresponding to ~MPM'n and supply a microprogram address (address of the next microinstruction to be read) to the microprogram memory. There is.

The microprogram memories MPM, ~MPMn are read-only ROMs (read-only memories), rewritable EPROMs (electronically programmable read-only memories), or RAMs (random memory) that can be read and written at any time. access memory), etc. Each microinstruction (control word) constituting the microprogram stored in each microprogram memory MPM has a control field that determines the control content, and a next address that contains information indicating the address of the next microinstruction to be read. - field, and the information in the next address field is fed back to the corresponding mitaro program sequencer MPS.

In addition, JZ Microprogram Sequencer MPS,
~MPSn is an address forming unit PL consisting of, for example, a programmable logic array, etc., although it is not particularly limited.
A, and a multiplexer MPX that supplies either the address supplied from this address forming section PL'A or the next address fed back from the microprogram memory MPM to the microprogram memory MPM. .

The microprogram memory MPM is provided with a decoder that decodes the microprogram address supplied from the multiplexer MPX and outputs a corresponding microinstruction.

”-The address forming unit PLA is input with an entry manual signal supplied from outside the chip to determine the content of the work, and the address forming unit PLA inputs an entry signal supplied from outside the chip to determine the content of the work. By appropriately programming, an address corresponding to the type of entry manual can be formed and output.

A wait input signal and a branch input signal supplied from outside the chip can be input to the multiplexer MPX, and when the wait input signal is input, the address of a certain step is fixed until the state changes. Furthermore, when a branch point is reached, a jump is made to a microinstruction that performs different processing depending on the branch input signal input at that time.

FIG. 2 shows an example of the configuration of the multiplexer MPX. Here, although there are no particular restrictions, the microprogram address is 8 bits and the branch input is 1 bit.
It is shown that it is made up of bits.

An address forming unit PL such as a programmable logic array that forms addresses based on entry manual input.
The address output from A is the transfer gate G1~
Microprogram memory M P M via G8
is supplied to the decoder DEC.

In the address input signal line of the above decoder DEC.

The 8-bit address contained in the microinstruction read from the microprogram memory MP'M is made available via transfer gates Gj to G8. Furthermore, the lower (or upper) two bits of the signal line that supplies this next address are connected to
True level and false level signals of branch inputs can be input, and transfer gates G2, +G22 and G
11+G12 are opened and closed in a complementary manner, so that part of the next address can be replaced by a branch input.

Each of the transfer gates G1 to Ga+Gt1 to G5Q and G21+G22 is controlled by a control signal that is part of a control field of a microinstruction read from the microprogram memory MPM.

However, the above transfer gates 01 to G8 are all turned on in the initial state, and other transfer gates 0
1 to G8 and 6211 G2□ are turned off, and the address formed by the address forming unit PLA based on the entry manual is first supplied to the decoder DEC.

When the system is operated and the first entry power enters the address forming unit PLA, the Drasf 7 gates 61 to G8 are opened as described above, and the first microprogram address corresponding to the type of entry power is input. is formed and sent to the decoder DEC, the first microinstruction of the process is read out, and various control signals and the next address are output. After the first microinstruction is read, the transfer gates G1 to G8 are turned off by part of the control signal of that microinstruction.
Instead, transfer gates G11 to G1B are turned on.

This allows the next microinstruction to be read.
The address in the address field is provided to the decoding DEC to read the next microinstruction. In this way, a series of microinstructions are read one after another and supplied from the output terminal Do to each part of the logic circuit constituting the system outside the chip, thereby performing sequential control.

When a branch condition occurs during reading of a series of microinstructions, the transfer gates Gl 1 and G are activated by control signals output from the microprogram memory.
l2 is turned off and Drasphage-hG2. +022
is turned on. As a result, a part of the next address (2 bits 1 -) is replaced with a branch input, so that a jump is made to the microinstruction corresponding to the branch input input at that time.

An end instruction is written at the end of a series of microinstructions corresponding to one entry manual. This end command turns off transfer gates 011 to G1Q and G21 r G2□.

A control signal is generated to turn on 61 to G8.

Therefore, when one process is completed, the microprogram address formed by the next engine 1 to 1 is transferred from the address forming unit PLA to the decoder of the microprogram memory MPM through the turned-on transfer gates 61 to G8. Supplied to DEC. As a result, the first microinstruction of the next process is read and the control signal and next address are output. After that,
As described above, the reading of the next microinstruction using the next address of the ficroinstruction is repeated until the processing of the series of microinstructions is completed.

In order to stop the state at a certain step by weight input, for example, each of the transfer gates 61 to G8, G
A circuit for latching the signals controlling G11 to G18 and G21 r G22 may be provided at the front stage, and the gate control signal may be latched by the wait input.

Furthermore, according to this embodiment, a request similar to a no-operation command can be made to correspond to one entry manual. When an entry corresponding to a no-operation instruction is entered, a predetermined microprogram address is formed and supplied to the decoder DEC to read out the specific microinstruction. This microinstruction is similar to the above-mentioned end instruction.
18 and c21r' A control signal is output to close G22 and open G1 to G8.

Therefore, while an entry corresponding to a no-operation instruction is input, 1-Lasphage h G 1~
G8 remains open and successively the same address continues to be supplied to the decoder DEC of the microprogram memory. Therefore, when another entry is input, a different address is formed and supplied to the decoder DEC, so the microinstruction corresponding to that entry is read out, and a series of microinstructions based on the next address are then read out. Instruction reading is repeated.

Each of the plurality of microprogram sequencers MP81 to MPSn and microprogram memories MPM to MPMn shown in FIG. 1 is operated as described above. . Furthermore, in the embodiment described above, input pins are provided for the plurality of microprogram sequencers MPS to MPSn so that entry manual signals each consisting of several bits can be input thereto.

Therefore, if the microprogram address has an 8-pin 1-configuration as described above, the microprogram memory M
The PM is configured to store 21+ or 256 words of microinstructions. On the other hand, the PL in n microprogram sequencers MP81 to MPSn
A is programmed separately and separate microprograms are stored in microprogram memories MPM1-MPMn.

Then, by inputting a valid entry only to one of the microprogram sequencers (an entry corresponding to a no-operation instruction is input to the other microprogram sequencers), 1, for example, 256Xn words can be input. A microprocessor or control unit can be constructed with microinstructions j'.

In addition, the above microprogram sequencer MP
The PLAs in the microprogram memories MpM, ~M P S are programmed identically, and the same entries are input.
The next address field of each microinstruction in M n contains exactly the same next address in each memory. Then, by inputting a certain entry, each microprogram sequencer MPS, ~M
P S n generates the same address and supplies it to the corresponding microprogram memories MPM1 to M PM n. As a result, each microprogram memory MPM1 to MPMn is read out in exactly the same way, that is, in parallel.

As a result, from the outside, it looks like a single microprogram.
A control word whose word length is n times the word length of the control field of the microinstruction stored in the memory is output.

Therefore, by appropriately setting the number of microprogram sequencers and microprogram memories to be used, it is possible to construct a microprocessor or control section that outputs control words of arbitrary word length.

By combining the above two configuration methods, a microprocessor or controller that can store a large number of microinstructions (the number of words is an integer multiple of 256 words) having a control word with a longer word length than when using one microprogram memory. It can also constitute a section.

According to the above embodiment, sequential control signals for performing a desired task can be sequentially output by microinstructions stored in the microprogram memory. Moreover, P in the microprogram sequencer
By appropriately programming the LA ROM, it is possible to arbitrarily configure a microprogram that can execute a variety of processes, including processes with long steps and processes with short steps. Therefore, all logic circuits conventionally constructed using a random logic system can be constructed using the microprogram system logic LSI according to this embodiment.

For example, it can realize the functions of a controller or sequencer that controls a robot, a 4-bit microcomputer, or a signal generation circuit for liquid crystal driving that continuously generates a predetermined pattern based on a certain signal (entry). can also be configured as a counter.

In other words, the control field of the microinstruction in the microprogram memory is filled with binary codes of 0 and 0, respectively.
．． . . 0 to I, ■, . . . are written in advance, and if these are read out in order, the same output as an N-ary counter can be obtained. By a similar method, it is possible to output a signal that drives each segment 1 to sequentially display a predetermined pattern (numbers, etc.) of the liquid crystal display device.

Note that in the above embodiment, multiple microprograms
A sequencer and microprogram memory constitute one programmable logic LSI chip, but when the microprogram memory is configured using EEPRoM (electrically programmable and erasable ROM) or RAM, It is also possible to form a write circuit for writing microinstruction codes into a microprogram memory on the same chip. In that case, the configuration can be such that write data is input using the output terminal Do.

Furthermore, in the above embodiment, the next microinstruction is read out only by the address in the next address field of the microinstruction that was read immediately before.
It is also possible to read out the next microinstruction by combining all or part of the address output from the address forming unit PLA with the next 1- address of the microinstruction.

[Effects (1) A microprogram sequencer consisting of a programmable logic array and a multiplexer configured to output a predetermined microprogram address based on a signal supplied from the outside, and a microprogram that stores a microprogram. Since a plurality of program memories are provided on the same chip, logic design that was conventionally performed using the random logic method can now be performed using the MicroProgera 11 method. This has the effect of facilitating the logical design of the section.

(2) A microprogram sequencer consisting of a programmable logic array and a multiplexer configured to output a predetermined microprogram address based on an externally supplied signal, and a microprogram memory that stores the microprogram. Since multiple microprogram memories are provided on the same chip, multiple microprogram memories on the same chip can be combined in parallel or serially. This has the effect of providing a highly versatile microprogram type logic LSI that can store microprograms.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, a microprogram sequencer is not limited to 1 or 2 bits for entry input or branch input, and may be configured so that even more signals from 1 to several bits can be input. . Furthermore, each microprogram memory may be configured such that the word length (number of bits) of each microinstruction in a plurality of microprogram memories provided in an LSI is different. Furthermore, the transfer gate that constitutes the multiplexer is a MOSFET.
However, the present invention is not limited to this, and may be configured using a logic gate circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a logic LSI according to the present invention, and FIG. 2 is a block diagram showing an example of the structure of a multiplexer used therein. MPM] ~ M P M n...Micro program. Memory, MPS1 to MPSn...Microprogram sequencer, MPX...Selection switching circuit (
multiplexer), PLA...Address formation unit (programmable logic array), 61'+Go+G
z1-G1atG21. G22...Transfer gate...Figure 1

Claims (1)

[Scope of Claims] 1. A logic LSI comprising a plurality of microprogram memories and a microprogram sequencer provided corresponding to each of these microprogram memories. 2. The microprogram sequencer executes a predetermined microprogram based on signals supplied from the outside.
a programmable logic array configured to output an address, at least a portion of the output signal of the programmable logic array, and a next address included in a microinstruction read from the microprogram memory; 2. The logic LSI according to claim 1, further comprising a selection switching circuit for selectively supplying the microprogram memory with the microprogram memory. 3. The selection switching circuit has a branching function of converting a part of the address supplied to the microprogram memory to change the jump destination based on a specific signal supplied from the outside. Logic LSI according to claim 1 or 2, characterized in that
. 4. The selection switching circuit has a function of fixing the address supplied to the microprogram memory based on a specific signal supplied from the outside and stopping in that state. A logic LSI according to claim 1, 2, or 3.