JPH01125124A - Programmable logic array - Google Patents

Abstract

PURPOSE:To utilize one and same programmable logic array for the simulation of various logic circuits by expressing a logic function based on the content of a rewritable storage element. CONSTITUTION:The logic array has an AND array 100 where associative memory cells 130 whose content is to be rewritable are arranged as a matrix and the coincident outputs of the associative memory cells 130 on the same column are connected together through a coincident line 141, and an OR array 110 where plural switching means 170, 180 connecting in series with storage cells whose storage content is rewritable are arranged as a matrix, the switching of switching means 170, 180 of each column is controlled by storage outputs through the storage cells 160 and the coincident line 141 from the associative memory cells 130 on the same column and one terminal of the switching means 170, 180 of the same row is connected in common to the output. thus, various logic functions can be programmed in the real time by setting the bit pattern to the storage cell in the associative memory 130 in the AND array 100, a coincidence output control circuit 140 and the OR array 110.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable logic array capable of realizing various logic functions using a two-stage logic circuit of AND and OR.

[Conventional technology]

Conventional programmable logic plays implement the necessary logic functions by installing Hiez board diodes at each intersection of wires running vertically and horizontally, and selectively cutting them off. Conventional programmable logic arrays are described in detail in ``How to Make and Use rPLA'' by Tsutomu Sasao, published by Nikkan Kogyo Shimbun.

[Problem that the invention seeks to solve]

The conventional programmable logic play described above has the disadvantage that the logic function is programmed by blowing out the Hiez type diode, and therefore the logic function once programmed cannot be modified. - Generally, the programmable logic play must be replaced and reprogrammed several times to achieve the final logic function. This work increases the cost and development time of devices using programmable logic arrays. Furthermore, LSI logical storage = I/ is required. Especially for digital processing that processes video.
When determining the circuit system and parameters of a filter, it is necessary to check the quality with human eyes, and computer simulation requires an enormous amount of calculation time, so an experiment board is required. In this case, it is important to be able to quickly modify the logic functions and to connect the experimental board to another LS.
It is desirable that IK can be reused. Furthermore, an experiment board using programmable logic play is also required when determining the specifications of a device using an LSI to be developed using a prototype. However, since the conventional program 2 maple logic play cannot modify the logic function, it is difficult to modify the experimental board and even the LSI.
This has the disadvantage of increasing development time and development costs.

[Means for solving problems]

The programmable logic play of the present invention is an AND play in which associative memory cells whose memory contents can be rewritten are arranged in a matrix, and matching outputs of the associative memory cells in the same column are connected to each other with matching lines, and a programmable logic play that allows rewriting the storage contents. A plurality of switch means connected in series with possible memory cells are arranged in a matrix, and each column switch means is controlled to open and close by the above-mentioned - connecting line from the associative memory cell in the same column and the memory output of the memory cell. , and an OR array in which one ends of the switch means in the same row are commonly connected to an output.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. This programmable logic array is an AND array 1 surrounded by a dashed line.
00, the OR array 110 surrounded by other broken lines, and the read/write circuit 12OA.

It consists of 120B and 120C. The AND array 100 has a configuration in which associative memory cells 130 and coincidence output control circuits 140 are arranged in three rows and three columns. Associative memory cell 1
The coincidence output 131 of 30 is input to the coincidence output control circuit 140, and the coincidence output of the coincidence output circuit 140 of the same column is input to the coincidence line 14.
Commonly given to 1.

- One end of the laying line 141 is connected to the power supply V via a resistor 150, and the other end is connected to the OR array 110.

The OR array 110 has a configuration in which a memory cell 160 and two MOS transistors 170 and 180 connected in series are arranged in two rows and three columns. MOS) transistor 170
, 180 are connected in series, and the output line 181 is connected to the resistor 182.
Connected to power supply V via. Associative memory cell 1 in each row
30, the coincidence output control circuit 140, and the memory cell 160 are connected to the positive bit lines 121A and 121B.

121C and negative bits 11122A, 122B, 122C
and read/write circuits 12OA, 120B, 120C
Leads to.

Next, the operation of AND array 100 will be explained. The AND array 100 receives the variables X1 . Perform selective conjunction between,X,,X,in each column,
The results are output to the match line 141 of each column. Whether or not to perform logical product depends on the memory contents of the coincidence output control circuit 140 @1#
and @0”.

Also, whether the AND is performed on variables or the inversion of variables is determined by the memory content of the associative memory cell 130 "1".
”, -11Q#.

When a variable X (X represents Xt,
(/X indicates the inversion of X) is output. The associative memory cell 130 compares its memory contents with the variable X,
When the two match, the match output 131 is set to high impedance with respect to the ground, and when they do not match, the match output 131 is set to low impedance. That is, associative memory cell 140 has F=
Outputs the logical operation result of X-D+/X・/D. If memory content D=1, F=X; if D=O, F=/X. This calculation result F is the matching output 13 of @1'' and '''0#.
It is output in correspondence with the high impedance and low impedance of 1.

The coincidence output control circuit 140 has a storage content S of @1.
”, connect the match output 131 to the match line 141, and
=00, open. Therefore, when S=0, the variable aX
does not affect match line 141. Since the plurality of coincidence outputs 131 in the same column are commonly connected to the coincidence line 141 via the coincidence output control circuit 140, the AND of the plurality of coincidence outputs 131 is obtained on the coincidence line 141.

Here, the memory content of the m-th row and n-th content addressable memory cell is Dm
If the memory content of the match output control circuit 140 in the mth row and the nth column is Smn, and the input variable to the associative memory cell 130 in the mth row is -, then the match l in the nth column! 11141 has (1)
Ln shown by the formula is output.

Ln=(Xl@DtH+/Xt-/D1n)
・S tn+ (Xt "Dtn+/Xt" /D
un ) ” Sun+(Xm*Dmn+/Xm@/D
mn)*Smn ・(1) Logical product array 10 in FIG.
0 is m=3. An example where n=3 is shown. - As an example, K, which performs the logical product of L t =
Let u=1, S tt=o, Sst+1, and set the content of the associative memory cell 130 to D11 snow 1. n
tt=t (t indicates don't care), D s't=0
And it is sufficient.

In this way, when the memory contents of the associative memory cell 130 and the coincidence output control circuit 14G are programmed, each -
Various logical AND operation results can be output to the laid line 141. Write data to the content addressable memory cell 130 is applied to the input/output line 123, and write data to the coincidence output control circuit 140 is applied to the product setting line 124. These write data are read/written by the read/write circuits 12OA and 120B.
Positive bit lines 121A and 121B are used as positive and negative data, respectively.
, negative bit lines 122A, 122B, and further designated by word line 142.
30 and is written to the coincidence output control circuit 140.

Next, the operation of OR array 110 will be explained. The OR array 110 is connected to a plurality of matching lines 141 from the AND play 10G, performs a selective OR operation on the AND operation results output from the - line 141, and outputs the result from the output line 181. Output. - The laid line 141 is connected to the gate of the MOS transistor 180 in the same column. The opening and closing of the MOS transistor 170 connected in series with this is controlled in accordance with the memory outputs "'0" and "1"K of the memory cell 160. One end of each column's MOS) run raster 1800 is commonly connected to an output line 181 together with a resistor 182.

Here, the memory output of the m-th row and n-th column memory cell 160 is Rmn
, when the output of the matching line 141 in the n-th column is Ln, the output Ym shown in equation (2) is obtained on the output line 181 in the m-th row.

Ym=/(L 1 ” nn11 + Ll ・%1@
+ ・"...+Ln+1Rmn)...
'(2) As shown in equation (2), the output line 181 of each row has @1"
An inverted output of the logical sum of the output L5-IJnK of the column match line 141, which is the storage output (Rm=@l'), is obtained. This indicates that when the memory contents of the memory cell 160 are programmed, various logical sums for K, -I, and I can be output from the output @181. Writing to the memory cell 160 is performed by applying write data to the membrane constant line 125 and specifying a column using the word line 142.

Therefore, the associative memory sum 130 in the AND array 100, the coincidence output control circuit 140, and the logic V array 1
By setting bit patterns in the storage cells within 10, various logic functions can be programmed. Furthermore, it is also possible to read the set bit pattern via a read/write circuit.

Can be used. Furthermore, the coincidence output control circuit 140 is
Coincidence output 13 in the memory cell described in Publication No. 9594
It can be constructed by adding a transistor between KMO8) and the match line 141. The gate of the MOS transistor is connected to the in/(-) in the memory cell. Furthermore, the memory cell 160 can be configured similarly to the memory cell.

FIG. 2 is a configuration diagram of a second embodiment of the present invention. The programmable logic play consists of an AND array 100, an OR array 110, a register 210, a decoder 220, and a bidirectional buffer 230. Register 210 is connected to product setting line 124, and decoder 220 is connected to word line 1.
42 , and the bidirectional buffer 230 connects to the output line 181 and the membrane constant line 125 .

For convenience of explanation of operation, FIG. 1 is referred to for the configuration of AND array 100 and AND array 110. The register 210 takes in the data on the input/output line 123 in synchronization with the clock signal 212, and transfers the taken data to the product setting line 1.
24 to a coincidence output control circuit 140 in AND array 100. Based on the mode signal 231, the bidirectional buffer 230 leads the data on the output line 181 to the logic input/output line 232, or conversely outputs the data applied to the logic input/output line 232 to the uterine constant line 125. AND array 10
When programming a logic function to 0 and the OR array 110, write data to the content addressable memory cell 130 is given to the input/output line 123, write data to the match output control circuit 140 is set to the register 210, Logic input/output line 2
32 with write data to the memory cell 160. At this time, the decoder 220 specifies the write column by driving the word line 142 specified by the word address 221.

In this way, in this embodiment, by providing the register 21o1 decoder 220 and the bidirectional buffer 230, the number of input/output terminals of the programmable logic array is halved compared to the embodiment of FIG. Since programmable logic arrays are generally mounted on IC packages, a smaller IC package can be used by halving the number of input/output terminals. Therefore, more programmable logic plays can be mounted on the printed circuit board, resulting in a reduction in the cost of devices using this.

Note that in the above description, the eleventh second M0S transistors 170 and 180 and the associative memory cell 130 are
), although other switching means such as bipolar transistors can be used. Furthermore, it is also possible to add a register or an inverter to the output line 181 and the logic input/output line 232.

〔Effect of the invention〕

As described above, the present invention can easily provide a programmable logic array in which a logic function can be rewritten in real time by expressing the logic function using the contents of a rewritable storage element. In addition, the same programmable logic play can be used for simulation of various logic circuits.

Therefore, by reducing the modification time and reusing the four logic functions, it is possible to reduce the development period and development cost of devices and LSIs using programmable logic arrays.

With current LSI technology, a static RAM of 256 kilobits has been realized. The program point of this programmable logic play is 4-bit static RAM.
If it can be realized using the area of a cell, it means that a programmable logic play with 32 inputs/outputs and 2048 product terms can be realized using the current LSI technology. The number of product terms is 4.
This means that a logic function equivalent to 8 BO gates can be expressed with twice as many gate chips. Therefore, by using 10 printed circuit boards on which 100 programmable logic play LSIs are mounted, it is possible to simulate a logic circuit with 8 million gates in real time. This has the effect that logical simulation of large combinators can be executed extremely quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the invention, and FIG. 2 is a block diagram of another embodiment of the invention. 100... logical AND array, 110...
OR array, 12OA, 120B, 120C...
. . . Read/write circuit, 130 . . . Associative memory cell, 140. Old . . . Coincidence output control circuit, 150.
182...Resistance, 160...'Memory cell, 170, 180...-MOS) Rungis/, 2
10...Register, 220...Decoder, 230...Bidirectional pass/f. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] 1. A logical AND array in which associative memory cells whose memory contents can be rewritten are arranged in a matrix, and matching outputs of the associative memory cells in the same column are connected to each other by matching lines, and A plurality of switch means connected in series with possible memory cells are arranged in a matrix, and the switch means in each column is controlled to open and close by the matching line from the associative memory cell in the same column and the memory output of the memory cell. , and an OR array in which one ends of the switch means in the same row are commonly connected to an output. 2. The content addressable memory cell includes a coincidence output control circuit comprising a second switch means for connecting the coincidence output and the coincidence line, and a rewritable storage means for controlling opening/closing of the switch means. Claim 1:
Programmable logic array as described in Section.