JPS6132479A - Manufacture of nonvolatile semiconductor memory device - Google Patents
Manufacture of nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS6132479A JPS6132479A JP15601584A JP15601584A JPS6132479A JP S6132479 A JPS6132479 A JP S6132479A JP 15601584 A JP15601584 A JP 15601584A JP 15601584 A JP15601584 A JP 15601584A JP S6132479 A JPS6132479 A JP S6132479A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- sio2 film
- memory device
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 17
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 10
- 239000001257 hydrogen Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- -1 hydrogen ions Chemical class 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 abstract description 9
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 9
- 229910052682 stishovite Inorganic materials 0.000 abstract description 9
- 229910052905 tridymite Inorganic materials 0.000 abstract description 9
- 238000000137 annealing Methods 0.000 abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 4
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- 230000014759 maintenance of location Effects 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は不揮発性半導体記憶装置の製造方法に係り、
特にシリコンゲートの窒化膜および酸化膜絶縁のいわゆ
る５ＮＯ８形不揮発形記憶装置の製造方法の改良に関す
るものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device,
In particular, the present invention relates to an improvement in a method of manufacturing a so-called 5NO8 type nonvolatile memory device in which a silicon gate is insulated with a nitride film and an oxide film.
従来、金属ゲート−窒化シリコン（Ｓｔ 、Ｎ４）膜−
酸化シリコン（Ｓｉｎ２）膜−半導体構造のいわゆる罠
形不揮発性記憶装置では、アルミニウム（Ａｅ）ゲート
のものが大部分であった。そして、この種の記憶装置ノ
重要な特性である記憶保持特性を良好に保つために、高
温処理工程はＳｉ ｓＮａ膜−８ｉ０２膜構造を１形成
する前に行われている。Conventionally, metal gates - silicon nitride (St, N4) films -
Most of the so-called trap-type nonvolatile memory devices having a silicon oxide (Sin2) film-semiconductor structure have an aluminum (Ae) gate. In order to maintain good memory retention characteristics, which are important characteristics of this type of memory device, a high temperature treatment step is performed before forming the Si sNa film-8i02 film structure.
ところが、これを多結晶シリコンをゲート電極として用
いる５ＮＯ８形不揮発性記憶装置に適用する場合を考え
ると、多くの特徴を活かすためには、必ず高温の熱処理
工性がＳｔ、Ｎ４膜−８ｉ０２膜構造形成後に必要とな
り、記憶保持特性に悪影響を与える。However, when considering the case where this is applied to a 5NO8 type nonvolatile memory device that uses polycrystalline silicon as a gate electrode, in order to take advantage of many of the features, high temperature heat treatment must be performed to create a St, N4 film-8i02 film structure. Required after formation and adversely affects memory retention properties.
そして、その原因は、半導体（シリコン）とＳｉ０２膜
との界面の表面準位密度の増大および５ｉ−４膜の伝導
度であシ、種々の検討の結果、特に界面の表面準位が記
憶保持特性に大きく影響していることが判った。The cause of this is an increase in the density of surface states at the interface between the semiconductor (silicon) and the SiO2 film and the conductivity of the 5i-4 film.As a result of various studies, it was found that the surface states at the interface in particular are It was found that the characteristics were greatly affected.
そして、この表面準位の発生原因としては、Ｓｉ０ｇ膜
の膜厚、この膜厚の薄い（代表的数値として数原子層に
相当する２０Ａ）ことによって発生するストレス、５ｉ
０２膜の形成条件、Ｓ ｉ 、Ｎ４膜の形成条件など種
々のものが挙げられ、この界面の表面単位を少なくする
方法として、高温での水素ア、ニールが提案されている
。The causes of this surface state are the thickness of the Si0g film, the stress caused by the thinness of this film (20A, which corresponds to several atomic layers as a typical value), and the 5i
There are various conditions for forming the 02 film, S i , and N4 film, and hydrogen anneal at high temperature has been proposed as a method for reducing the surface unit of this interface.
しかし、この水素アニールはこの場合特に高温（８００
℃以上）で扱うので非常に危険を伴うおそれがある。However, this hydrogen annealing is performed at a particularly high temperature (800
(°C or higher), it can be extremely dangerous.
この発明は以上のような点に鑑みてなされたもので、シ
リコン基板とＳｉＯ□膜との界面の表面準位の減少に高
温水素アニールを用いることなく、水素イオンの注入に
よって表面準位を減少させることによって記憶保持特性
の良好な５ＮＯ８形不揮発性牛導体記憶装置を安全に製
造できる方法を提供するものである。This invention was made in view of the above points, and it reduces the surface states at the interface between the silicon substrate and the SiO□ film by implanting hydrogen ions without using high-temperature hydrogen annealing. The present invention provides a method for safely manufacturing a 5NO8 type non-volatile conductor memory device with good memory retention characteristics.
以下、ｎチャネルＳ、ＮＯ８Ｏ８形見揮発性記憶装置造
方法を例にとって説明する。まずＳｔ基板（１）に選択
酸化を施して活性領域を囲んでフィールド５ｉ０２膜（
２）を形成し、活性領域表面には厚さ約２０Ａの極薄イ
ＳｉＯ，，膜（３）を形成後、ＣＶＤ法テア イｋ ）
” ５ｉ０２膜（２）および極薄い５ｉ０２膜（３）の
上に５ｔ３Ｎ、膜（４）を堆積させる。その後、更にそ
の上に同じ＜ ＣＶＤ法で多結晶Ｓｔ層（４）を堆積形
成し、す／をデポジションして多結晶Ｓｉ層（４）をｎ
形化するっこの段階を第１図に示すっ
つついて、４菓、・双成技術によってグー１１形成用ボ
トレジストパターン（図示ぜず）をマスクとしてグラズ
マエツチ／グを施して多結晶ＳＩゲート電極（５ａ）、
ケートＳｉ、Ｎ４膜（４ａ）、ゲートＳ ｉ０２膜Ｃ３
ａ）を残し、不要となったホトレジストを除去した後ｎ
十形ソース領域（６）及びｎ十形ドレイ／領域（７）を
形成するためリンイオンを注入し、アニールを行って活
性化しておく。その後水素イオンを例えば、注入エネル
ギー３０〜５０ ｋｅＶ 、 （ｆ−人ｉ １ ｘｌＯ
” 〜ｉ ｘｌＯ”ｃｍ−２程度で注入して前述の界面
における表面準位を減少させる。この状態を第２図に示
す。Hereinafter, a method for manufacturing an n-channel S, NO8O8 memento volatile memory device will be explained as an example. First, selective oxidation is performed on the St substrate (1), and a field 5i02 film (
2), and after forming an ultra-thin SiO film (3) with a thickness of about 20A on the surface of the active region, a CVD method is applied.
” A 5t3N film (4) is deposited on the 5i02 film (2) and the extremely thin 5i02 film (3). Then, a polycrystalline St layer (4) is further deposited thereon by the same CVD method, Polycrystalline Si layer (4) is formed by depositing
This step of forming is shown in Figure 1.Following the process, a polycrystalline SI gate electrode is formed by performing glazma etching using the bottom resist pattern (not shown) for forming the goo 11 as a mask using the double formation technique. (5a),
Gate Si, N4 film (4a), gate Si02 film C3
After removing unnecessary photoresist, leaving a) n
Phosphorus ions are implanted to form a 10-type source region (6) and an n-10 drain/region (7), and activated by annealing. Thereafter, hydrogen ions are implanted, for example, at an implantation energy of 30 to 50 keV, (f-person i 1 xlO
The surface level at the aforementioned interface is reduced by implanting at a dose of about 100 cm -2. This state is shown in FIG.
その後は、通常の方法で、眉間絶縁膜（８）の形成１形
ソース領域（６）、ｎ十形ドレイ／領域（７）及びゲー
ト電極（３ａ）へのコンタクト孔の形成（ゲート電極に
関しては図示しなかったので以下説明を省略する） Ｍ
−８ｓからなるソース配ｍ （９）、ドレイン配ａ四の
形成、ソース配線（９）およびドレイン配線αＱとそれ
ぞれソース領域（６）お・よびドレイン領域（７）との
焼結工程、表面保護膜（図示せｒ）形成工程を経て第３
図に示す不揮発性記憶装置の製造は冗ｒする。After that, the glabella insulating film (8) is formed, contact holes are formed for the 1-type source region (6), the nx-type drain/region (7), and the gate electrode (3a) using the usual method (for the gate electrode, Since it is not shown, the explanation is omitted below) M
- Formation of source wiring m (9) and drain wiring A4 consisting of -8s, sintering process of source wiring (9) and drain wiring αQ with source region (6) and drain region (7), respectively, surface protection After the film (r not shown) forming step, the third
The manufacturing of the nonvolatile memory device shown in the figure is redundant.
以上実施例ではｎ十形ソース領域（６）、ドレイ／領域
（７）形成後に水素イオン注入を実施したが゛、Ｓｉ、
、Ｎ。In the above embodiments, hydrogen ions were implanted after forming the nx type source region (6) and the drain/region (7).
,N.
膜（４）堆積直後、または多結晶Ｓｉ層（５）堆積直後
、更にまた、゛多結晶Ｓｔゲート電極（５ａ）、ゲート
５ｔＳＮ４膜（４ａ）およびゲートＳｉＯ２膜（３ａ）
のエツチング形成直後であってもよい。Immediately after the film (4) is deposited, or immediately after the polycrystalline Si layer (5) is deposited, the polycrystalline St gate electrode (5a), the gate 5tSN4 film (4a), and the gate SiO2 film (3a)
It may be immediately after etching formation.
また、この発明はｎチャネルＳｉゲートプロセスのみな
らず、ｐチャネル８１ゲートプロセス、０ＭＯ８（相補
形ＮＤＳ）−８ｉゲートプロセス等にも勿論適用できる
。Further, the present invention is of course applicable not only to the n-channel Si gate process but also to the p-channel 81 gate process, the 0MO8 (complementary NDS)-8i gate process, and the like.
以上説明したように、この発明では５ＮＯ８形不揮発性
記憶装置の製造に当ってシリコン基板と５ｉ０２膜との
界面の表面単位を減少させるために高温水素アニールを
用いることすく、水素イオン注入で達成するようにした
ので、記憶保持特性のよい不揮発性記憶装置が安全に容
易に室温で製造できる。As explained above, in the present invention, high-temperature hydrogen annealing is used to reduce the surface unit at the interface between the silicon substrate and the 5i02 film when manufacturing a 5NO8 type nonvolatile memory device, and this can be achieved by hydrogen ion implantation. As a result, a nonvolatile memory device with good memory retention characteristics can be safely and easily manufactured at room temperature.
第１図〜！ ３図はこの発明の一実施例を説明するため
にその主要段階における状態を示す断面図である。
図において、（１）はシリコン基板、（３）はＳｉＯ□
膜、（３ａ）はゲート５ｉ０２膜、（４）は５ｆｓＮ＜
膜、（４ａ）はゲート５ｉｌＮ４膜、（５）は多結晶シ
リコン層、（５ａ）は多結晶層シリコンゲート電極、（
９） 、 ００は金底配線層である。
なお、図中同一符号は同一または和尚部分を示す０Figure 1~! FIG. 3 is a sectional view showing an embodiment of the present invention at its main stages. In the figure, (1) is a silicon substrate, (3) is a SiO□
film, (3a) is gate 5i02 film, (4) is 5fsN<
(4a) is a gate 5ilN4 film, (5) is a polycrystalline silicon layer, (5a) is a polycrystalline silicon gate electrode, (
9) and 00 are gold-bottom wiring layers. In addition, the same reference numerals in the figures indicate the same or Buddhist priest parts.
Claims (2)
ン膜及び多結晶シリコン層を順次形成し、これらに所要
のパターンにエッチングを施してそれぞれゲート二酸化
シリコン膜、ゲート窒化シリコン膜および多結晶シリコ
ンゲート電極とした後、所要の金属配線層を形成する工
程を含む不揮発性半導体記憶装置の製造方法において、
上記窒化シリコン膜の形成後上記金属配線層の形成以前
の段階で水素イオンを注入して上記シリコン基板と上記
二酸化シリコン膜との界面の表面準位を減少させる工程
を備えたことを特徴とする不揮発性半導体記憶装置の製
造方法。(1) A silicon dioxide film, a silicon nitride film, and a polycrystalline silicon layer are sequentially formed on a silicon substrate, and the required patterns are etched to form a gate silicon dioxide film, a gate silicon nitride film, and a polycrystalline silicon gate electrode, respectively. In a method for manufacturing a non-volatile semiconductor memory device, the method includes the step of forming a required metal wiring layer after
The method is characterized by comprising a step of implanting hydrogen ions at a stage after the formation of the silicon nitride film and before the formation of the metal wiring layer to reduce the surface state at the interface between the silicon substrate and the silicon dioxide film. A method for manufacturing a nonvolatile semiconductor memory device.
注入量１×１０＾１＾１〜１×１０＾１＾３ｃｍ＾−＾
２程度に注入することを特徴とする特許請求の範囲第１
項記載の不揮発性半導体記憶装置の製造方法。(2) Hydrogen ions are implanted at an implantation energy of 30 to 50 keV and an implantation amount of 1 x 10^1^1 to 1 x 10^1^3 cm^-^
Claim 1 characterized in that the injection is carried out to the extent of 2.
A method of manufacturing a non-volatile semiconductor memory device according to section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15601584A JPS6132479A (en) | 1984-07-24 | 1984-07-24 | Manufacture of nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15601584A JPS6132479A (en) | 1984-07-24 | 1984-07-24 | Manufacture of nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132479A true JPS6132479A (en) | 1986-02-15 |
Family
ID=15618447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15601584A Pending JPS6132479A (en) | 1984-07-24 | 1984-07-24 | Manufacture of nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132479A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943837A (en) * | 1987-03-11 | 1990-07-24 | Hitachi, Ltd. | Thin film semiconductor device and method of fabricating the same |
| JP2005045012A (en) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
-
1984
- 1984-07-24 JP JP15601584A patent/JPS6132479A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943837A (en) * | 1987-03-11 | 1990-07-24 | Hitachi, Ltd. | Thin film semiconductor device and method of fabricating the same |
| JP2005045012A (en) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JP4545401B2 (en) * | 2003-07-22 | 2010-09-15 | パナソニック株式会社 | Manufacturing method of semiconductor device |
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