JPS6130783B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo signal demodulation circuit using the Motorola system, which is known as an AM stereo transmission system.

When transmitting stereo signals through radio broadcasts, etc., it is necessary to use a signal transmission method that is compatible so that even ordinary receivers (that is, those not equipped with a stereo system) can receive the broadcast. Therefore, a difference component signal (hereinafter referred to as LR) and a sum component signal (hereinafter referred to as L+R) are synthesized from the left channel (hereinafter referred to as L channel) and right channel (hereinafter referred to as R channel) signals. Usually, LR and L+R signals are transmitted.

One method for transmitting such stereo signals using AM is to amplitude-modulate the carrier wave with a stereo sum (L+R) signal and phase-modulate it with a stereo difference (L-R) signal, thereby transmitting the stereo signal. This amplitude one-angle modulation method is known as the so-called Motorola method.

An example of an AM stereo signal generation mechanism using this Motorola system will be explained. Figure 1 shows the configuration of the transmitting section, where 1 is a general transmission oscillator, 2 is a π/2 phase shift circuit, 3 and 4 are balanced modulation circuits, 5 is an adder circuit, 6 is a matrix circuit, and 7 is a stereo identification signal oscillator, 8 is an L channel input terminal, 9 is an R channel input terminal, 10 is a difference signal output terminal, 11 is a sum signal output terminal, 12 is an amplitude suppression circuit, 13 is an AM modulation circuit, and 14 is an antenna. be.

The carrier wave (cosω _c t) from the carrier wave oscillator 1 is sent to the adder circuit 5 and the first balanced modulation circuit 3, and the carrier wave (sinω _c t) is sent to the second balanced modulation circuit 4 via the π/2 phase shift circuit 2. ) are supplied respectively, and on the other hand, the other inputs of these balanced modulation circuits 3 and 4 are L channel and R channel supplied from input terminals 8 and 9.
The L-R signal and L+R signal synthesized from the channel signals by the matrix circuit 6 are sent to terminals 10 and 11.
Further, the balanced modulation circuit 4 is supplied with a stealth identification signal from the oscillator 7, and the balanced modulation circuit 3 receives a carrier wave (cosω _c t) balanced modulated by the L-R signal. A carrier wave (sinω _c t) is obtained which is balanced-modulated by the L+R signal and the stereo identification signal, and these signals are added in the adder circuit 5 to generate a signal f ₁ (t) at its output terminal a.

f ₁ (t)={1+k(L+R)} cosω _c t +k(L-R+P) sinω _c t This signal f ₁ (t) can be further decomposed as follows to obtain signal f′ ₁ (t) I can do it.

Here, P is a stereo identification signal and k is a constant.

This signal f ₁ (1) is expressed as a vector as shown in Figure 2, where the first term of f ₁ (1), {1+k(L+R)} cosω _c t is a vector (16+17), and the second term Since k(L-R+P) sinω _c t of is expressed by vector 18, vector 19 which is the sum of these vectors is f ₁ (t)
shows.

As is clear from FIG. 2, the phase relationship of f ₁ (t) is the vector 16 representing the carrier wave cosω _c t.
The phase is shifted by a phase angle of 20 relative to cos(ω _c
t+φ).

Now, returning to FIG. 1, the output terminal a of the adder circuit 5
The signal f ₁ (t) obtained at 13, and is AM modulated by the L+R signal from the output terminal 11 (second
(indicated by vector 22 in the figure) appears at output terminal b as a stereo signal e _c and is supplied to antenna 14 .

Here φ=tan ^-1 k(L-R+P)/1+k(L+
R).

If this stereo signal e _c is represented in a vector diagram, it becomes the vector 22 in Fig. 3, which can be further decomposed into two signals 23 and 24 whose carrier wave cosω _c t and phases 25 and 26 are shifted by ±π/4. .

That is, the vector 23 is the first of the equations of the signal e _c
signal component of the term , and the vector 24 is the signal component of the second term. represents.

The above is an example of a mechanism for generating stereo signals in the Motorola system. Next, a general demodulation circuit on the receiving side will be explained with reference to FIG. 4.

In FIG. 4, reference numeral 27 denotes an input terminal, through which the stereo signal e _c is received by a high frequency circuit, a mixing circuit, etc. of the receiver, and a stereo signal e _c1 converted into an intermediate frequency (IF) signal is supplied. be. 28 is a division circuit, 29 is an amplitude suppression circuit, 3
0 is a low-pass filter, 31 is a multiplication circuit, 32 is a PLL
33 is a π/2 phase shift circuit, 34 is a -π/4 phase shift circuit, 35 is a π/4 phase shift circuit, 36 and 37 are multiplication circuits, 3 8 and 39 are bandpass filters, and 40 is an L signal output terminal,
41 is an R signal output terminal.

The stereo signal e _c1 supplied to the input terminal 28 is However, cosω ₁ t is expressed as an intermediate frequency.

This stereo signal e _c1 is supplied to the divider circuit 28 and the amplitude suppression circuit 29, which first generates a signal f _s1 = cos (ω ₁ t + φ) at the output of the suppression circuit 29,
A signal f _s1 is applied to the PLL circuit 32, and a signal sinω ₁ t having a phase difference of π/2 is obtained at its output.

The phase of the output signal sinω ₁ t of the PLL circuit 32 is shifted by π/2 by the phase shift circuit 33, and a signal synchronized with the intermediate frequency, f _s2 =cosω ₁ t, is extracted from the output. These signals f _s1 and f _s2 are supplied to a multiplication circuit 31, where they are subjected to synchronous detection together with a low-pass filter 30, and a signal f _s3 =cosφ is obtained as an output. This signal f _s3 is applied to the other input of the divider circuit 28 and divided by the stereo signal e _c1 from the input terminal 27 to obtain the following stereo signal e _c2 in which the L channel and the R channel are separated.

This signal e _c2 is applied to the second and third multiplier circuits 36,
37 and output from the phase shift circuit 33, the signal f _S2 = cosω ₁ t is phase-shifted by the -π/4 phase shift circuit 34 and the π/4 phase shift circuit 35, and the signal f _S4 =
cos(ω ₁ t−π/4) and f _s5 =cos(ω ₁ t+π/4) are supplied to the second and third multiplication circuits 36 and 37, and these multiplication circuits 36 and 37 and the bandpass filter 38 ，
39 performs synchronous detection, and L channel signals and R channel signals are obtained at output terminals 40 and 41, respectively. In this way, the stereo signal is demodulated by the demodulation circuit shown in FIG.

In the well-known Motorola AM stereo transmission system, stereo signals are generated and demodulated as described above, but in actual receivers, it is not sufficient to simply be able to receive stereo signals; It is also necessary to be able to automatically switch between stereo and monaural depending on the situation, and to display the switching.
It is necessary to be able to control the stereo operating state when the input signal weakens and the S/N ratio deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a Motorola type AM stereo demodulation circuit of this type that can add necessary functions such as switching between stereo and monaural with a simple configuration.

In order to achieve this objective, the present invention extracts an output according to a stereo identification signal from a PLL circuit necessary for AM stereo signal demodulation, and switches between stereo and monaural using this output and a signal according to the strength of the input signal. The present invention is characterized in that the demodulation operation is switched between stereo and monaural recording by changing the phase of a signal serving as a reference for demodulation.

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 5, parts equivalent to or identical to those of the AM stereo demodulation circuit in FIG. 4 are given the same numbers, and detailed explanation thereof will be omitted.

In the figure, 42 is the high frequency part of the receiver, 43
is an intermediate frequency amplification stage, 44 is a rectifier circuit, 45, 4
6 and 47 are components of the PLL circuit 32, 45 is a phase comparator, 46 is a low-pass filter, and 47 is a voltage controlled oscillator. 48 and 49 are adder circuits, 50 is a switch circuit, 51 is an AND circuit, 52 is a changeover switch, 53 and 54 are its contacts, 55 is a power supply, and 56
57 is a lamp driver circuit, and 57 is a stereo display lamp.

Next, its operation will be explained.

The stereo signal e _c1 from the intermediate frequency amplification stage 43 is and the signal e obtained at the output of the divider circuit 28
_c2 is This is as explained in connection with FIG. This signal e _c2 is applied to the second and third multiplier circuits 3
6, 37, and the other input receives the signal sinω ₁ t from the PLL circuit 32.
The signal cosω ₁ t phase-shifted by 3 is sent to the first adder circuit 4.
8, is supplied via the second adder circuit 49.

Furthermore, these first and second adder circuits 48, 49
The other input of is connected to the PLL via the switch circuit 50.
The signal sinω ₁ t from the voltage controlled oscillator 47 of the circuit 32
and −sinω ₁ t are respectively supplied, and when the switch circuit 50 is closed, these adder circuits 4
Signals f _s4 and f _s5 are obtained at the outputs of 8 and 49.

f _s4 = cosω ₁ t + sinω ₁ t = √2cos (ω ₁ t-π/4) f _s5 = cosω ₁ t-sinω ₁ t = √2cos (ω ₁ t + π/4) These synchronization signals f _s4 , f _s5 is supplied to multiplication circuits 36 and 37, and the multiplication circuit 36 multiplies the stereo signal e _c2 and the synchronization signal f _s5 to produce the next signal. appears at the output of multiplication circuit 36, which, when passed through bandpass filter 38, produces a signal e _R at output terminal 40.

e _R =k/2·R This signal e _R consists only of the signal component of the R channel.

Similarly, the output of the multiplication circuit 37 is passed through the bandpass filter 3.
₉ , a signal e _L is obtained at the output terminal 41, and a signal of the L channel can be obtained.

Now, the input of the AND circuit 51 is the PLL circuit 32.
The output of the low-pass filter 46, the output of the rectifier circuit 44, and the output from the changeover switch 52 are supplied, and the output of the AND circuit 51 is used to connect the switch circuit 50.
is about to be closed.

The switch 52 is used to manually switch the operation of the receiver between stereo and monaural. When the contact is switched as shown in the figure, the switch is switched to stereo, and the voltage from the power supply 55 is switched to stereo.
It is supplied to one input of the AND circuit 52.

Further, from the rectifier circuit 44, the intermediate frequency amplification stage 4
A DC voltage corresponding to the level of the intermediate frequency signal from 3, that is, the level of the input signal, is supplied to the other input of the AND circuit 51.

Therefore, if the input signal is the stereo signal e _c as described above, the stereo identification signal P is included therein. Since this stereo identification signal P is selected to have a lower frequency than the L channel and R channel signals, if the time constant of the low pass filter 46 of the PLL circuit 32 is selected to a predetermined value, the input signal The low-pass filter 46 to the AND circuit 5 only when the identification signal P is included.
1 can be supplied with a signal of a predetermined level.

That is, the stereo identification signal P is selected to be, for example, 25 Hz, and on the other hand, the lower limit of the L channel and R channel signals is about 50 Hz, so the time constant of the low pass filter 46 is set to a predetermined value. By selecting the cutoff frequency as
If it is set between 50Hz and 25Hz, a signal of a predetermined level can be supplied from the low-pass filter 46 to the AND circuit 51 only when the stereo identification signal P is included in the input signal. .

Note that at this time, since the cutoff frequency of the low-pass filter 46 necessary for the operation of the PLL circuit 32 is also 50 Hz or higher, there is no possibility that the original operation of the PLL circuit 32 will be affected.

Therefore, the input signal is a stereo signal e _c ,
Furthermore, all inputs to the AND circuit 51 are "1" only when the input level is maintained above a predetermined value.
(Of course, it is assumed that the switch 52 is switched to stereo), the output of the AND circuit 51 also becomes "1", and the switch circuit 50 is activated to close it, and the PLL circuit 32 is sent to the adder circuits 48 and 49. The signals sinω ₁ t and −sinω ₁ t are supplied to maintain the demodulation operation in a stereo state.

At the same time, the output of the AND circuit 51 is also supplied to the lamp driver circuit 56, so that the stereo indicator lamp 57 lights up to indicate that the stereo operating state is present.

In this state, if the input signal changes from a stereo signal to a monaural _signal , it does not include the stereo identification signal P, so the PLL
The output from the low-pass filter 46 of the circuit 32 is below the level that operates the AND circuit 51,
The output of the AND circuit 51 becomes "0".

When the output of the AND circuit 51 becomes "0", the switch circuit 50 is opened, and only the signal cosω ₁ t, which has been supplied via the phase shift circuit 33, is supplied from the addition circuits 48 and 49 to the multiplication circuits 36 and 37. , as a result, synchronous detection is performed, and the same output signal k(L+R)/√ is output to the output terminals 40 and 41.
2 appears and automatically switches to monaural reception mode.

At the same time, the signal applied to the lamp driver circuit 56 also becomes "0", so the lamp 57 also goes out, indicating that the system is in a monaural state.

Furthermore, when the level of the input signal decreases due to a decrease in electric field strength, the output of the rectifier circuit 44 also decreases, and the level of the input to the AND circuit 51 also decreases, and when it falls below a predetermined value, the AND circuit 51
The ON condition is no longer maintained and the output becomes “0”
become. Therefore, when the level of the input signal decreases and the necessary S/N cannot be maintained in the stereo reception state, the stereo signal is automatically switched to monaural mode.

That is, even if the selector switch 52 is set to stereo, if the input signal is no _longer a stereo signal, the level of the input signal falls below a predetermined value, or these two conditions occur simultaneously, the AND circuit The output of 51 becomes "0", the Sderes display lamp 57 goes out, and
The switch circuit 50 opens and the multiplication circuits 36 and 37
The reference signals f _s4 and f _s5 become signals cosω ₁ t, so that only the monaural signal component {1+k(L+R)}cosω ₁ t of the stereo signal f ₁ (t), or only the original monaural signal can be synchronously detected. output terminals 40, 41
The same signal k(L+R)/2 is obtained, resulting in a monaural state.

When the changeover switch 52 is switched to monaural, the signal applied from the switch 52 to the AND circuit 51 is always kept at "0", so the monaural reception state is maintained regardless of other conditions until I explain. Nor.

As explained above, according to the present invention, it is possible to provide an automatic switching function between stereo and monaural to a Motorola AM stereo demodulation circuit with a simple configuration, and it is possible to display stereo and monaural operation. At the same time, it is possible to perform an operation that sufficiently copes with deterioration of S/N in a weak electric field or the like.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of an AM stereo signal transmission section using the Motorola system, Figs. 2 and 3 are vector diagrams for explaining its operation, and Fig. 4 is demodulation on the receiving side of an AM stereo signal using the Motorola system. Block diagram showing an example of the circuit, No. 5
The figure is a block diagram showing an AM stereo demodulation circuit according to an embodiment of the present invention. 32... PLL circuit, 36, 37... Multiplication circuit, 38, 39... Bandpass filter, 43... Intermediate frequency amplification stage, 44... Rectifier circuit, 45... Phase comparator, 46... Low pass filter 47...voltage controlled oscillator, 48, 49...addition circuit, 50...switch circuit, 51...AND circuit, 52...changeover switch, 56...lamp driver circuit, 57...stereo display lamp.

Claims (1)

[Claims] 1. In an AM stereo signal demodulation circuit using an amplitude one-angle modulation method that transmits stereo signal information by amplitude modulating a carrier wave using stereo sum (L+R) signal information and phase modulating using stereo difference (L-R) signal information, a PLL circuit that generates a first reference signal with a phase shift of π/2 and a second reference signal with a phase shift of −π/2 in synchronization with a carrier wave; a first addition circuit which receives as input a third reference signal whose phase has been shifted by −π/2;
a second reference signal and a third reference signal as inputs.
an adding circuit; a switching means for switching on and off the respective supply states of the first and second reference signals to the first and second adding circuits;
An AND circuit is provided which receives three types of signals as input: an output signal of a low-pass filter included in the PLL circuit, a control signal representing the reception level of the carrier wave, and a control signal that can be manually selected to give a binary level, The outputs of the first and second adder circuits are respectively supplied as synchronization signals for separating the left (YL) signal and the right (R) signal from the stereo signal, and the output of the AND circuit is used to control the switching circuit off. characterized in that it is configured to be supplied as a signal.
AM stereo signal demodulation circuit.