JPS6130112A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To use a D.RAM efficiently and to obtain a maximum of two-fold delay time for the user of two channels by repeating read/write and stop of read/write of the D.RAM alternately in every half sampling cycle when one channel is used. CONSTITUTION:When digital data of one channel is delayed, low-level and high- level signals are outputted from inverters 39 and 40 respectively, and an NAND circuit 34 outputs a high-level signal when the output synchronizing signal of a frequency divider 31 is in the high level, and the circuit 34 outputs the output signal of a waveform shaping and differentiation circuit 30 only when said output synchronizing signal is in the low level. A D.RAM address count control circuit 37 generates address signals A0-A7 only when the synchronizing signal is in the low level, and the circuit 37 does not generate address signals when the synchronizing signal is in the high level, and these operations are repeated alternately. Consequently, only digital data of one channel on a digital data transmission line of two channels is subjected to A/D conversion and D/A conversion and is written in and read from the D.RAM in the sampling cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital delay circuit, and more particularly to a digital delay circuit that delays one or two channel digital signals by a desired time using a digital memory circuit.

Conventional technology Digital delay circuits have been used for various purposes. For example, when applied to a reverberation sound adding device, an analog shift register such as a BBD (packet pre-gate device) is used as a delay circuit. Compared to the above, it is possible to improve the signal-to-noise ratio (S/1), frequency characteristics, distortion rate, dynamic range, and other characteristics. FIG. 7 shows a block diagram of an example of a reverberation sound adding device having this digital delay circuit. In the figure, the analog audio signal of the first channel inputted to the input terminal 1a passes through a buffer amplifier 2a and a low-pass filter 3a, respectively, and is then connected to an A/D integration circuit 4a and a 16-bit A/D conversion section 5a, for example, in cascade. The data is sampled and quantized by an integral type A/D conversion circuit (the timing of sampling is determined by a conversion command from terminal CC1 of the control circuit 6), and is converted into a digital signal of, for example, 32 bits per sampling point. After the data (sampling frequency, e.g. 44.056 kHz >) is converted, the data input tJ@child[), I
applied to N. On the other hand, the analog audio signal of the second channel enters the input terminal 1b, and in the same manner as above, it is connected to the buffer amplifier 2b, the low-pass filter 3b, the A/D integration circuit 4b, and the 16-bit A/D converter 5b (the The sampling timing is determined by a conversion command from the terminal CG2 of the control circuit 6.

1, applied to N. The control circuit 6 receives two channels of input digital data alternately for each channel and in a time-division manner every half period of the sampling period.

The control circuit 6 includes n dynamic random access memories (D, RAM) (where n is any natural number).
71 to 71 first stage paste, serially to RAM7I 3 above
2-bit digital data is sent to its output terminals, D and O.
Read/write cycle time from UT (e.g. 20μs)
It also outputs an 8-bit address signal to D and RAM 7+ to 7η, and also outputs a write control signal WE and strobe signals RAS and CAS, respectively. The digital data is delayed by sequentially transferring each address of RAM 7+ to 7Tl, but 64
The delay time τ for bit D and one RAM is - the number of quantization pits at the sample point is X.

If the read/write cycle time is t (seconds), then (
28X28 )X t/X (unit: second).

The delay time can be controlled by using the data selector 8 to select any one of D, RAM7+ to 7Tl,
The first method is to output a combination of the outputs of the RAM, the second method is to control the combination of 8 bits of row address and 8 bits of column address with switch 9, and the second method is to control the combination of 8 bits of row address and 8 bits of column address with variable resistor 10.
There is a third method in which the frequency of K is controlled to change the period of the read/write cycle. The digital data delayed by the desired time in this way is inputted to the input terminal D and IN of the control circuit 6, and is further input to the 16-bit D/A converter 11 and the output terminal OUT via the control circuit 6. The signal is supplied to, for example, a simultaneous integration type D/A conversion circuit consisting of a D/A integrator/glitch circuit 12, where it is converted back into an analog signal.

The delayed analog audio signal taken out from the D/A integrator/glitch circuit 12 is sent to switch circuits 13 and 14.
are supplied respectively. The symmetric square wave with a sampling period extracted from the 16-bit D/A converter 11 is directly supplied to the switch circuit 13, while the symmetric square wave with the opposite phase is supplied to the switch circuit 14, which samples them. It is turned on and off alternately every half of the cycle. As a result, the delayed analog audio signal of the first channel is taken out from the switch circuit 14, and is passed through the low-pass filter 16a, the buffer amplifier 17a, and the variable resistor 18a.

The signals are supplied to the buffer amplifier 2a through the amplifiers 19a, where they are mixed with the original analog audio signal from the input terminal 1a. On the other hand, the delayed analog audio signal of the second channel is taken out from the switch circuit 13, and is applied to the low-pass filter 16b and the buffer amplifier 1 in the same manner as above.
7b, a variable resistor 18b, and an amplifier 19b. Thereafter, the same operation as above is repeated, and a multiplexed signal of the delayed analog audio signal and the original analog audio signal is outputted to the output terminals 20a and 20b for each channel.

Problems to be Solved by the Invention However, in the above device, when attempting to add an analog audio signal with a desired delay time to a 1-channel analog audio signal (when using 1 channel), the above 2-channel analog audio signal is Similar to when processing signals simultaneously, A/D conversion circuit.

Each operation of the D/A conversion circuit and control processing of RAM 7+ to 7η are performed by the output bit clock B of the control circuit 6,
Do everything in phase synchronization with CLK! Therefore, the data processing speed per channel of D and RAM 7+ to 7Tl is twice the A/D and D/A conversion cycle (that is, half the sampling period). Therefore, during half of the read/write cycle time when one channel is used, D and RAM 7+ to 7η do not contribute to the actual delay of digital data, and their storage capacity is not used at 100%. First, there was the problem that it was uneconomical.

Therefore, the present invention provides a digital delay circuit that solves the above problems by alternately repeating writing and reading of RAM and stopping its operation every half period of the sampling period when one channel is used. The purpose is to

Means for Solving the Problems Figure 1 is a block diagram showing the configuration of the main parts of the present invention.
A circuit corresponding to a main part of the control circuit 6 shown in the figure is shown. The digital delay circuit includes first and second A/D conversion circuits and a single D/A conversion circuit.

It is roughly composed of first and second switch circuits that distribute the D/A conversion output into two systems, n glues, digital memories such as RAM, and a control circuit that controls these.
The configuration is the same as that in FIG. 7 except for the control circuit. In FIG. 1, a clock generator 25 generates and outputs a bit clock B, CLK of a constant frequency. Timing clock circuit 2
6 is supplied with a signal indicating whether the input digital data to be delayed to the digital memory circuit is 1 channel or 2 channels and a bit clock, and is synchronized with the bit clock and synchronized with the sampling period of the input digital data. It outputs pulses with equal periods and signals with different waveforms depending on the number of channels of input digital data. The control timing circuit 27 is a circuit that generates various clock pulses for controlling the A/D converter circuit and the D/A converter circuit, and is synchronized in phase with the pulses equal to the sampling period from the timing clock circuit 26, and is used to control the digital memory circuit. It generates a synchronization signal LRCK which becomes a reference clock for D/A converting the digital data of one or two channels read from first and second A/D conversion clock pulses AD-1 and AD-2 supplied to the conversion circuit, respectively, and first and second switches that distribute the output signal of the D/A conversion circuit into two systems; The first and second pulses DA- serve as switching signals for the circuit.
1 and DA-2 are generated and output, respectively. However, when the input digital data is one channel, the control timing circuit 27 generates and outputs pulses AD-1 and DA-1 (or AD-2 and DA-2) together with the synchronizing signal LRCK and the bit clocks B, CLK. , pulse AD-2 and DA-2 (or AD-1 and DA-1)
are not generated and output respectively.

Furthermore, the read/write control circuit 28 is supplied with signals according to the number of channels from the timing clock circuit 26, generates and outputs the write/read control signals RAS, CAS, and WE for the digital memory circuit, and also outputs the write/read control signals RAS, CAS, and WE of the digital memory circuit. 7) outputs address signals AD to Atn. However, in the present invention, the input digital data is
When it is a channel, the address signal AO, -ATI+
are generated and output sequentially every half period of the sampling period, and on the other hand, when the input digital data is one channel, the address signals AO to ATr are generated every half period of the sampling period.
The generation of l and the pause in its generation are repeated alternately. In addition,
When generation of the address signal is stopped, the generation of the write/read control signal is also stopped.

When the action input digital data is one channel, the first
Address signals and write/read control signals are generated and output only when the digital data of the (or second) channel is synchronized, and generation of the address signals and write/read control signals is suspended when the second (or first) channel is synchronized. , the digital memory circuit is the first (or second)
Writing and reading operations are performed only during channel synchronization, and operations are performed at a sampling period synchronized with the input digital data of one channel, making it possible to efficiently use 100% of the storage capacity of the digital memory circuit. Hereinafter, the circuit of the present invention will be explained along with examples.

Embodiment FIG. 2 shows a circuit system diagram of essential parts of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 1 are given the same reference numerals. In FIG. 2, a clock generator 25 generates and outputs a symmetrical square wave of, for example, 1.5 MHz, and outputs this as a bit clock B, CLK through a control timing circuit 27. Differentiator circuit 30 and 1/32 frequency divider 3
1, respectively. The waveform shaping/differentiating circuit 30 generates a narrow pulse that falls in phase synchronization with, for example, the falling edge of the bit clock B, CLK, and supplies this pulse to one input terminal of the NANO circuit 34. Further, the 1732 frequency divider 31 generates a pulse with a period equal to the sampling period of the digital data to be delayed, and supplies this pulse to the other input terminal of the NAND circuit 34 through the OR circuit 33. The signal is supplied to the /A conversion control circuit 35, and further passed through the control timing circuit 27 and outputted as a synchronization signal LRCK as shown in FIG. 3(C) and FIG. 5(A>).

The 1-channel/2-channel control circuit 32 is
This circuit generates signals according to the number of channels, and includes two switches 81 + 82 + exclusive OR circuit 38. Consisting of inverters 39 and 40, when there are two channels of digital data to be delayed, switches S1 and S2 are both turned on, and when there is one channel of data to be delayed,
And when it is the first channel, only switch S1 is on.

For the second channel, only switch S2 is turned on. First, to explain the case of delaying the digital data of two channels, the 1-channel/2-channel control circuit 32 receives a higher level signal than the inverter 39 because the switches S+ and 82 are both turned on. Supplied to the OR circuit 32 and inverter 4
A signal with a higher level than 0 is supplied to the exclusive OR circuit 41.

As a result, the signal supplied from the OR circuit 33 to the NAND circuit 34 is always at a high level. This allows the NA
A pulse having the opposite phase to the output pulse of the waveform shaping/differentiation circuit 30 is taken out from the ND circuit 34, and constitutes the read/write control circuit 28.

RAM read/write control circuit 36 and R
The signals are supplied to the AM address counter control circuit 37, respectively.

As a result, the RAM read/write control circuit 36 controls the bit clock B, shown in FIG.
The strobe signal RAS shown in (B) of the same figure, the strobe signal CAS shown in (D)' of the same figure, and the write signal shown in (E) of the same figure, which are phase synchronized with CLK, respectively. II control signal WE, a signal WE having an opposite phase to this signal, and an XY address signal that determines the output timing of the row address and column address are respectively output. Also, at the same time, the circuit 37
Bit address signals An-A7 are respectively output in parallel. This address signal Ao''Ay is a signal indicating 8 bits of row address or 8 bits of column address, and the circuit 37 receives 8 bits of row address and 8 bits of column address in approximately half the sampling period as shown in FIG. 3(D). 8 bits alternately, and
Output 32 times in total. In other words, the address of the RAM is determined by 8 bits of the row address and 8 bits of the column address, and changes sequentially 16 times in approximately half the sampling period, so the address counter (not shown) counts 16 times. .

When the strobe signal RAS falls as shown in FIGS. 4(B) and 4(C), the 8-bit row address signal is input to the D and RAM, and the strobe signal CΔS is input as shown in FIG. 4(D). When it falls, the column address signal 8 bits are input, and after the strobe signal @CAS falls, the constant Ft
After f time, the write control signal WE falls as shown in the same layer (E), and the input digital data is transferred to the above column address 8.
Before writing to the address specified by the 8-bit row address and the 8-bit row address, the digital data previously stored at the same address is read out.

In addition, the reliability shown in FIGS. 4(F) and (G), RAM
A signal read from D, and input digital data supplied to the RAM are shown, respectively. Further, the bit clock B shown in FIG. 4(A).

The numerical value at the top of the CLK waveform indicates the generation timing of the bit clock B, C[K multiplied by 8 tJ゛.

Further, the A/D and D/A conversion control circuits 35 have the same sampling period and mutually opposite phases as shown in FIG. 3(A).
The first and second A/D conversion clock pulses AD-1 and AD-2 as shown in FIG.
(E) in the same figure.
, and generate and output first and second pulses DA-1 and DA-2 as shown in (F), respectively. The two A/D conversion circuits (corresponding to 4a and 5b in Figure 7) to which two channels of digital data are supplied separately are clock pulses AD-1,
The input analog signal is sampled and quantized in one sampling period from the rising edge of AD-2 to the next rising edge. Here, clock pulses AD-1 and AD-2 are shown in FIG. 3(A).
As can be seen from ,(B), since they are in opposite phases, the two A/D variable circuits are shifted by half a period of the sampling period A.
/D conversion operation is performed. In addition, the first and second pulses D
A-1 and DA-2 are each a D/A converter (11 in FIG.
) is applied as a switching signal to two switch circuits (corresponding to 13.14 in Figure 7) provided at the output end of the D/A conversion circuit, and is turned on during the high level period, and , is off during the low level period. As a result, it is possible to perform a desired delay of two channels of digital data, similar to the conventional method described with reference to FIG.

Next, to explain the case where the input digital data is 1 channel, in this case, the 1 channel/2 channel control circuit 32 turns on the switch S1 and turns off the switch S2 when the digital data of the 1 channel is the first channel. It is said that In addition, when the digital data of the first channel is the second channel, the switch S1 is turned off.
Switch S2 is turned on. Now, assuming that the digital data of the first channel is delayed, a low level signal is output from the inverter 39, and the inverter 40 outputs a low level signal.
A higher level signal is output.

Therefore, from the exclusive logic conjunction circuit 41, the 1/32 frequency divider 3
Since a pulse with the opposite phase to the output pulse of 1 is taken out, and the output signal of the inverter 39 is at a low level, the signal supplied from the OR circuit 33 to the NAND circuit 34 is 1/3
The pulse has a phase opposite to the output pulse of the frequency divider 31. Therefore, the NAND circuit 34 is 1/32 as shown in FIG. 5(B).
During the high level period of the synchronization signal LRCK, which is the output of the frequency divider 31, a high level signal is always output, and the synchronization signal LR,
The output signal of the waveform shaping/differentiation circuit 3° is gated out only during the low level period of GK. As a result, the DRAM read/write control circuit 36 writes and reads only during the low level period of the synchronizing signal LRCK, and does not generate and output this control signal during the high level period of the synchronizing signal LRCK. Further, the A/D and D/A conversion control circuit 35 is shown in FIG.
The first clock pulse AD-1 as shown in A) and the first clock pulse AD-1 as shown in FIG.
D) only the first pulse DA-1 is generated, and the second clock pulse AD-'2 and the second pulse DA-2 are generated as shown in FIG.
and no output is generated.

Further, the DRAM address counter control circuit 37 generates the address signal Ao=A7 only during the low level period of the synchronizing signal LRCK, as shown in FIG. 5(C),
During the next high level period, not generating and outputting the address signal is repeated alternately.

As a result, of the two channels of digital data transmission path, only the digital data of one channel is
D, D/A conversion is performed, and data is written to and read out from D, RAM at the sampling period.

Note that when delaying the digital data of the second channel, the switch S1 is turned off and the switch S2 is turned on, so that the output signal of the inverter 39 is at a low level, and the output signal of the inverter 40 is at a low level. . Therefore, a signal in phase with the synchronizing signal LRCK (shown in FIG. 6(B)), which is the output signal of the 1/32 period 31, is taken out from the exclusive OR circuit 41 and passed through the OR circuit 33 to the NAND circuit 34. supplied to Therefore, in this case,
As can be easily inferred from the above explanation, the synchronization signal LR
During the high level period of CK, the address signal An-A7 is generated as shown in FIG. 6(C), and the second clock pulse AD-2 as shown in FIG. 6(A) and the second clock pulse AD-2 as shown in FIG. 6(D) are generated. A second clock pulse DA-2 as shown is generated and output.

It goes without saying that the present invention can also be used for applications other than the reverberation sound adding device.

Effects of the Invention As described above, according to the present invention, in a circuit that delays two channels of digital data separately for a desired time, one
For digital data in a channel, the same delay time can be obtained with half the amount of memory when using 2 channels. Therefore, by using the digital memory circuit 100% efficiently, the delay time can be up to twice as much as when using 2 channels. It has features such as being able to obtain delay time.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing the main part of the configuration of the circuit of the present invention, FIG. 2 is a circuit system diagram showing the main part of an embodiment of the circuit of the invention, FIGS. 3, 4, 5, and FIG. 6 is a signal waveform diagram for explaining the operation of the circuit of the present invention, and FIG. 7 is a block system diagram showing an example of a two-channel reverberation sound adding apparatus to which the circuit of the present invention can be applied. 1a, 1b...Analog audio signal input terminal, 4
a, 4b...A/D integration circuit, 5a, 5b-
16-pit A/D converter, 6...control circuit, 71-7
η...Dynamic random access memory←
D, RAM), 11...16-bit D/A converter,
12...D/A integrator/glitch circuit, 20a. 20b...analog audio signal output terminal, 25.
... Clock generator, 26... Timing clock circuit, 27... Control timing circuit, 28...
・Read/write control circuit, 30...Waveform shaping/differentiation circuit, 31...1/32 frequency divider, 32...1 channel/2 channel control circuit, 35...A/
D. D/A conversion control circuit, 36...D, RAM read/write control circuit, 37...D, RAM
Address counter control circuit.

Claims (1)

[Claims] A/D converts 1-channel or 2-channel analog signals
One or two channels of digital data sampled and quantized by a conversion circuit is sequentially written to and read from a digital memory circuit through each address, thereby generating delayed digital data from the memory circuit. In a digital delay circuit that outputs a bit clock to a D/A conversion circuit, a clock generator that generates and outputs a bit clock of a constant frequency, a signal indicating whether the input digital data is 1 channel or 2 channels, and the bit clock are respectively supplied. a timing clock circuit that is synchronized with the bit clock and outputs a pulse having a period equal to the sampling period of the input digital data, and a signal having a different waveform depending on the number of channels of the input digital data; A synchronization signal is synchronized in phase with the pulse from the timing clock circuit, and is used as a reference clock to cause the D/A conversion circuit to D/A convert the 1 or 2 channels of digital data read from the memory circuit. At the same time, when the input digital data is of two channels, the first and second A/D conversion clock pulses for obtaining two channels of digital data and the delayed analog signals of two channels are outputted from the D/A conversion circuit. The first pulse is used as a switching pulse for a switch circuit that distributes output from the end.
and a second pulse, respectively, and when the input digital data is of one channel, a control timing circuit that generates and outputs only the first or second A/D conversion clock pulse and the first or second pulse. Then, the timing clock circuit supplies a signal according to the number of channels, and when the input digital data is 2 channels, it generates and outputs a write/read control signal for the digital memory circuit, and also outputs an address signal for the digital memory circuit. Sequentially generates and outputs the write/read control signal and address signal approximately every half period of the sampling period, and when the input digital data is one channel, generates and outputs the write/read control signal and the address signal and stops generating the signal approximately every half period of the sampling period. A digital delay circuit characterized by consisting of an alternating read/write control circuit.