JPS61295715A - Frequency presetting device - Google Patents

Frequency presetting device

Info

Publication number
JPS61295715A
JPS61295715A JP13961885A JP13961885A JPS61295715A JP S61295715 A JPS61295715 A JP S61295715A JP 13961885 A JP13961885 A JP 13961885A JP 13961885 A JP13961885 A JP 13961885A JP S61295715 A JPS61295715 A JP S61295715A
Authority
JP
Japan
Prior art keywords
circuit
switch
voltage
tuning
tuning voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13961885A
Other languages
Japanese (ja)
Inventor
Hiroshi Kondo
浩 近藤
Norio Abe
安部 紀夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13961885A priority Critical patent/JPS61295715A/en
Publication of JPS61295715A publication Critical patent/JPS61295715A/en
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To constitute a frequency presetting device at low cost and reduce its secular change, and to vary a tuning speed continuously by leading a desired tuning voltage out by the charging and discharging of an integration circuit through the selection of the 1st of the 2nd switch circuit and supplying it to a voltage control channel selecting circuit. CONSTITUTION:When the switch part 61 of the 1st switch circuit 6 is pressed, the integration circuit 9 consists of a resistance part 62 and a capacitor 8 and a charging speed is set freely by varying pressing force and increasing and decreasing a resistance value. When the output voltage of this integration circuit 9, i.e. tuning voltage reaches a desired value, is held at it is by opening the switch part 61 and the tuning voltage is digitized by the voltage control channel selecting circuit 2 through the operation of an external switch 5 and stored in a memory circuit 3. When the tuning voltage is lowered, the switch part 71 of the 2nd switch circuit 7 is pressed and the integration circuit 9 is composed of a resistance part 72 and capacitor 8 and discharge to an earth terminal.

Description

【発明の詳細な説明】 〔韮栗上の利用分野〕 この発明はテレビジョン受像機における周波数プリセッ
ト装置、特にそのプリセット操作の簡略化に関するもの
である 〔従来の技術〕 第2図は例えば三ix機製カラーテレビCT−2228
F’MをもってすでKfi品化さCた促米の周波数プリ
セット装置を示す回路図でめり2図において(1)は直
流電圧供給端子■及び多回転可変抵抗器VRからなる周
波数プリセット回路でろり、可変抵抗器VRから所望の
チューニング電圧を4出する。(2)はこのチューニン
グ電圧を受ける例えば乗積回路等により構成さA、6電
圧制御選局回路。
[Detailed Description of the Invention] [Field of Application] This invention relates to a frequency presetting device in a television receiver, and particularly to simplifying the presetting operation thereof [Prior Art] Fig. 2 shows, for example, Machine color TV CT-2228
In Figure 2, there is a circuit diagram showing the frequency presetting device of the C-produced rice that has already been made into a Kfi product with F'M. (1) is the frequency presetting circuit consisting of the DC voltage supply terminal ■ and the multi-rotation variable resistor VR. Then output the desired tuning voltage from the variable resistor VR. (2) A, 6 voltage control channel selection circuit which receives this tuning voltage and is constituted by, for example, a multiplication circuit.

(3)はこの電圧制御選局回路の出力を記憶するメモリ
回路、(41はこのメモリ回路の記憶イ直を選出するチ
ューナ、151は上記電圧制御、l!!1局回路(2)
を制御する外部式カスインチである。
(3) is a memory circuit that stores the output of this voltage control channel selection circuit, (41 is a tuner that selects the memory channel of this memory circuit, 151 is the above voltage control, l!!1 station circuit (2)
It is an external type control unit.

第2図の動作について説明する。周波数プリセット回路
(1)は、上記のように多回転可変抵抗器VRによυ構
成さn2周波数をプリセットするときKは、この可変抵
抗器VRを回転させて所望のチユーニング電圧を導出す
る。このチューニング電圧に、電圧制御選局回路+21
 K入力さnてデジタルに換さn、このデジタル値が外
部式カスインチ(5)を操作することによりメモリ回路
(3)に記憶される。
The operation shown in FIG. 2 will be explained. The frequency preset circuit (1) is composed of the multi-rotation variable resistor VR as described above. When presetting the n2 frequency, K rotates the variable resistor VR to derive a desired tuning voltage. To this tuning voltage, voltage control channel selection circuit +21
The K input is converted into a digital value, and this digital value is stored in the memory circuit (3) by operating an external type input (5).

そしてチューナ(4)によりこのメモリ回路(3)の記
憶値が選出さnることになる。
Then, the value stored in this memory circuit (3) is selected by the tuner (4).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の周波数プリセット装置は、上記のように多回転可
変抵抗器VRを用いるものとしているので、可変抵抗器
の微妙な操作がむずかしいうえ。
Since the conventional frequency presetting device uses the multi-rotation variable resistor VR as described above, delicate operation of the variable resistor is difficult.

選局速度が遅く、したがって周彼ya?:n確にプリセ
ットするのに時間がかかるという問題点があった。
The selection speed is slow, so Zhou Heya? :nThere was a problem that it took time to set the preset accurately.

この発明はこのような問題点を解決するためになさtた
もので1周波数プリセット用可変抵抗器を不安とすると
ともに、操作が簡単でしかも周波数をプリセットする時
間を短縮できる周波数プリセット装置を得ることを目的
とする。
The present invention has been made to solve these problems, and it is an object of the present invention to provide a frequency presetting device that is easy to operate and shortens the time required to preset the frequency, while making the variable resistor for single frequency presetting unreliable. With the goal.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る周波数プリセット装置は、押圧力に応じ
て抵抗値が変化する第1及び第2のスイッチ回路を設け
、第1のスイッチ回路の一端を直流電圧供給端子に、第
2のスイッチ回路の一端をアース端子に接続し、他方谷
スイッチ回路の他端を共通のコンデンサに接続して積分
回路を構成しこの積分回路の出力端子からチューニング
電圧を導出するものとした。
The frequency presetting device according to the present invention includes first and second switch circuits whose resistance value changes depending on the pressing force, one end of the first switch circuit being a DC voltage supply terminal, and one end of the second switch circuit being a DC voltage supply terminal. One end was connected to the ground terminal, and the other end of the valley switch circuit was connected to a common capacitor to form an integrating circuit, and the tuning voltage was derived from the output terminal of this integrating circuit.

〔作用〕[Effect]

この発明においてに、第1のスイッチ回路を選択するこ
とにより積分回路は充電さn、第2のスイッチ回路を選
択することにより積分回路に放電さnる。しかも各スイ
ッチ回路に押圧力に応じて抵抗値が変化するものとなっ
ているから、積分回路の光電または放電時間を任麓に加
減でき、したがって所望のチューニング電圧を得る時間
を自在に変化させることができる。
In this invention, by selecting the first switch circuit, the integrating circuit is charged, and by selecting the second switch circuit, the integrating circuit is discharged. Moreover, since each switch circuit has a resistance value that changes according to the pressing force, the photoelectric or discharge time of the integrating circuit can be adjusted at will, and therefore the time to obtain the desired tuning voltage can be freely changed. Can be done.

〔発明の実施例〕[Embodiments of the invention]

第1図はこの発明の一実施例を示す回路図であり、(1
)〜(5)は上記従来装置と同一または相当するもの、
(6)は一端が直流電圧供給端子VK樋続さnた第1の
スイッチ回路であり、スイッチ部(61)とこのスイッ
チ部の押圧力に応じて抵抗値が変化する抵抗部(62)
によV構成さnている。(7)は一端がアース端子に接
続さnた第2のスイッチ回路でるv5スイッチ部(71
)とこのスイッチ部の押圧力に応じて抵抗値が変化する
抵抗部(72)により構成さnる。(8)に上記各スイ
ッチ回路(6+、 (71の他端に接続さn’tc共通
のコンデンサでcbり、上記抵抗部(62)または(7
2)とによ!llll回分回路)を構成している。
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
) to (5) are the same as or equivalent to the above conventional device,
(6) is a first switch circuit whose one end is connected to the DC voltage supply terminal VK, and includes a switch part (61) and a resistor part (62) whose resistance value changes depending on the pressing force of this switch part.
It is composed of V. (7) is a V5 switch part (71) which is a second switch circuit whose one end is connected to the ground terminal.
) and a resistance part (72) whose resistance value changes depending on the pressing force of this switch part. (8) is connected to each of the above switch circuits (6+, (71) with a common capacitor connected to the other end of the above resistor section (62) or (7).
2) Toyo! 1llll batch circuit).

第1図において、鵠1のスイッチ回路(61のスイッチ
部(61〕を押圧したときは、M分回路(9)は抵抗部
(62)とコンデンサ(8)によV構成さし、直流電圧
供給端子■から光電さ匹、しかも充電速度はスイッチ部
(61)の押圧力を変化させ、抵抗部(62)の抵抗値
を加減することにより自由に設定できる5、この積分回
路(9)の出力電圧つまクチューニング電圧が所望値に
達したとき、スイッチ部(61)を開放すnば、その電
圧はそのまま保持さn、外部式カスインチ(5)の操作
により、電圧制御選局回路(2)がそのチューニング電
圧をデジタル変換し、このデジ麿ル値をメモリ回路(3
)に記憶させる。チューニング電圧を下げるには、第2
のスイッチ回路(7)のスイッチ部(71)’&弁押圧
て、、ljt分回路(9)を抵抗部(72)とコンデン
サ(8)により構成し、アース端子へ放電することによ
り行わnる。このときの放電速度はスイッチ部(71)
の押圧力を変化させ、抵抗部(72)の抵抗値を加減す
ることによジ自由に設定できる。
In Fig. 1, when the switch circuit (61) of Mouse 1 is pressed, the M branch circuit (9) is configured as V by the resistor (62) and the capacitor (8), and the DC voltage is The charging speed can be freely set by changing the pressing force of the switch part (61) and adjusting the resistance value of the resistor part (62) 5. When the output voltage or tuning voltage reaches a desired value, if the switch section (61) is opened, the voltage is maintained as it is, and the voltage control tuning circuit (2 ) converts the tuning voltage digitally, and sends this digital value to the memory circuit (3
). To lower the tuning voltage, use the second
By pressing the switch part (71)'& valve of the switch circuit (7), the circuit (9) for ljt is constructed of a resistor part (72) and a capacitor (8), and is performed by discharging to the ground terminal. . The discharge rate at this time is the switch part (71)
The resistance value of the resistance part (72) can be freely set by changing the pressing force of the resistance part (72).

なお、上記直流電圧供給端子■には一定の@流電圧を供
給するほか、直流成分を含む脈動電圧を供帖するものと
しても同様の動作を行うことができる。
In addition to supplying a constant @ current voltage to the DC voltage supply terminal (2), the same operation can be performed by supplying a pulsating voltage containing a DC component.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によルば、所望のチューニング電
圧をスイッチの操作による積分回路の充放電ニより得る
ものとし、かつその速度をスイッチの押圧力により加減
できるものとしたから、装置を安価に構成できるととも
に経年変化を少なくすることができ、さらにプリセット
操作が簡単となるうえチューニング速度を無段階に変化
でき。
As described above, according to the present invention, a desired tuning voltage can be obtained by charging and discharging an integral circuit by operating a switch, and the speed can be adjusted by changing the pressing force of the switch, so that the device can be manufactured at low cost. In addition to being able to be configured to reduce aging, preset operations are easy and tuning speeds can be changed steplessly.

プリセット時間を短縮できるという効果を得ることがで
きる。
It is possible to obtain the effect that the preset time can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す回路図、第2図は従
来の周波数プリセット装置を示す回路図であり1図にお
いて(1)は周波数プリセント回路で(6)はスイッチ
部(61)と抵抗部(62)からなる第1のスイッチ回
路5(7)はスイッチ部(71)と抵抗部(72)から
なる第2のスイッチ回路、t81Uコンデンサ。 (9)&ユ槓分回路、■は厘流電圧供給端子、(2)は
電圧制御選局回路、(3)にメモリ回路である。 なお、谷図中同−符号は同一または相当部分を示す。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing a conventional frequency presetting device. In Fig. 1, (1) is a frequency precent circuit, and (6) is a switch section (61). The first switch circuit 5 (7) consists of a switch section (71) and a resistance section (72), and a second switch circuit consists of a switch section (71) and a resistance section (72), a t81U capacitor. (9) &Y branch circuit, (2) is a current voltage supply terminal, (2) is a voltage control channel selection circuit, and (3) is a memory circuit. Note that the same reference numerals in the valley diagram indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 所望のチューニング電圧を電圧制御選局回路を介してメ
モリ回路により記憶させる周波数プリセット装置におい
て、スイッチ部と抵抗部からなりスイッチ部の押圧力に
応じて抵抗部の抵抗値が変化する、一端がそれぞれ直流
電圧供給端子及びアース端子に接続される第1及び第2
のスイッチ回路と、これら第1及び第2のスイッチ回路
の他端に接続された、各抵抗部とにより積分回路を構成
する共通のコンデンサとからなる周波数プリセット回路
を備え、上記第1または第2のスイッチ回路の選択によ
る上記積分回路の充放電により、該積分回路から所望の
チューニング電圧を導出し、これを上記電圧制御選局回
路に供給するようにしたことを特徴とする周波数プリセ
ット装置。
In a frequency presetting device that stores a desired tuning voltage in a memory circuit via a voltage control tuning circuit, it consists of a switch part and a resistor part, and the resistance value of the resistor part changes according to the pressing force of the switch part. The first and second terminals are connected to the DC voltage supply terminal and the ground terminal.
and a common capacitor connected to the other ends of the first and second switch circuits and forming an integrating circuit with each resistor section, A frequency presetting device characterized in that a desired tuning voltage is derived from the integrating circuit by charging and discharging the integrating circuit by selecting a switch circuit, and supplies this to the voltage-controlled tuning circuit.
JP13961885A 1985-06-24 1985-06-24 Frequency presetting device Pending JPS61295715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13961885A JPS61295715A (en) 1985-06-24 1985-06-24 Frequency presetting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13961885A JPS61295715A (en) 1985-06-24 1985-06-24 Frequency presetting device

Publications (1)

Publication Number Publication Date
JPS61295715A true JPS61295715A (en) 1986-12-26

Family

ID=15249481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13961885A Pending JPS61295715A (en) 1985-06-24 1985-06-24 Frequency presetting device

Country Status (1)

Country Link
JP (1) JPS61295715A (en)

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