JPS61295642A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce FORBIDDEN regions, and to contrive to enhance wiring efficiency at a semiconductor integrated circuit device by a method wherein the gate electrode parts of transistors not being used at a CMOS gate array are used as signal wirings in place of second layer aluminium wirings. CONSTITUTION:A poly-silicon gate 7 is so formed as to make signal lines to be led out from both the edges of the gate thereof, the symbol 2 in the figure is an N<+> type diffusion layer and the symbol 3 is the GND (an aluminium wiring). A signal inputted from a first layer aluminium wiring 4a in the lateral direction passes through a poly-silicon layer connected to the gate contact 7, and transmitted to a first layer aluminium wiring 4e connected to a gate contact 8. Because the gate electrode parts are used like this without using second layer aluminium wirings, no FORBIDDEN region is generated. Accordingly, the second layer aluminium wirings 9a-9e in the longitudinal direction can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a data array (CMOS gate array) in which complementary MOS transistors are arranged in an array. It is related to the improvement of

[Conventional technology]

Generally, in a mask slice type CMOS gate array, a desired logic is constructed using a plurality of transistors out of a large number of transistors prepared in advance.

Figure 3 shows the NMO5 part of the CMOS. In the figure, 1 is a polysilicon gate, 2 is an n
10 is the drain or source of the diffusion layer. Also, 3 is GN
D (aluminum wiring), 4a to 4e are horizontal first layer aluminum wirings, 6 is a second layer aluminum wiring used only for vertical wiring, and 5a.

5b is the first layer aluminum wiring 4a and the second N aluminum wiring 6.
This is a through hole that connects the first N aluminum wiring 4a and 40. Note that the x mark in the figure indicates a grid.

In this way, in the conventional structure, the first M aluminum wiring 4a and the second N aluminum wiring 6 are connected by the through hole 5a, and the first layer aluminum wiring 4e and the second layer aluminum wiring 6 are connected by the through hole 5b. Connect first layer aluminum wiring 4a and 4e
Connect the 2nd M aluminum wiring 6! No other wiring can be used on I. In other words, vertical wiring prohibited zone (F
ORBIDDEN).

This will be explained in more detail using FIGS. 4 and 5.

FIG. 4 shows that second layer aluminum interconnections 9a and 9c are provided in the NMOS portion of FIG. 3, and FIG. 5 shows a cross section taken along the line v--v. In FIG. 5, the same symbols as in FIG. 4 indicate the same parts, 15 is a P-type well region, 1
4 is a gate insulating film, 11, 12, and 13 are interlayer insulating films, and 10 is a surface protection film.

As is clear from these figures, the first layer aluminum wiring 4a
Since the second layer aluminum wiring 6 is used to connect the lines 48 and 48, wiring corresponding to the vertical wirings 9a and 9c cannot be used in this portion.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional CMOS gate array, the first
Forbidden band CP because vertical second layer aluminum wiring is used to connect layer aluminum wiring.

There is a problem in that an RBIDDEN region) is formed, and other vertical wiring cannot be done within that region.

This invention was made in order to solve the above-mentioned problems, and provides a semiconductor integrated circuit device in which horizontal wiring can be connected without using the second JW aluminum wiring, that is, without creating a FORBIDDEN region. The purpose is to obtain.

Incidentally, in a conventional mask slice type CMOS gate array, MOS transistors that do not constitute logic cells are not used at all. Therefore, it is reasonable to connect each logic cell using these unused transistors, and it is considered that improvement in wiring efficiency can be expected.

[Means for solving problems]

Therefore, the semiconductor integrated circuit device according to the present invention is a CMOS
The gate electrode portions of unused transistors in the gate array are used as signal wiring instead of the second layer aluminum wiring.

[Effect]

In this invention, since the gate of a transistor that does not constitute a logic cell is used in place of the second layer aluminum wiring, a FORBIDDEN region is not created, other vertical wiring regions are increased, and wiring efficiency is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, reference numeral 1 denotes a polysilicon gate, and both ends thereof are shaped so that signal lines can be drawn out from both ends. 2 is n10 diffusion layer, 3 is GND (aluminum wiring), 4
a to 4f are horizontal first layer aluminum wirings. 7.8
is the gate contact, and gate contact 7 is the first
Layer aluminum wiring 4a and polysilicon (polysilicon gate 1) are connected, and gate contact 8 connects first layer aluminum wiring 4e and polysilicon.

In such a configuration, a signal input from the first layer aluminum wiring 4a passes through the polysilicon connected by the gate contact 7, and is transmitted to the first layer aluminum wiring 4e connected to the gate contact 8.

Unlike the conventional example, this embodiment is configured without using the second layer aluminum wiring, so a FORBIDDEN region cannot be formed.

This is shown in detail in FIG. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same parts, and 9a to 9C are vertical second layer aluminum wirings. As is clear from a comparison between FIG. 2 and FIG. 4, in the example of FIG. 4, the second layer aluminum wiring 6 is used to connect the first layer aluminum wiring 4a and 46, so Although other vertical wiring could not be done, in this embodiment, since the gate electrode portion is used for the wiring, the vertical second layer aluminum wiring 9b can be used, and the wiring efficiency is improved.

〔Effect of the invention〕

As described above, according to the present invention, P channel MO5) transistor or N channel MO of CMOS gate array
S) Since the gate electrode of the transistor is used as a signal wiring, the FORBIDDEN area becomes smaller.
, which has the effect of improving wiring efficiency.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view when a second layer of aluminum wiring is formed in the device, and FIG. 3 is a plan view of a conventional semiconductor integrated circuit device. FIG. 4 is a plan view of the conventional circuit device in which a second layer of aluminum wiring is formed, and FIG. 5 is a cross-sectional view taken along the line V--V. 1...Polysilicon gate, 2...n-dissolution layer, 4
a to 4e... Second layer aluminum wiring, 5... Through hole, 7.8... Gate contact. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device having a gate array in which complementary MOS transistors are arranged in an array, signal line lead-out portions are provided at both ends of the transistor gate electrode of a P-channel MOS or an N-channel MOS, and a logic cell is configured. 1. A semiconductor integrated circuit device characterized in that a gate electrode of a MOS transistor that is not connected to a gate electrode is used as a signal wiring for connecting logic cells.