JPS61294954A - Offset 4-phase differential psk modulator-demodulator - Google Patents

Abstract

PURPOSE:To simplify a demodulation circuit by providing the 1st and 2nd differential coders converting the 1st and 2nd parallel data code into the code change to eliminate the need for the control of a phase difference of a recovered carrier always at 0 deg.. CONSTITUTION:A serial/parallel conversion circuit 2 converts inputted serial data A into 2 systems of parallel data B and C. Differential coders 3a, 3b convert the code of parallel data B, C into a code change. The differential coder 3a, 3b consist respectively of an EOR circuit 31a and a delay device 32a, and an EOR circuit 31b and a delay device 32b, and an orthogonal modulation circuit 4 consists of balanced modulators 41a, 41b, a carrier oscillator 42, a 90 deg. phase shifter 43 and an adder 44. A synchronous detection circuit 5 consists of phase detectors 51a, 51b, a carrier recovery circuit 52, a 90 deg. phase shifter 53 and low-pass filters 55a, 55b, and differential decoders 7a, 7b consist respectively of an EOR circuit 71a, a delay device 72a and an EOR circuit 71b and a delay device 72b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a four-phase differential PSK modulator and demodulator, and particularly to an offset four-phase differential PSK modulator and demodulator suitable for transmitting and receiving via a nonlinear transmission path.

[Background of the invention]

In the field of digital wireless communications, four-phase differential phase modulation (
QDPSK) is widely used. However, in this QDPSK system, when passing through a nonlinear transmission path, the band expands and the bit error rate characteristics also deteriorate. This is an important problem to be overcome in transmission systems 9, such as satellite communications and mobile communications, where the bandwidth is limited and the carrier power-to-noise power ratio (C) cannot be very large.

From this point of view, the offset QPSK method has been attracting attention in recent years. This is an IEICE technical report.

C8-81-52, 1981 by Suzumoto et al. [Fundamental Properties of Narrowband Digital Angle Modulated Waves] change points to 1/1/1 of each other
This is a method of modulating by shifting two data cycles. This has the advantage that the envelope of the modulated wave does not cross zero, and the band does not expand much even through a nonlinear transmission path.

However, in this offset QPSK method, the conventional QPSK
The differential code and decoding method used in the SK method could not be used, and it was necessary to detect the absolute phase on the demodulator side.

[Purpose of the invention]

An object of the present invention is to provide an offset four-phase differential PSK modulation/demodulation device 1 that is compatible with this offset QPSK method.

[Summary of the invention]

The present invention independently converts the sign of input data into a sign change (for example, if it is 0, the previous sign is continued, and if it is 1, the previous sign is inverted). A dynamic encoder is provided on the modulator side, and on the demodulator side, differential decoders are provided independently for each of the P and Q channels to capture a change in the code of detected data and convert it to its original code.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In the same figure, 1 is the digital data (A) to be transmitted.
input terminal, 2 input serial data (A)
Serial-to-parallel converter circuit that converts the parallel data (B) and (C) of the system, 3a and μ are differential encoders that convert the signs of the parallel data (B) and (C) into sign changes, and 4 are each independent Parallel data differentially encoded (D)
and Cg) with two carrier waves having a phase difference of 90 degrees from each other, 40 is an output terminal of the modulated signal, and differential encoders 3a and 3b are each EO
The quadrature modulation circuit 4 includes the R circuit 31eL, the delay device 324, the gOR circuit 316, and the delay device 324, and the orthogonal modulation circuit 4 includes a balanced modulator 41α,
41b, a carrier wave oscillator 42, a 90-degree phase shifter 43, and an adder 44. The above is offset 4-phase differential PSK
(0-QDPSK) modulation circuit.

Further, in FIG. 1, 50 is an input terminal for an o-QDPSK modulation signal, 5 is a synchronous detection circuit that detects the phase of an input modulation signal using two orthogonal carrier waves that are phase-synchronized with the modulation signal, and 6a and 6b are synchronous detection circuits. 7α and 7b are code identification circuits that distinguish the positive and negative of the two systems of signals at timings synchronized with the speed of the transmitted parallel data, and convert them into digital signals. F) and (G) A differential decoder that converts each sign change back to the original code, and 8 converts the decoded parallel data (H) and (I) into serial data (
9 is the output terminal of the finally demodulated digital data (J), and the synchronous detection circuit 5 is connected to the phase detectors 51a, 514 and the carrier regeneration circuit 52 by 90 degrees. Phaser 53 and low frequency fill 55-55
In this case, the differential decoders 7 and 7 each include an EOR circuit 71, a delay device 722, and an EOR circuit 71 and a delay device 72A. The above is the o-QDPSK demodulation circuit. FIG. 2 is a waveform diagram showing the operation of each part of the circuit shown in FIG. 1. The operation of this embodiment will be explained below with reference to the same figure.

In FIG. 2, <1> indicates an operating waveform on the modulation circuit side, and <it> and <iii> indicate operating waveforms on the demodulation circuit side. Further, <11> indicates the case where the phase difference φ of the carrier reproduced by the demodulation circuit with respect to the carrier phase in the modulation circuit is 0 degrees and 180 degrees, and <+ii> indicates the case where the same is ±90 degrees. First, on the modulation circuit side of the comb, divide the input digital data (A) into every 2 bits, set the leading bit as XR, and set the temporary bit as YR (γ coefficient R is an integer). Then, serial-parallel conversion is performed. The parallel data (B) and (C) converted by the converter 2 are output alternately in a form shifted by 1/2 data cycle (T/2) as shown in the figure.

Next, this parallel data XR and YR is sent to the differential encoder 3a.
and 3b are converted into data PR and saw. This can be expressed as a logical formula as follows.

PK=XR■Px-+・・・Song・ (1)QK=YK
■QK-1 (2) However, ■ indicates exclusive OR.

The data PK and QK are then modulated by a quadrature modulator 4. This modulation signal converts the in-phase carrier cp to ccs w
ct and the orthogonal carrier cQ as sin wct (WC is the carrier angular frequency), it is expressed by the following equation.

PK -cnswct+QK -sin wct-.(3) Order K On the demodulation circuit side, the modulated signal expressed by equation (3) is detected by the synchronous detection circuit 5. At this time, the in-phase carrier cP' regenerated by the carrier regeneration circuit 52 is converted into ccs(
wct+φ), and the orthogonal carrier cQ′ is sin(wct+
φ), the detected output signal is expressed by the following equation.

PK-tanφ-QK-tsuφ ・Song... (4) PK-
sinφ+QK−Q)Sφ Curved surface (5) When the carrier regeneration circuit 52 is operating normally, the phase difference φ with the modulation circuit side takes values such as 0 degrees, ±90 degrees, and ±180 degrees.

FIG. 2 (11) shows operating waveforms when this phase difference φ is 0 degrees and 180 degrees. For example, when φ is 0 degrees, data PK and QK appear in the output signals (F) and (G) of the code identification circuits 6α and 6o, respectively. When this is passed through differential decoders 7cL and 7b, the original parallel data XK and YK appear as output signals (H) and (I), respectively. This process can be expressed as a logical formula as follows.

PR■Pa-+=(XR■P-1)■PK-13X・
... (6) QK■QK-1=(YR■QK-1
) ■QK-IEYK・・・・・・ (7) Also, φ is 1
In the case of 80 degrees, PR and QK appear in (F) and (G) as seen from equations (4) and (5), but due to the action of differential decoders 7a and 76, (H) and In (I), the original XK and YR are decoded. In other words, in the logical formula, MiXK ・・・・・・・・・ (8)Qx■QK−+
=(Yx■QK-1)■PK-+=Y■QR-1■QK
-'Mi YK ...... (9) is indicated.

In this way, when the original parallel data n and YK data lp are obtained, they are converted into serial data by the parallel-to-serial conversion circuit 8, and the final demodulated data (J) is obtained.

Similarly, even when φ is ±913 degrees, the channels in which XR and YK appear are simply reversed, as shown in Figure 2 <1ii>, and the front-to-back relationship between XR and Yx is maintained. There is no problem if you perform parallel-to-serial conversion in that order. This method will be detailed later.

FIG. 6 is a diagram showing a specific example of a modulation circuit according to the present invention. In the same figure, 21.22a, 224 and 5ScL
, 5511 is a D type 7 lip frog (D-FF)
, 1o is an input terminal for the clock signal CK1 of input data (A). FIG. 4 is a waveform diagram showing the operation of each part of the circuit shown in FIG. 3. The operation will be explained below using FIG. 4. The input clock CK1 is frequency-divided by 1/2 by 1)-FF21. 1. Ayri CN3 and West 5 will be created. Then, by latching the serial data (A) inputted at the timing of 0 and CN3 using the D-FFs 22cL and 224, parallel data X1 and YL are obtained. In the differential encoders 3α and 64, the delay units 324 and 524 shown in the embodiment of FIG.
-It is only composed of FF35a and 33/4,
Its operation is exactly the same. However, in the configuration shown in Figure 3, PR and QR are XR and YR as shown in Figure 4.
Although the output is delayed by one cycle, there is no problem with this. Then, the differentially encoded parallel data PR and QR are modulated by the orthogonal modulation circuit 4. In this way, according to this specific example, 0-QDPSK can be achieved with a simple configuration.
A modulation circuit can be realized.

FIG. 5 is a diagram showing a specific example of a demodulation circuit according to the present invention. In the same figure, 614.61J! r is a comparator, 6
2cL+62', 64.73a, 73', 83 are D-F
F', 65 is a clock regeneration circuit, 65.66 is an inverter circuit, 81cL.

81 is a logical product (AND) circuit, 82 is a logical sum (OR)
The circuit 90 is an output terminal of a clock CK1' which is bit synchronized with the demodulated data (J). The two systems of signals detected by the synchronous detection circuit 5 are sent to comparators 616 and 61b and D, respectively.
- Code identification circuit 6α composed of FF62α and FF62
and 6h, it is converted into digital y signals CF') and (G). This timing is controlled by the rising edges of clocks CK2' and CK2', which are obtained by dividing the clock CK1' reproduced by the clock reproducing circuit 63 by 1/1 by the D-F'F64. The differential decoding circuit 7eL, 74 replaces the delay device 72cL, 724 in the embodiment of FIG.
6k, and the operation is exactly the same. Next, the operationally decoded parallel data (H) and (I
) are the reproduced clocks CK2' and CK2' and AN
The D circuits e1a and 81 are ANDed. These two signals (L) and (M) are further logically summed by an OR circuit 82,
When latched by the D-F'F85 at the rising timing of the recovered clock CK1', the final demodulated data converted into serial data is obtained.

FIG. 6 is an operation waveform diagram showing this situation, and <1> means that when the phase difference φ of the reproduced carrier is 0 degrees and 180 degrees, <
11> shows the case where φ is ±90 degrees. In this way, transmission data can be demodulated without error no matter what value φ is.

〔Effect of the invention〕

According to the present invention, the offset 4-phase P
Since a differential method can also be applied to the SK method, there is no need to detect the phase of the feeder, in other words, it is not necessary to always control the phase difference φ of the reproduced carrier to 0 degrees, which has a great effect on simplifying the demodulation circuit.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are configuration diagrams showing one embodiment of the present invention, and Figure 2 <i>, <ii>, and <iii> show the first embodiment.
Figure (a). FIG. 3 is a circuit diagram showing a specific example of the modulation circuit according to the present invention, FIG. 4 is an operating waveform diagram of the circuit shown in FIG. 3, and FIG. A circuit diagram showing a specific example of the demodulation circuit according to the invention, FIG. 6 <i>, <ii>
5 is an operating waveform diagram of the circuit shown in FIG. 5. FIG. 2...Series-parallel conversion circuit, 36.3k...Differential encoder, 7a, 74...Differential decoder, 8...Parallel- Series conversion circuit.

Claims (1)

[Claims] 1. Input serial digital data to the first and second
a serial-to-parallel converter that converts the first and second parallel data into parallel data and outputs them with the sign change points of the first and second parallel data shifted from each other by 1/2 parallel data period; A quadrature modulator that balance-modulates a carrier wave using the first and second parallel data; and a quadrature modulator that receives the signal sent from the quadrature modulator via a transmission path, and transmits the received signal to two modulators that have a phase difference of 90 degrees from each other. It includes a synchronous detector that performs phase detection using two orthogonal carrier waves, and first and second code discriminators that determine whether the first and second signals detected by the synchronous detector are positive or negative and convert them into digital signals, respectively. An offset four-phase differential modulation and demodulation device characterized in that the offset four-phase differential modulation and demodulation device is provided with first and second differential encoders that convert codes of the first and second parallel data into changes in code. 2. Input serial digital data to the first and second
a serial-to-parallel converter that converts the first and second parallel data into parallel data and outputs them with the sign change points of the first and second parallel data shifted from each other by 1/2 parallel data period; A quadrature modulator that balance-modulates a carrier wave using the first and second parallel data; and a quadrature modulator that receives the signal sent from the quadrature modulator via a transmission path, and transmits the received signal to two modulators that have a phase difference of 90 degrees from each other. It includes a synchronous detector that performs phase detection using two orthogonal carrier waves, and first and second code discriminators that determine whether the first and second signals detected by the synchronous detector are positive or negative and convert them into digital signals, respectively. In the modulation/demodulation device, the first and second differential decoders each decode the original code from the code change of the first and second digital signals output from the first and second code discriminators. An offset four-phase differential PSK modulator and demodulator, characterized in that: 3. In claim 2, the first and second parallel signals output from the first and second differential encoders are alternately output at a data rate twice as high as the data rate of the parallel signals. An offset four-phase differential PSK modulation/demodulation device comprising a parallel-to-serial converter for taking out and converting into a serial signal. 4. In claim 1, the first and second code discriminators decode the original codes from the encoding of the first and second digital signals output from the first and second code discriminators, respectively. 1. An offset four-phase differential PSK modulation and demodulation device, characterized in that it is provided with a differential decoder. 5. In claim 4, the first and second parallel signals output from the first and second differential decoders are alternately output at a rate twice the data rate of the parallel signals. An offset four-phase differential PSK modulation/demodulation device comprising a parallel-to-serial converter for taking out and converting into a serial signal.