JPH0763163B2 - Digital transmission system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital transmission system, and in particular, a series of binary serial digital signals is column-converted into a plurality of parallel digital signal trains, and then speed conversion is performed. The present invention relates to a slave synchronization type digital transmission system for transmitting a multilevel signal (multilevel baseband signal or multilevel modulated signal).

[Prior art]

With the development of digital communication, high-efficiency multilevel modulation schemes such as 16-ary quadrature amplitude modulation (16QAM) have been widely used to improve the frequency utilization efficiency of transmission lines. In such a high-efficiency digital transmission system, when the input is a series of serial digital signals, this is column-converted into four parallel digital signal sequences, and speed conversion is performed to monitor the transmission section. After adding additional pulses (frame synchronization pulse, parity check pulse, meeting line pulse, etc.), one carrier wave is quadrature-amplitude modulated and transmitted by these four digital signal sequences whose speeds have been converted. In order to perform this sequence conversion and modulation processing, first, extracts the clock signal f _c from the serial digital signal, the reference clock signal f _s of the clock signal f _c by 1/4 frequency columns converted digital signal sequence And a phase locked loop circuit (PLL circuit) equipped with a voltage controlled oscillator (VCO) is controlled by using this reference clock signal f _s to generate a clock signal f _r in the speed-converted transmission section. It is configured. As a timing extracting means for generating a clock signal f _c from an input serial digital signal, a method of extracting a clock signal frequency component contained in the serial digital signal using a tuning circuit has been conventionally used.

[Problems to be solved by the invention]

However, in the conventional timing extraction means using the tuning circuit described above, the clock signal f _c cannot be extracted when a momentary interruption occurs in the input serial digital signal. Therefore, the input of the frequency divider circuit for generating the reference clock signal f _s. Is interrupted. A counter type circuit is usually used for the frequency dividing circuit,
The output phase when the input is interrupted and then added again has uncertainty due to the initial conditions, and when the instantaneous interruption is recovered, the output phase changes suddenly (a multiple of 90 degrees in the case of dividing by 4). I have something to do. The transient response time of the PLL circuit that generates the speed-converted clock signal f _r cannot be shortened too much because of the relationship with the response time of the clock recovery circuit on the reception demodulation side in the high-efficiency transmission section. I can't follow. Therefore, the phase relationship between the reference signal (f _s ) and the output (f _r ) of the PPL circuit changes with time until the transient response is completed. That is, the timing of sampling the column-converted digital signal with the clock signal f _r having a slightly higher frequency for speed conversion is not normal but fluctuates. For this reason, data bits may be missing due to insertion of additional bits, or the same data may be read continuously, resulting in erroneous reading of data. The transient response time of the above-mentioned PLL circuit on the transmission side is several msec to several tens msec at the maximum when the phase change is 180 degrees, and even if the instantaneous interruption time of the input serial digital signal is as short as several hundreds nsec, During this period, there are many bit errors and there is a drawback that the line is disturbed. An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a digital transmission system capable of limiting a line failure time due to a momentary interruption of an input signal to only a momentary interruption time of an input.

[Means for solving problems]

The digital transmission system of the present invention is a dependent-synchronization type digital transmission system in which a series of binary serial digital signals is column-converted into a plurality of parallel digital signal sequences, speed-converted, and then transmitted as a multilevel signal. The timing extracting means for reproducing the clock signal of the serial digital signal includes a PLL circuit having a VCO, and the output of the timing extracting means is continuously transmitted even if the serial digital signal is interrupted. Has been done.

〔Example〕

The present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which a bipolar code (AM
16Q for a series of serial digital signals transmitted by I code)
The figure shows the case of connecting to the AM digital radio transmission system. In FIG. 1, an input signal 100 is converted into a unipolar code by a code conversion unit 1 and column-converted into a parallel digital signal 101 of four columns by a column conversion unit 2 and then a speed conversion and scramble processing is performed by a signal processing unit 3. The quadrature modulator 4 performs 16QAM modulation on the carrier wave, and the modulated carrier wave is converted into a radio frequency and transmitted from the transmitter 5. On the other hand, the input signal 100 is branched and added to a clock extraction circuit (consisting of a tuning circuit) 6, and the VCO of the PLL circuit 7 is phase-controlled by the clock signal 102 (f _c ) extracted here, and the PLL circuit 7 is output 103 (f _c ) to the column conversion unit 2. The column conversion unit 2 includes a frequency dividing circuit, divides the clock signal input 103 by 4 to generate the reference clock signal f _s ,
Using this, a serial signal is sampled and converted into a parallel digital signal sequence 101. The reference clock signal 104 (f _s ) divided by 4 is a column-converted parallel digital signal sequence 1
A PLL for sending the clock signal 105 ( _fr ) for the wireless section after speed conversion to the signal processing unit 3 together with 01.
It becomes the reference input signal of the circuit.

FIG. 4 is a block diagram showing a configuration example of the signal processing unit 3,
Speed conversion / additional pulse addition circuit 13, scramble circuit 1
4 and PLL circuit 15.

The PLL circuit 15 is a circuit for obtaining a clock signal f _r for a wireless section, and in the m−1 / m circuit 16, one bit out of m bits of the clock signal f _r is extracted to have the same frequency component as the reference clock signal f _s. M-1 bit signal is generated, this signal and the reference clock signal f _s are phase-compared by the phase comparator (PHCOMP) 19, and the output is added to the VCO 17 as control information via the LPF 18, and the reference clock signal f s is added. phase-locked to _s and m / m-1
Only the speed-converted clock signal f _r can be obtained at the output of the VCO 17.

The speed conversion / additional pulse adding circuit 13 receives the reference clock signal f _s , the clock signal f _r, and the additional pulse for monitoring the transmission section described above, and receives the clock frequency of the digital signal sequence 101 from the sequence conversion unit 2. And convert f _s to f _r ,
The above-mentioned additional pulse is inserted into the time slot which has become free by this conversion. The scramble circuit 14 scrambles the output of the speed conversion / additional pulse adding circuit 13.

In the configuration of FIG. 1, the clock extraction circuit 6 is a conventional circuit for extracting the clock signal frequency component contained in the input signal by a tuning circuit or the like, and the output is cut off when the input signal disappears. The PLL circuit 7 is a normal PLL circuit including a VCO, a phase comparator and a loop filter.
The output 103 of the circuit 7 is controlled so as to have the same phase as the clock signal 102 extracted by the clock extraction circuit 6. According to this configuration, even if the input signal 100 is instantaneously interrupted and the output 102 of the clock extraction circuit 6 is instantaneously interrupted, the clock signal input 103 of the column conversion unit 2 is not interrupted and is a continuous signal. Is supplied. Therefore, the reference clock signal 104, which is the output of the frequency dividing circuit of the column conversion unit 2, does not undergo a rapid phase change, and the signal processing unit 3 does not generate a code error.

On the other hand, the conventional system has the PLL circuit 7 from the configuration of FIG.
The output 102 of the clock extraction circuit 6 is directly input as the clock signal of the column conversion unit 2. Therefore, if there is a momentary interruption in the input signal 100, the clock signal input to the column conversion unit 2 is also disrupted, and when the momentary interruption is restored and the clock signal input is applied again as described above, it is divided depending on the condition of the momentary interruption. The output phase of the circuit becomes uncertain, and the reference clock signal 104 suddenly changes in phase by a multiple of 90 degrees. Therefore, the PLL circuit 15 provided in the signal processing unit 3 cannot follow this change, and the phase relationship between the reference clock signal f _s and the clock signal f _r input to the speed conversion / additional pulse addition circuit 13 is changed. There is a large deviation, and a code reading error occurs here, resulting in a code error until the transient response of the PLL circuit 15 ends.

FIG. 2 is a block diagram of another embodiment of the present invention, in which CMI (cod
ed Mark Inversion) shows the configuration of the timing extraction means in the case of connecting a series of encoded serial digital signals 106 to the 16QAM digital wireless transmission system. In FIG. 2, a code conversion unit 8 is a code conversion unit that converts an input CMI code into a unipolar code, and the unipolar code 107 converted here is sent to the column conversion unit 2 and four columns of parallel digital signals are transmitted. It is converted into a column 101, and thereafter, the same processing as in the case of FIG. 1 is performed. The timing extraction means for reproducing the clock signal input 108 (f _c ) input to the column conversion unit 2 is a flip-flop (FF) 9, a low-pass filter (LPF) 10, a VCO 11,
It is composed of a phase-locked loop circuit composed of a delay line (DL) 12, and is configured so that the clock signal input 108 of the column conversion unit 2 is continuously output even if the input signal 106 is interrupted. As in the embodiment of FIG. 1, the line fault can be limited to the same extent as the instantaneous interruption time of the input signal 106.

The operation of the timing extracting means shown in FIG. 2 will be described below with reference to the waveform diagram of the CMI code shown in FIG. CMI code is two codes "0,1" with double bit rate of "0" of information bit.
And a binary NRZ (Non-Return to Zero) code configured to alternately transmit the information bit "1" to either "1,1" or "0,0". is there. As shown in FIG. 3, in the CMI-coded signal, the change in the code at the midpoint t _c of the information bit time slot T is always the rising edge (0 → 1) and the falling edge (1 → 0). Does not occur. Therefore, as shown in FIG. 2, when the output of VCO11 is supplied to the timing terminal C of FF9 via DL12, the phase of the output of DL12 (the time when the output changes from negative to positive)
Is ahead of the midpoint t _c of the time slot T and the sampling time is t _{1 in} FIG. 3, the output of FF9 for “0” of the information bit is “1”, which is later than t _c. When the sampling time reaches t ₂ , the output of FF9 becomes “0”. Therefore, the Q output of FF9 is added to VCO11 via LPF10, and when the Q output of FF9 is "1" (when the output of LPF10 becomes large), the frequency of VCO11 is lowered (the phase is delayed). , When it is “0” (when the output of LPF10 becomes small), if the frequency of VCO11 is controlled to increase (advance the phase), the ratio of “1” and “0” of the Q output of FF9 will be The phase of the output of the VCO 11 is controlled so as to be the same, that is, the sampling time is t _c, and the clock signal is extracted. DL12 is used in the code conversion unit 8.
When decoding the CMI code, it is inserted so that a sampling signal having a phase that is T / 4 ahead of t _c and a phase that is delayed from t _c can be easily generated by the delay circuit, and is not necessarily required.

In the embodiment shown in FIG. 2 described above, the timing extraction means has an FF.
9 uses a circuit that directly compares the input signal 106 and the output of the VCO 11, but uses a normal clock extraction circuit that extracts the clock frequency component included in the CMI code with a tuning circuit, and uses the same PLL as in FIG. The same effect can be obtained by providing a circuit. Further, although the above-described embodiments show the case where the frequency is divided by 4 and connected to the 16QAM modulation system, when connecting to the quadrature amplitude modulation system other than 16QAM, for example, the frequency is divided by 6 to obtain 64QA.
The technical idea of the present invention can be applied to the case of M modulation or the case of performing 4-phase PSK modulation by dividing the frequency by 2 and the same effect can be obtained. In addition,
The 8-phase PSK modulation is also one of the quadrature amplitude modulations, and is a subject of the present invention when converting a series of serial digital signals into three parallel digital signal sequences for modulation. Furthermore, in each of the above-described embodiments, the digital radio transmission system using the quadrature amplitude modulation has been described, but the radio transmission system is not necessarily limited to the radio transmission system, and the quadrature amplitude modulation is not limited. That is, a series of binary serial digital signals (bipolar code is a binary RZ code) is converted into a parallel digital signal sequence, subjected to speed conversion, and then converted into a multilevel baseband signal. The technical idea of the present invention can be applied to an optical transmission system that modulates and transmits an optical signal with a band signal and a baseband multilevel transmission system that transmits a multilevel baseband signal as it is on a line.

〔The invention's effect〕

As described in detail above, according to the digital transmission method of the present invention, even if a momentary interruption occurs in the input serial digital signal, the clock signal input to the column converter is continuously supplied without interruption. Therefore, the shortcoming of the conventional method that the data is erroneously read during the speed conversion process due to the abrupt change of the output phase of the frequency divider when the interruption is recovered is eliminated, and the line failure time due to the interruption can be minimized. effective.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, FIG. 3 is a CMI waveform diagram for explaining the operation of FIG. 2, and FIG. FIG. 3 is a block diagram showing a configuration example of a signal processing unit in FIG. 1. 1,8 ... Code converter, 2 ... Column converter, 3 ... Signal processor, 4 ... Quadrature modulator, 5 ... Transmitter, 6 ... Clock extraction circuit, 7,15 ... PLL circuit , 9 ...... Flip-flop (FF), 10,18 ...... Low pass filter (LPF), 11,17 ......
Voltage controlled oscillator (VCO), 12 ... Delay line (DL), 13 ...
… Speed conversion and additional pulse addition circuit, 14 …… Scramble circuit, 16 …… m−1 / m circuit, 19 …… Phase comparator (PHCOM
P).

Claims (2)

[Claims] 1. A dependent-synchronization type digital transmission in which a series of binary serial digital signals is input, column conversion is performed by a column conversion unit into a plurality of parallel digital signal sequences, speed conversion is performed, and then the signals are transmitted as multilevel signals. In the method, a timing extraction unit for reproducing a clock signal of the serial digital signal includes a phase locked loop circuit including a voltage controlled oscillator that is phase locked to the clock signal in a stage before the column conversion unit,
A digital transmission system characterized in that the timing extraction means is continuously output even if the serial digital signal is interrupted. 2. A subordinate that receives a series of CMI-encoded binary serial digital signals, performs column conversion into a plurality of parallel digital signal sequences by a column conversion unit, performs speed conversion, and then transmits as a multilevel signal. In a synchronous digital transmission system, a flip-flop for inputting the serial digital signal in a stage before the column conversion unit, and a voltage control for controlling an oscillation frequency by inputting an output of the flip-flop through a low-pass filter A digital transmission system comprising an oscillator and a phase-locked loop circuit for phase-locking with the clock signal of the serial digital signal by inputting the output of the voltage-controlled oscillator to the timing terminal of the flip-flop. .