JPS61294935A - 半導体装置およびデ−タ伝送路 - Google Patents

半導体装置およびデ−タ伝送路

Info

Publication number
JPS61294935A
JPS61294935A JP13660785A JP13660785A JPS61294935A JP S61294935 A JPS61294935 A JP S61294935A JP 13660785 A JP13660785 A JP 13660785A JP 13660785 A JP13660785 A JP 13660785A JP S61294935 A JPS61294935 A JP S61294935A
Authority
JP
Japan
Prior art keywords
output
cmos inverter
conductivity type
stage
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13660785A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0521451B2 (enrdf_load_html_response
Inventor
Hironori Terada
浩詔 寺田
Katsuhiko Asada
勝彦 浅田
Hiroaki Nishikawa
博昭 西川
Nobufumi Komori
伸史 小守
Kenji Shima
憲司 嶋
Soichi Miyata
宗一 宮田
Satoshi Matsumoto
敏 松本
Hajime Asano
浅野　一
Masahisa Shimizu
清水　雅久
Hiroki Miura
三浦　宏喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Sharp Corp
Sanyo Electric Co Ltd
Panasonic Holdings Corp
Original Assignee
Mitsubishi Electric Corp
Sharp Corp
Sanyo Electric Co Ltd
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp, Sharp Corp, Sanyo Electric Co Ltd, Matsushita Electric Industrial Co Ltd filed Critical Mitsubishi Electric Corp
Priority to JP13660785A priority Critical patent/JPS61294935A/ja
Priority to US06/875,551 priority patent/US4785204A/en
Publication of JPS61294935A publication Critical patent/JPS61294935A/ja
Publication of JPH0521451B2 publication Critical patent/JPH0521451B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)
JP13660785A 1985-06-21 1985-06-21 半導体装置およびデ−タ伝送路 Granted JPS61294935A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13660785A JPS61294935A (ja) 1985-06-21 1985-06-21 半導体装置およびデ−タ伝送路
US06/875,551 US4785204A (en) 1985-06-21 1986-06-18 Coincidence element and a data transmission path

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13660785A JPS61294935A (ja) 1985-06-21 1985-06-21 半導体装置およびデ−タ伝送路

Publications (2)

Publication Number Publication Date
JPS61294935A true JPS61294935A (ja) 1986-12-25
JPH0521451B2 JPH0521451B2 (enrdf_load_html_response) 1993-03-24

Family

ID=15179249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13660785A Granted JPS61294935A (ja) 1985-06-21 1985-06-21 半導体装置およびデ−タ伝送路

Country Status (1)

Country Link
JP (1) JPS61294935A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPH0521451B2 (enrdf_load_html_response) 1993-03-24

Similar Documents

Publication Publication Date Title
US6417711B2 (en) High speed latch and flip-flop
US6686787B2 (en) High-speed fully balanced differential flip-flop with reset
US6211704B1 (en) Asynchronous sensing differential logic (ASDL) circuit
WO2001009900A2 (en) High speed latch and flip-flop
US20150303901A1 (en) Flip-flop circuit
US6696874B2 (en) Single-event upset immune flip-flop circuit
US3971960A (en) Flip-flop false output rejection circuit
US4785204A (en) Coincidence element and a data transmission path
US6191618B1 (en) Contention-free, low clock load domino circuit topology
US11799456B2 (en) Clock generation circuit and latch using same, and computing device
US6075748A (en) Address counter cell
JP4575300B2 (ja) ダイナミック・フリップ・フロップの信号レベル置換を備えたマスタ・ラッチ回路
US6661274B1 (en) Level converter circuit
US20070080714A1 (en) Flip-flop circuit
US5546035A (en) Latch circuit having a logical operation function
US6208188B1 (en) Synchronizing circuit for receiving an asynchronous input signal
US6078196A (en) Data enabled logic circuits
US6373310B1 (en) Scalable set/reset circuit with improved rise/fall mismatch
US20050083093A1 (en) Flip-flop
US6509772B1 (en) Flip-flop circuit with transmission-gate sampling
US7242235B1 (en) Dual data rate flip-flop
US5994936A (en) RS flip-flop with enable inputs
JPS61294935A (ja) 半導体装置およびデ−タ伝送路
JPS61294932A (ja) 半導体装置およびデ−タ伝送路
US6404253B1 (en) High speed, low setup time voltage sensing flip-flop

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term