JPS61294877A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61294877A
JPS61294877A JP60137329A JP13732985A JPS61294877A JP S61294877 A JPS61294877 A JP S61294877A JP 60137329 A JP60137329 A JP 60137329A JP 13732985 A JP13732985 A JP 13732985A JP S61294877 A JPS61294877 A JP S61294877A
Authority
JP
Japan
Prior art keywords
semiconductor
crystal
buffer layer
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60137329A
Other languages
Japanese (ja)
Inventor
Yukio Fukuda
幸夫 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60137329A priority Critical patent/JPS61294877A/en
Publication of JPS61294877A publication Critical patent/JPS61294877A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1852Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound

Abstract

PURPOSE:To grow and form a high quality semiconductor crystal, by forming a semiconductor layer, which constitutes a second semiconductor that is contacted with a third semiconductor, with a semiconductor material, whose lattice constant is smaller than the lattice constant of the third semiconductor. CONSTITUTION:A semiconductor device is formed by sequentially laminating a buffer layer 12 and a gallium arsenide crystal 13 on a silicon substrate 11 having a surface orientation of [100]. The buffer layer 13 comprises 10 SiGe mixed crystal layers, with their composition ratios being increased stepwise by every 0.1. In this semiconductor device, it is necessary that the thickness of each SiGe layer constituting the buffer layer 12 is set at a value larger than the critical thickness, which can be alleviated in dislocation newly caused by the lattice misalignment between the layers. In this case, the thickness is all set at about 0.2mum. Thus problems such as cracking and peeling can be avoided, and the device having excellent crystalline property is obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は緩衝層を介して異種基板上に形成される半導体
結晶を用いた半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using a semiconductor crystal formed on a different substrate with a buffer layer interposed therebetween.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

以下、シリコン基板上にゲルマニウム緩衝層を介して形
成されたガリウムひ素形太陽電池を例にして説明する。
Hereinafter, a gallium arsenide solar cell formed on a silicon substrate with a germanium buffer layer interposed therebetween will be described as an example.

第3図は、例えば「デブロプメント・オブ・ライト−ウ
ェイト・スインGaAsソーラ・セル・オン・Slサブ
ストレイトス:テクニカル・ダイジェスト・オブ・ザ・
インターナショナルpvSEC−1、神戸2日本、PP
837−840.19841(”Developame
nt of Light−Weight Th1n G
aAs5olar Ce1ls on St 5ubs
trates:TechniealDigest  o
f  the  International  PV
SEC−1,kobe。
FIG.
International pvSEC-1, Kobe 2 Japan, PP
837-840.19841(”Developame
nt of Light-Weight Th1n G
aAs5olar Ce1ls on St 5ubs
trates:Technical Digest o
f the International PV
SEC-1, kobe.

Japan、pp837−840.1984”)に示さ
れた、シリコン基板上にゲルマニウム緩衝層を介して形
成されたガリウムひ素形太陽電池の主要構成要素を示す
断面図であり、図中、1はシリコン基板、2はシリコン
基板上に形成されたゲルマニウム緩衝層、3はダルマニ
ウム緩衝層上に形成されたガリウムひ素結晶層である。
Japan, pp 837-840.1984") is a cross-sectional view showing the main components of a gallium arsenide solar cell formed on a silicon substrate with a germanium buffer layer interposed therebetween, and in the figure, 1 is a silicon substrate. , 2 is a germanium buffer layer formed on a silicon substrate, and 3 is a gallium arsenide crystal layer formed on the dalmanium buffer layer.

室温におけるシリコン、ゲルマニウム、ガリウムひ素各
結晶の格子定数は各々5.431X。
The lattice constants of silicon, germanium, and gallium arsenide crystals at room temperature are each 5.431X.

5.658X 、5.654Xであり、シリコン結晶と
ガリウムひ未結晶との格子不整合は約4%と大きく、他
方ゲルマニウム結晶とガリウムひ未結晶との格子不整合
は0.04%以下と小さい。このため、シリコン基板上
にガリウムひ未結晶を直接成長させた場合、大きな格子
不整合のために成長されたガリウムひ素結晶内には転位
に代表される電気的、光学的に活性な多数の結晶欠陥が
導入されてしまい、このような低品位のガリウムひ未結
晶を用いて形成されたデバイスは性能的に実用に耐えが
たいものである。他方、シリコン結晶とガリウムひ未結
晶との間に、ガリウムひ未結晶との格子不整合が小さい
ダルマニウム結晶を緩衝層として挿入すれば、シリコン
結晶との格子不整合により発生する大部分の結晶欠陥を
ダルマニウム緩衝層内に吸収させることができるため、
この上に高品位のガリウムひ未結晶が成長可能となる。
5.658X, 5.654X, and the lattice mismatch between the silicon crystal and the gallium blank crystal is as large as about 4%, while the lattice mismatch between the germanium crystal and the gallium blank crystal is as small as 0.04% or less. . For this reason, when a gallium arsenide crystal is grown directly on a silicon substrate, there are many electrically and optically active crystals represented by dislocations within the grown gallium arsenide crystal due to the large lattice mismatch. Defects are introduced, and devices formed using such low-grade gallium amorphous crystals are unsuitable for practical use in terms of performance. On the other hand, if a dalmanium crystal, which has a small lattice mismatch with the gallium non-crystal, is inserted as a buffer layer between the silicon crystal and the gallium non-crystal, most of the crystals caused by the lattice mismatch with the silicon crystal can be removed. Defects can be absorbed into the dalmanium buffer layer, so
On top of this, high-grade gallium green crystals can be grown.

しかしながら、ガリウムひ未結晶の格子定数は僅かなが
らではあるがダルマニウム結晶の値よりも小さいこと、
さらには、シリコン結晶の線膨張係数(約2.3 X 
10−’℃−1)がガリウムひ未結晶の値(約5.8 
X 10−’で1)及びゲルマニウム結晶の値(約5.
7 X 10”−6℃−1)の半分以下であるために、
結晶成長温度から室温に戻された状態では、ガリウムひ
未結晶に大きな引っ張り応力が加わることになる。この
ため、得られたガリウムひ未結晶の格子定数は正規の値
よυも大きな値を示し、エネルギーバンドギャグに代表
される物性定数が本来の値とは異なってしまう。また、
ガリウムひ未結晶の膜厚を太陽電池等のデバイス形成に
必要な3μm程度以上にすると降伏現象が起こり、ガリ
ウムひ未結晶が割れたり、ゲルマニウム緩衝層から剥が
れたりする等の問題が発生する。
However, the lattice constant of gallium uncrystallized is slightly smaller than that of dalmanium crystal;
Furthermore, the coefficient of linear expansion of silicon crystal (approximately 2.3
10-'℃-1) is the value of gallium uncrystallized (approximately 5.8
1) at x 10-' and the value of germanium crystals (approximately 5.
7 x 10"-6℃-1),
When the crystal growth temperature is returned to room temperature, a large tensile stress is applied to the gallium uncrystallized material. For this reason, the lattice constant of the obtained gallium uncrystallized material shows a value υ larger than the normal value, and the physical property constants represented by the energy band gag differ from the original values. Also,
When the thickness of the gallium uncrystallized film is increased to more than about 3 μm, which is necessary for forming devices such as solar cells, a breakdown phenomenon occurs, and problems such as the gallium uncrystallized cracking or peeling from the germanium buffer layer occur.

〔発明の目的〕[Purpose of the invention]

本発明は上述した問題点を解決するためになされたもの
であり、その目的は異種半導体基板上に高品位の半導体
結晶を成長形成せしめることにより、これを用いた高性
能の半導体装置を提供することにある。
The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a high-performance semiconductor device using the same by growing high-quality semiconductor crystals on a different type of semiconductor substrate. There is a particular thing.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために本発明者等は種々実験をなし
た結果、異種半導体基板上に緩衝層を介して半導体結晶
を成長形成する場合において、緩衝層をこの表面上に形
成する半導体の格子定数よりも小さい値を有する半導体
材料で形成すれば、緩衝層の上に形成される半導体には
常に圧縮応力が働き、割れや剥がれ等の問題が発生しな
いばかりでなく、緩衝層とこの上に形成される半導体と
の格子整合を正しくとることにより半導体の物性定数を
それに固有の値に近ずけられ得ることが分かった。
In order to achieve the above object, the present inventors conducted various experiments and found that when a semiconductor crystal is grown and formed on a different type of semiconductor substrate with a buffer layer interposed therebetween, the buffer layer is formed on the surface of a semiconductor lattice. If the semiconductor material is formed with a semiconductor material having a value smaller than the constant, compressive stress will always act on the semiconductor formed on the buffer layer, and problems such as cracking and peeling will not occur, and the buffer layer and the It has been found that by properly achieving lattice matching with the semiconductor to be formed, the physical constants of the semiconductor can be brought closer to the values inherent to the semiconductor.

これにもとすき、基板となる第1の半導体の表面上に、
少なくとも、緩衝層となる1層または複数層の半導体層
で構成された第2の半導体と、前記第1の半導体とは異
種の第3の半導体とが順次積層された構造の半導体装置
において、前記第3の半導体の緩衝層となる前記第2の
半導体を構成する半導体各層のうち、少なくとも前記第
3の半導体と接する前記第2の半導体を構成する半導体
層を、その格子定数が前記第3の半導体の格子定数より
も小なる値を有する半導体材料で形成することを特徴と
する半導体装置、さらに、前記第1の半導体をシリコン
結晶とし、前記第2の半導体をシリコンケ゛ルマニウム
混晶層かあるいはシリコンダルマニウム混晶層とゲルマ
ニウム結晶層とで構成し、前記第3の半導体をガリウム
ひ素とするときに、前記第3の半導体であるガリウムひ
素と接する前記第2の半導体を構成するシリコンゲルマ
ニウム混晶の組成をSt、 xGeXで表わしたときに
Xの値を0.98以下に定めたことを特徴とする半導体
装置を提案するに至った。
To this end, on the surface of the first semiconductor serving as the substrate,
In a semiconductor device having a structure in which at least a second semiconductor composed of one or more semiconductor layers serving as a buffer layer and a third semiconductor of a different type from the first semiconductor are sequentially stacked, Among the semiconductor layers constituting the second semiconductor, which serves as a buffer layer of the third semiconductor, at least the semiconductor layer constituting the second semiconductor in contact with the third semiconductor has a lattice constant equal to that of the third semiconductor. A semiconductor device characterized in that it is formed of a semiconductor material having a lattice constant smaller than the lattice constant of a semiconductor, further comprising a silicon crystal as the first semiconductor and a silicon-kemanium mixed crystal layer or silicon as the second semiconductor. A silicon-germanium mixed crystal that constitutes the second semiconductor that is composed of a darmanium mixed crystal layer and a germanium crystal layer and that is in contact with gallium arsenide that is the third semiconductor when the third semiconductor is gallium arsenide. We have proposed a semiconductor device characterized in that the value of X is set to 0.98 or less when the composition is expressed as St and xGeX.

〔発明の実施例〕[Embodiments of the invention]

以下に、基板をシリコン結晶とし、緩衝層をシリコンゲ
ルマニウム混晶かあるいはシリコンゲルマニウム混晶と
ゲルマニウム結晶とで形成し、その表面上にガリウムひ
未結晶を形成した半導体装置を例に、本発明の実施例に
ついて説明する。なお、以下、シリコンゲルマニウム混
晶の組成はSl、−xG@工で表わすことにする。また
、結晶成長は分子線エピタキシャル装置を用いて行なっ
た。
In the following, a semiconductor device in which the substrate is a silicon crystal, the buffer layer is formed of a silicon germanium mixed crystal or a silicon germanium mixed crystal and a germanium crystal, and a gallium non-crystal is formed on the surface thereof will be described as an example. An example will be explained. Note that hereinafter, the composition of the silicon germanium mixed crystal will be expressed as Sl, -xG@technique. Further, crystal growth was performed using a molecular beam epitaxial apparatus.

本発明の第1の実施例は、面方位〔100〕のシリコン
基板上に、厚さ約1μmで組成比X、が0.95のSi
1□GeX混晶とした緩衝層、ガリウムひ未結晶とを順
次積層して形成した半導体装置である。
In the first embodiment of the present invention, Si with a thickness of about 1 μm and a composition ratio X of 0.95 is formed on a silicon substrate with a plane orientation of [100].
This is a semiconductor device formed by sequentially stacking a buffer layer made of 1□GeX mixed crystal and gallium amorphous crystal.

本実施例による半導体装置は第3図に示した半導体装置
と同様の断面を有するので、ここでは記載を省略する。
Since the semiconductor device according to this embodiment has a cross section similar to that of the semiconductor device shown in FIG. 3, a description thereof will be omitted here.

本実施例において、Sl、−XGeX混晶層の厚さはシ
リコン基板との格子不整合が新たに発生する転位によっ
て緩和され得る臨界的膜厚以上に設定する必要があり、
ここでは約1μmとした。なお、この厚さを前記臨界的
厚さ以下にすると格子不整合が十分に緩和されない。
In this example, the thickness of the Sl, -XGeX mixed crystal layer must be set to a value greater than or equal to the critical thickness at which the lattice mismatch with the silicon substrate can be alleviated by newly generated dislocations.
Here, it was set to about 1 μm. Note that if this thickness is less than the critical thickness, the lattice mismatch will not be sufficiently alleviated.

また、ガリウムひ未結晶と接する81.−エGe X混
晶層は、ガリウムひ未結晶に常に圧縮応力が加わるよう
に、その格子定数がガリウムひ未結晶の値よりも小さく
なるように設定する必要があり、以下に示す511−x
G@工混晶の格子定数を表わす第(1)式にもとすいて
、Xの値は0.98以下としなければならない。本実施
例ではXが0.95の511−xGex混晶とした。
In addition, 81. -Ge
Based on the equation (1) expressing the lattice constant of the G@technical mixed crystal, the value of X must be 0.98 or less. In this example, a 511-xGex mixed crystal with X of 0.95 was used.

d(x)=5.431+0.227X(i)  、−(
1)ここで、d(x)は511−エGCx混晶の格子定
数を表わす。
d(x)=5.431+0.227X(i), -(
1) Here, d(x) represents the lattice constant of the 511-EGCx mixed crystal.

以上に述べた条件下で形成した緩衝層の表面上に、1μ
mから10μmの範囲の厚さのガリウムひ未結晶を成長
させてみたが、割れや剥がれ等の問題は生じなかった。
On the surface of the buffer layer formed under the conditions described above, 1μ
We tried growing gallium amorphous crystals with a thickness in the range from m to 10 μm, but no problems such as cracking or peeling occurred.

また、X線回折により測定した格子定数は前述したガリ
ウムひ素の固有値に極めて近い値を示した。
Further, the lattice constant measured by X-ray diffraction showed a value extremely close to the above-mentioned characteristic value of gallium arsenide.

次に、第1図は本発明の第2の実施例であり、面方位(
100)のシリコン基板11上に、組成比Xを0.05
から0.95まで0.1ずつステップ状に増加させなが
ら形成した10層のSl、−XGeX混晶層からなる緩
衝層12、ガリウムひ未結晶13を順次積層して形成し
た半導体装置である。
Next, FIG. 1 shows a second embodiment of the present invention, and the surface orientation (
100) on a silicon substrate 11 with a composition ratio X of 0.05.
This semiconductor device is formed by sequentially stacking a buffer layer 12 made of 10 layers of Sl and -XGeX mixed crystal layers and a gallium uncrystal 13, which are formed in steps of 0.1 from 0.95 to 0.95.

本実施例においても、緩衝層12を構成する各511−
XGex層は、各層間の格子不整合が新たに発生する転
位によって緩和され得る臨界的厚さ以上に設定する必要
があり、ここではその厚さを全て約0.2μmとした。
Also in this embodiment, each of the 511-
It is necessary to set the XGex layer to a thickness greater than a critical thickness at which the lattice mismatch between each layer can be alleviated by newly generated dislocations, and here the thicknesses were all set to about 0.2 μm.

なお、この厚さを前記臨界的厚さ以下にすると格子不整
合の緩和が十分に達成されない。本実施例においても、
緩衝層120表面上に1μmから10μmの範囲の厚さ
のガリウムひ未結晶13を成長させてみたが、前述した
第1の実施例と同様に、割れや剥がれ等の問題は生じな
かった。
Note that if this thickness is less than the critical thickness, the lattice mismatch will not be sufficiently alleviated. Also in this example,
Gallium amorphous crystals 13 having a thickness in the range of 1 μm to 10 μm were grown on the surface of the buffer layer 120, but similar to the first example described above, no problems such as cracking or peeling occurred.

次に、第2図は緩衝層22をダルマニウム結晶とS i
 1 + 、c1! X混晶とで形成した本発明の第3
の実施例であり、面方位(1003のシリコン基板11
上に、厚さ約1μmのrルマニウム結晶層と組成比Xが
0.95で厚さが約0,2μmのS i 1 + XG
 a X混晶層からなる緩衝層22、ガリウムひ未結晶
13を順次積層して形成した半導体装置である。
Next, in FIG. 2, the buffer layer 22 is made of dalmanium crystal and Si
1 +, c1! The third compound of the present invention formed with X mixed crystal
This is an example of a silicon substrate 11 with a plane orientation (1003).
On top, there is an r-rumanium crystal layer with a thickness of about 1 μm and an Si 1 + XG layer with a composition ratio X of 0.95 and a thickness of about 0.2 μm.
This is a semiconductor device formed by sequentially stacking a buffer layer 22 made of an aX mixed crystal layer and gallium amorphous crystal 13.

本実施例においても、緩衝層22の表面上に1μmから
10μmの範囲の厚さのガリウムひ、未結晶13を成長
させてみたが、前述した第1の実施例と同様に、割れや
剥がれ等の問題は生じなかった。
In this example as well, we tried to grow uncrystallized gallium 13 on the surface of the buffer layer 22 with a thickness ranging from 1 μm to 10 μm, but as in the first example described above, cracks, peeling, etc. No problems occurred.

なお、以上の実施例では緩衝層としてシリコンゲルマニ
ウム混晶を用いた場合についてのみ述べたが、格子定数
が組成比を変えることによって制御可能な他の半導体材
料、例えばガリウムひ素りん等の化合物混晶材料等を用
いても同様の効果が期待できることは言うまでもない。
Although the above embodiments have only described the case where a silicon germanium mixed crystal is used as the buffer layer, other semiconductor materials whose lattice constants can be controlled by changing the composition ratio, such as compound mixed crystals such as gallium arsenide phosphorus, etc. It goes without saying that similar effects can be expected by using other materials.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明による半導体装置では、異
種基板上に形成される半導体結晶に常に圧縮応力が加わ
るため、半導体結晶を厚く形成した場合でも割れや剥が
れ等の問題が回避でき、結晶性の優れたものが得られる
という大きな特徴がある。
As explained above, in the semiconductor device according to the present invention, since compressive stress is always applied to the semiconductor crystal formed on a different substrate, problems such as cracking and peeling can be avoided even when the semiconductor crystal is formed thickly, and the crystallinity is It has the great feature of providing excellent results.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第2の実施例を示す半導体装置の断面
図、 第2図は本発明の第3の実施例を示す半導体装置の断面
図。 第3図は従来提案されている、シリコン基板上にゲルマ
ニウム緩衝層を介して形成されたガリウムひ素形太陽電
池の主要構成要素を示す断面図である。 11・・・シリコン基板、12.22・・・緩衝層、1
3・・・ガリウムひ素結晶。 出願人代理人 弁理士 鈴 江 武 彦第1v!J 第2図 第3図
FIG. 1 is a sectional view of a semiconductor device showing a second embodiment of the invention, and FIG. 2 is a sectional view of a semiconductor device showing a third embodiment of the invention. FIG. 3 is a sectional view showing the main components of a conventionally proposed gallium arsenide solar cell formed on a silicon substrate with a germanium buffer layer interposed therebetween. 11... Silicon substrate, 12.22... Buffer layer, 1
3...Gallium arsenide crystal. Applicant's agent Patent attorney Takehiko Suzue 1st v.! J Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)基板となる第1の半導体の表面上に、少なくとも
、緩衝層となる1層または複数層の半導体層で構成され
た第2の半導体と、前記第1の半導体とは異種の第3の
半導体とが、順次積層された構造の半導体装置において
、前記第3の半導体の緩衝層となる前記第2の半導体を
構成する半導体各層のうち、少なくとも前記第3の半導
体と接する前記第2の半導体を構成する半導体層を、そ
の格子定数が前記第3の半導体の格子定数よりも小なる
値を有する半導体材料で形成することを特徴とする半導
体装置。
(1) On the surface of the first semiconductor serving as a substrate, a second semiconductor composed of at least one or more semiconductor layers serving as a buffer layer, and a third semiconductor which is different from the first semiconductor. In a semiconductor device having a structure in which semiconductors are sequentially stacked, among the semiconductor layers constituting the second semiconductor, which serves as a buffer layer of the third semiconductor, at least the second semiconductor layer in contact with the third semiconductor A semiconductor device characterized in that a semiconductor layer constituting the semiconductor is formed of a semiconductor material whose lattice constant has a smaller value than the lattice constant of the third semiconductor.
(2)第1の半導体をシリコン結晶とし、第2の半導体
をシリコンゲルマニウム混晶層かあるいはシリコンゲル
マニウム混晶層とゲルマニウム結晶層とで構成し、第3
の半導体をガリウムひ素とするときに、前記第3の半導
体であるガリウムひ素と接する前記第2の半導体を構成
するシリコンゲルマニウム混晶の組成をSi_1_−_
xGe_xで表わしたときにxの値を0.98以下に定
めたことを特徴とする特許請求の範囲第1項記載の半導
体装置。
(2) The first semiconductor is a silicon crystal, the second semiconductor is composed of a silicon germanium mixed crystal layer or a silicon germanium mixed crystal layer and a germanium crystal layer, and the third semiconductor is composed of a silicon germanium mixed crystal layer or a silicon germanium mixed crystal layer and a germanium crystal layer.
When the semiconductor is gallium arsenide, the composition of the silicon germanium mixed crystal constituting the second semiconductor in contact with the third semiconductor gallium arsenide is Si_1_-_
2. The semiconductor device according to claim 1, wherein the value of x is set to 0.98 or less when expressed as xGe_x.
JP60137329A 1985-06-24 1985-06-24 Semiconductor device Pending JPS61294877A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60137329A JPS61294877A (en) 1985-06-24 1985-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60137329A JPS61294877A (en) 1985-06-24 1985-06-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61294877A true JPS61294877A (en) 1986-12-25

Family

ID=15196121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60137329A Pending JPS61294877A (en) 1985-06-24 1985-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61294877A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
JPH05129201A (en) * 1991-05-31 1993-05-25 Internatl Business Mach Corp <Ibm> Multilayer material and its preparation
US5548128A (en) * 1994-12-14 1996-08-20 The United States Of America As Represented By The Secretary Of The Air Force Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates
US5959308A (en) * 1988-07-25 1999-09-28 Texas Instruments Incorporated Epitaxial layer on a heterointerface
US6858502B2 (en) 1999-03-12 2005-02-22 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
JP2011014898A (en) * 2009-06-05 2011-01-20 Sumitomo Chemical Co Ltd Sensor, semiconductor substrate, and method of manufacturing the semiconductor substrate
JP2013030798A (en) * 2007-09-07 2013-02-07 Amberwave Systems Corp Multi-junction solar cells
JP2014063861A (en) * 2012-09-20 2014-04-10 Toshiba Corp Semiconductor device manufacturing method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959308A (en) * 1988-07-25 1999-09-28 Texas Instruments Incorporated Epitaxial layer on a heterointerface
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
JPH05129201A (en) * 1991-05-31 1993-05-25 Internatl Business Mach Corp <Ibm> Multilayer material and its preparation
US5548128A (en) * 1994-12-14 1996-08-20 The United States Of America As Represented By The Secretary Of The Air Force Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates
US6858502B2 (en) 1999-03-12 2005-02-22 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
JP2013030798A (en) * 2007-09-07 2013-02-07 Amberwave Systems Corp Multi-junction solar cells
JP2011014898A (en) * 2009-06-05 2011-01-20 Sumitomo Chemical Co Ltd Sensor, semiconductor substrate, and method of manufacturing the semiconductor substrate
KR20120036801A (en) * 2009-06-05 2012-04-18 스미또모 가가꾸 가부시키가이샤 Sensor, semiconductor substrate, and method for manufacturing semiconductor substrate
US8835906B2 (en) 2009-06-05 2014-09-16 National Institute Of Advanced Industrial Science And Technology Sensor, semiconductor wafer, and method of producing semiconductor wafer
JP2014063861A (en) * 2012-09-20 2014-04-10 Toshiba Corp Semiconductor device manufacturing method
US9287441B2 (en) 2012-09-20 2016-03-15 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device

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