JPS61292937A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the transmission characteristics of a signal by directly leading out an output wiring for an output circuit formed in a fundamental cell outside the cell from an active element by a metallic wiring having multilayer structure. CONSTITUTION:A first layer aluminum wiring 23 connects several drain region in a P channel MOS field-effect transistor M2 and an N channel MOS field- effect transistor M5 in common while being connected to a second layer aluminum wiring 24 through a through-hole section TH. The aluminum wiring 24 is lead out to both sides of a fundamental cell 1 while crossing power supply lines 21, 22, and output terminals outa, outb are formed to each of the aluminum wirings 24. The output terminals outa, outb are connected to inter-cell wirings wired in a wiring region 4 through the through-hole section TH. Accordingly, output wirings for an output circuit shaped into the fundamental cell 1 can be lead out even to the wiring regions 4 on both the upper side and lower side of the cell 1 through the aluminum wirings 24 having small resistance, thus improving the transmission characteristics, etc. of signals among cells.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit device technology and to technology that is particularly effective when applied to gate arrays, such as those formed by mixing bipolar elements and MO8 elements. The present invention relates to techniques that are effective for use in semiconductor integrated circuit devices.

[Background technology]

In recent years, as digital circuit systems using semiconductor integrated circuit devices have become larger in scale, demands for lower power consumption, faster speeds, and smaller size, as well as for diversification of their functions, have become stronger. Under these circumstances, gate arrays, so-called semi-custom ICs, have begun to attract attention.

A large number of basic cells are arranged and formed in this gate array.

In each basic cell, circuit elements necessary to construct a basic logic circuit, such as elements such as MO8 field effect transistors and resistors, are formed in advance in the form of a semiconductor base. By arranging a large number of these basic cells, it is possible to construct various circuits or systems according to customer orders relatively easily and at low cost simply by changing the wiring pattern.

Note that the technology related to this type of gate array is, for example,
It is described in "Toshiba Review (Volume 37, No. 7)" published by Toshiba Corporation, published in 1982, pages 607-610.

FIGS. 8(a), 8(b), and 8(c) show a basic cell 1 of a gate array studied by the present inventors prior to making the present invention.

The basic cell 1 shown in the figure includes p-channel type MO8 field effect transistors Ml, M2 and n-channel type MO8 field effect transistors.
8i field effect transistor M4. A basic logic circuit called a macro cell is constructed by connecting M5 as appropriate according to the customer's order. Furthermore, using these macrocells, large-scale digital circuit networks that are completely blind to specific functions are being constructed.

In FIG. 8, (a) shows a planar layout pattern of the basic cell 1. In FIG.载) shows an equivalent circuit of the output circuit portion formed within the basic cell l. (c) partially shows the arrangement state of cell 1.

First, in FIG. 2A, numeral 11 indicates a source/drain region formed by a p+ type scattered layer, and numeral 12 indicates a source/drain region formed by an n type diffused layer.

18a and 18b are wirings made of polycrystalline silicon,
By these polycrystalline silicon wirings 18a and 18b, MO
8 field effect transistors Ml, M2°M4. Each gate electrode and input wiring of M5 are formed. Reference numerals 21 and 22 are power supply lines, in which 21 is connected to the positive power supply VCC, and 22 is connected to the ground potential GND, which is the negative power supply. The pair of power supply lines 21 and 22 are formed of aluminum wiring. The pair of power supply lines 21.degree. and 22 are wired vertically through each basic cell 1, 1.degree., as shown in FIG. 2C. Also, the same figure (e)
, 4 indicates a wiring area for connecting cells 1 to 1. In FIG. The regions 4 are provided on both sides of the cell 1 (in the figure, on the upper and lower sides of the cell 1).

Here, in the illustrated example, as shown in FIG. 4B, a p-channel MO8 field effect transistor M2 and an n-channel MO8 field effect transistor M5 constitute a C-MOS type inverting output circuit.

As shown in the figure (a), the input terminals ina and inb are distributed to both sides of the cell 1 (upper and lower sides in the figure) by the polycrystalline silicon 18b passing under the power supply lines 21 and 22. It has been derived. Also, its output terminal o
utatoutb is also led out to both sides of the cell 1 by aluminum wiring 23, as shown in FIG. 2(a).

In this case, one output terminal outa is a p-channel M
It is led out in series with the source/drain region 11t of the O8 field effect transistor M2. Thereby, the wiring of the output circuit passes through the power supply line 21 and is led out to one output terminal outa on the upper side of the cell 1. The other output terminal outb is led out through the source/drain region 12 of the n-channel MO8 field effect transistor M5 in series. Thereby, the wiring of the output circuit passes through the ground line 22 and is also led out to the other output terminal outa on the upper side of the cell 1.

In this way, with the configuration in which the input terminals ina, i, nb and the output terminals outa, outb can be led out to the wiring area 4 on either the upper or lower side of the basic cell 1, the wiring between each cell is established. It can be done freely and rationally. Moreover, this makes it easy to automate the design of wiring patterns between cells. If the output wiring 23 from cell 1 can only be routed to the wiring area 4 on one side of cell 1, the wiring between the cells will be extremely complicated and difficult, and the wiring between adjacent cells will be extremely complicated and difficult. Problems arise, such as wiring having to be routed in large detours.

However, in the above-described configuration, since the source/drain region 11 or 12 is interposed between the output circuit and its output terminal outa9 or outb, as shown in FIG. 1
The diffusion layer resistance due to 2 is interposed in series between the output circuit and the output terminal outa or outb as a series parasitic resistance r. And 1. The inventors have found that this series parasitic resistance r causes problems such as an increase in the parasitic time constant that degrades the signal transfer characteristics between cells.

Further, FIGS. 9(a), 9(b), and 9(c) show another example of the configuration of the basic cell 1 in the gate array studied by the present inventors.

In FIG. 9, (a) shows a planar layout pattern of the basic cell 1. In FIG.载) indicates a circuit of the output circuit portion formed within the basic cell 1. (c) partially shows the arrangement state of cell 1.

The configuration shown in FIG. 9 is basically the same as that shown in FIG. 8. To explain only the differences, here:
C-MOS field effect transistor M2. Output terminals Out & eoutb of the inverting output circuit formed by M5 are led out by polycrystalline silicon wiring 18d. In this configuration, no source/drain region is interposed between the output circuit and the output terminal outapoutb. Therefore, there is no diffusion layer resistance in the source/drain regions.

However, in this configuration, the polycrystalline silicon wiring 18
The specific resistance d becomes a parasitic resistance r, which is interposed in series between the output circuit and the output terminal outsideoutb. The inventor has clarified that this causes the same problem as shown in FIG. 8 in this case as well.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device in which a gate array is formed, in which interconnections are provided in series with wiring from an output circuit formed within a cell without impairing the freedom and rationality of wiring between cells. The object of the present invention is to provide a technology that can reduce parasitic resistance and thereby improve signal transfer characteristics between cells.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of all typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device in which a gate array is formed, the output wiring of the output circuit formed in the basic cell is directly drawn out from the active element to the outside of the cell using a multilayer metal wiring structure. Therefore, it is possible to reduce the parasitic resistance interposed in series with the output wiring without sacrificing the degree of freedom and rationality of wiring between cells, thereby improving the signal transmission characteristics between cells. It is intended to achieve the purpose of

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIGS. 1(a), 1(b), and 1(c) show a portion of a basic cell of a gate array to which the technique according to the present invention is applied.

The basic cell 1 shown in the figure is basically the same as that shown in FIG. 8 or 9. That is, basic cell 1
The p-channel MO8 field effect transistor Ml
, M2 and n-channel MO8 field effect transistor M4. A basic logic circuit called a macro cell is constructed by connecting M5 as appropriate according to the customer's order. Furthermore, large-scale digital circuit networks with specific functions are now constructed using these macrocells.

In FIG. 1, (a) shows a planar layout pattern of the basic cell 1. In FIG. (b) shows several circuits of the output circuit portion formed in the basic cell 1. (C) partially shows the arrangement state of cell 1.

In the same figure (a), 11 is a source/drain region made of a p+ type scattered layer, and 12 is a source/drain region made of an n+ type scattered layer.
The drain regions are shown respectively. 18a.

18b is a wiring made of polycrystalline silicon, and these polycrystalline silicon wirings 18a, 18b connect MO8 field effect transistors M1, M2 . M4 to M5 gate electrodes and input wirings are formed.

21 and 22 are power supply lines, and 21 is the positive power supply V
CC and 22 are connected to the ground potential GND, which is a negative power supply. The pair of power supply lines 21 and 22 are formed of aluminum wiring. The pair of power supply lines 21 and 22 are connected to each basic cell 1, 1 . ...Wires run vertically through the inside. In FIG. 4(e), reference numeral 4 indicates a wiring area for making an open connection between cells 1 and 1. The regions 4 are provided on both sides of the cell 1 (in the figure, on the upper and lower sides of the cell 1).

In the illustrated example, the p-channel MO8 field effect transistor M2 and the n-channel MO8 field effect transistor
The field effect transistor M5 constitutes a C-MOS type inverting output circuit. Its input terminal ina+ inb
As shown in FIG. 5A, the polycrystalline silicon 18b passes completely below the power supply lines 21 and 22 and is distributed to both sides of the cell 1 (upper and lower sides in the figure). Along with this, the output terminal out of the inverting output circuit
As shown in FIG. 2C, a*outb is also led out to the wiring region 4 on either the upper side or the lower side of the cell 1.

Here, the output terminal Outa of the inverting output circuit.

The output wiring leading outb to the outside of cell 1 is a multilayer metal wiring, specifically, a two-layer aluminum wiring (
23, 24).

In FIGS. 1(a) and 1(b), 23 indicates the first layer of aluminum wiring, and 24 indicates the second layer of aluminum wiring. In addition, TH is a through hole part, and jg
The first layer of aluminum wiring and the second layer of aluminum wiring are connected in the vertical direction.

The first layer aluminum wiring 23 is a p-channel MO8
The drain regions of the field effect transistor M2 and the n-channel MO8 field effect transistor M5 are interconnected, and the through-hole portion THfj! : Connected to the second-layer aluminum wiring 24 through. The second-layer aluminum wiring 24 extends across the power supply lines 21 and 22'i to both sides of the basic cell 1 (upper and lower sides in the figure). Output terminals 0uta+outbf are formed at the ends of the aluminum wiring 24 led out of the cell 1, respectively. This output terminal outapoutb is connected to the through hole section TH.
It is connected to the inter-cell wiring wired in the wiring area 4 via the wiring area 4. In this case, for the inter-cell wiring, a first layer of aluminum wiring is used in the longitudinal direction across the wiring region 4, and a second layer of aluminum wiring is used in the width direction across the wiring region 4. Further, each of the power supply lines 21 and 22 is formed of a first layer of aluminum wiring.

With the above configuration, the output wiring of the output circuit formed in the basic cell 1 does not pass through high resistance parts such as diffusion layers or polycrystalline silicon wiring, and has a significantly lower resistance than these. Via the aluminum wiring 24't-
It becomes possible to lead out to the wiring region 4 on either the upper side or the lower side of the cell 1.

As a result, it is possible to increase the degree of freedom and rationality of wiring between cells, and also to reduce the parasitic resistance (r) that is interposed in series with the wiring from the output circuit formed within the cell. This makes it possible to improve signal transmission characteristics between cells.

FIGS. 2(a), 2(b), and 2(c) show the main parts of another embodiment of the present invention.

To explain the difference from the embodiment described above, in the embodiment shown in the figure, each basic cell 1 includes C-MO8t field effect transistors Ml-M4. M2-M5. Along with M3-M6, a pair of npn bipolar transistors Ql,
Q2 are each formed in the form of a semiconductor base. In this case, C-MOSt field effect transistors Ml-M4.
M2-M5 and M3-M6 are used to completely configure the front stage side of the logic circuit and the parts that perform the logic function.

The bipolar transistors Ql and Q2 are used to form the output stage of the logic circuit. As in the case of the embodiment described above, the output wiring of this output stage is connected to the basic cell 1 by straddling the power supply lines 21 and 22 by the aluminum wiring 24 in the second layer and the power lines 21 and 22 by the aluminum wiring in the first layer. It is designed to be derived on either the upper or lower side of .

In FIG. 2, (a) shows a planar layout pattern of the basic cell 1. In FIG.载) indicates a circuit of the output circuit portion formed within the basic cell 1. (c) is (
The cross-sectional state of the CC portion of a) is shown.

In FIGS. 2(a), 2(b), and 2(c), a pair of bipolar transistors Ql and Q2 are connected in series in a totem pole configuration to form a complementary (pushinable) output circuit. C represents an n+ type collector region, B represents a p type base region, and E represents an n+ type emitter region. 18a,
18b and 18e are C-MOS field effect transistors Ml-M4. M2-M5. M3-M
6 common gate electrodes and gate input wirings are configured. Further, in (C), 30 represents an n-type silicon semiconductor substrate, 31 represents a surface oxide film, and 32 represents an insulating film between the eyebrows.

Next, the overall structure of the gate array in which the basic cells 1 shown in FIGS. 2(a), 2(b), and 2(c) are formed will be shown.

FIG. 3 shows an outline of a gate array to which the technology according to the present invention is applied.

As shown in the figure, the semiconductor integrated circuit device ICE including a gate array includes an internal circuit section 200, an input buffer section 110, and an output buffer section 120. Input buffer section 110 and output buffer section 12
0 are interposed between the internal circuit section 100 and the external connection terminal pad 3 and operate as a buffer with level conversion.

In FIG. 3, vtth is the input threshold, and ViH is H
(high level), ViL is the input logic level when L (low level), VoH is the output logic level when H (high level), and VoL is the output logic level when L (low level). show.

1+, inl~ink are logic inputs to the outside, out
l to outm respectively indicate logic outputs to the outside.

FIG. 4 shows an outline of the circuit state within the semiconductor device IC described above.

In the figure, an internal circuit section 200 includes a large number of logic function units (macro cells) 201 according to customer orders.
~20n and interconnections (dotted lines) connecting these to each other are formed. Along with this, the input buffer section 110
A large number of input buffer circuits 111 are formed in the input buffer section 120, and a large number of output buffer circuits 121 are formed in the output buffer section 120, respectively, as required.

FIG. 5 shows an outline of the layout configuration of the above-mentioned semiconductor integrated circuit device IC.

In the figure, 1 indicates a basic cell. In this basic cell 1, a semiconductor base is formed to form a part or all of a circuit element for forming a basic logic circuit, that is, a circuit element for forming a basic logic circuit. A large number of basic cells 1 with the same pattern are arranged. Reference numeral 4 indicates a wiring area for communicating between the basic cells 1.

By using one or more of these basic cells 1, the logic circuit units (macro cells) 201 to 201 shown in FIG.
20n is configured.

Further, 2 indicates an I10 buffer section. This buffer section 2
Either the input buffer circuit 111 or the output buffer circuit 121 is selected and formed. A large number of buffer sections 2 are arranged around the internal circuit section 200.

3 indicates a terminal pad for external connection. This terminal pad 3
A large number of terminals are arranged outside the buffer section 2, and are used as input terminals or output terminals depending on the type of circuit formed in the buffer section 2 at the corresponding position.

Furthermore, in addition to the terminal pad 3 used as an input terminal and an output terminal, terminal pads 3a and 3b used as a power supply terminal and a ground terminal are also provided.

6(a)(b>(e)) show the contents of the basic cell 1 described above.

The basic cell 1 shown in the figure is basically the same as the round cell shown in FIG. 2(a). That is, Fig. 6(a)(b)
Inside the basic cell 1 shown in (C), there are circuit elements for configuring a basic logic circuit, that is, a semiconductor base for forming part or all of the circuit elements for configuring the entire basic logic circuit. It is formed.

Here, as shown in the same figure (a), p-channel MO
8 field effect transistors Ml, M2. M3゜n-channel MO8 field effect transistor M4゜M5. M6. resistors R1, R2 and bipolar transistor Ql,
A semiconductor base forming part or all of Q2 is formed.

Figures 1 and 2) show the layout of the basic cell 1 on which the semiconductor base is formed. In the same figure (b), 11 is a p-channel MOSif: field effect transistor M1°M2.
p-type diffusion layer forming the source/drain region of M3, 12
is an n-channel MO8 field effect transistor M4. M5
．． Each of the n+ type scattering layers forming the source/drain regions of M6 is shown. Further, 13 is an n-type epitaxial layer portion where npn type bipolar transistors Ql and Q2 are formed, 14 is a diffusion layer for collector C electrode current collection, 15 is a base B diffusion layer, and 16 is an emitter E diffusion layer. show. Furthermore, 17 is p for forming resistors R1, R2t-
The type diffusion layer is shown. And 18a, 18b.

18c are the gate electrodes of M1 to M6 of the MO8 field effect transistor and the cell terminal parts in1a, in1
b.

1n2a, 1n2b, 1n3a, 1n3b The polycrystalline silicon electrode portions that also serve as f are shown. In this case, 1nla.

1nlb, 1n2a, and 1n2b are each drawn out to the outside of the basic cell 1, but 1n3a and 1n3b are placed inside the basic cell 1 as hidden terminals. The hidden terminal portions 1n3a and 1n3b are used for wiring between adjacent basic cells 1, etc.

FIG. 2C shows the above-mentioned basic cell 1 as a block.

FIG. 7 shows an example of a circuit constituted by the basic cell 1 described above.

FIG. 3(a) shows an example of the configuration of the circuit of the logic symbols shown in FIGS. In this case, the circuit consists of MO8 field effect transistors M whose preceding stages are complementary connected.
1-M6, while its output stage is composed of bipolar transistors Q1 and Q2. This achieves both low power consumption and high speed due to high driving force. The output terminal section OUT can be taken out from either side of the basic cell 1, as described above.

〔effect〕

(1) In a semiconductor integrated circuit device in which a gate array is formed, the output wiring of the output circuit formed in the basic cell is directly drawn out from the active element to the outside of the cell using a multilayer metal wiring structure. This makes it possible to reduce the parasitic resistance that is interposed in series with the output wiring without impairing the flexibility and rationality of wiring between cells, thereby improving the signal transmission characteristics between cells. The effect is that you will be able to do it.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the aluminum wiring 24 may be a metal wiring other than aluminum, such as aluminum/Gesten.

[Application field]

The above description has been made of the case where the invention made by the present inventor is applied to the technology of gate arrays, which is the background field of application, but the invention is not limited to this, for example, technology of semiconductor devices including analog circuits, etc. It can also be applied to

[Brief explanation of drawings]

Figures 1 (a), (b) and (c) are diagrams showing an embodiment of the basic cell section which is the main part of this invention, and Figure 2 (a), (b) and (c) are diagrams showing the main part of this invention. FIG. 3 is a block diagram showing an outline of a gate array to which this invention is applied; FIG. 4 shows the internal state of a gate array to which this invention is applied. 5 is a diagram showing the layout state of a gate array to which the present invention is applied; FIGS. 6(a), (b), and (C) are diagrams showing the configuration of its basic cell portion; FIG. a) and (b) are diagrams showing an example of a circuit configured using basic cells, and Fig. 8 (a), (b), and (c) are configurations of basic cell portions of gate arrays studied prior to this invention. Illustration showing an example, No. 9
Figures (a), (b), and (c) are diagrams showing other configuration examples of the basic cell portion of the gate array that were studied prior to the present invention. IC...semiconductor device in which a gate array is formed, 1.
...Basic cell, 2...I10 buffer section, 2b...
Area where the output buffer circuit is configured, 4... Wiring area, Ql, Q2... Bipolar transistor as an active element that constitutes the entire output circuit in the basic cell 1, M1~
M6... MO8 field effect transistor formed in the basic cell 1, 18&~18e... Gate electrode and wiring made of polycrystalline silicon, 21.22... Power supply line (first layer aluminum wiring), 24 ...Second layer aluminum wiring, TH...Through hole part. Figure 1 Figure 2 (C) Figure 6 Figure 7 (Ku) (wa Figure 8 (of) (Illusion, HA)

Claims (1)

[Claims] 1. A large number of basic cells are arranged in rows and columns, and
A pair of active elements for configuring complementary output circuits are formed in each basic cell, and a pair of power supply lines for supplying operating power to the circuits formed in each basic cell are formed. A semiconductor integrated circuit device in which wiring runs vertically through each basic cell, and the output wiring from the output circuit constituted by the pair of active elements is formed in a separate layer from the pair of power supply lines. 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is formed of a metal wiring formed by metal wiring, and the output wiring is led out to the outside of the basic cell by straddling at least one of the pair of power supply lines. 2. The semiconductor integrated circuit device according to claim 1, wherein the pair of active elements are C-MOS field effect transistors having gate electrodes made of polycrystalline silicon. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the pair of active elements are a pair of bipolar transistors connected in series in a totem pole type. 4. Claim 1, characterized in that in each of the basic cells, a bipolar transistor for configuring an output circuit section is formed in the form of a semiconductor base together with a C-MOS field effect transistor. 3. The semiconductor integrated circuit device according to any one of Items 1 to 3. 5. The semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the metal wiring is an aluminum wiring. 6. Claim 1, characterized in that aluminum wiring formed in a first layer is used as the pair of power supply lines, and aluminum wiring formed in a second layer is used as the output wiring. 6. The semiconductor integrated circuit device according to any one of .