JPS63152144A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive to improve the freedom in the design of wirings by a method wherein third wirings, which are extended from one end of a logical region to the other end, are provided between first wirings of lower layer and second wirings of upper layer, and the selected first and second wirings are connected to each other by the third wirings. CONSTITUTION:Power wirings 8 consisting of a fourth layer of Al film are extended in such a way as to cross a logical region from its one end to the other end. Moreover, power wirings 9 consisting of a third layer of Al film are provided for connecting the wirings 8 and second layer-power wirings. The wirings 9 are extended in a direction to intersect the wirings 8 and cross the logical region in such a way as to reach to the other end of the logical region from one end thereof. By providing the wirings 9, the design of the wirings 8 provided above the wirings 9, the design of a bump electrode 5B, which is connected to the wirings 8 and is used as an external electrode, and the design of power wirings 12A and 13A provided below the wirings 9 can be performed separately. Moreover, the design of the wirings 8 and the electrode 5B can be performed separately from the layout or constitution of fundamental cell rows and fundamental cells. Hereby, the freedom in the design of the wirings can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly effective when applied to semiconductor integrated circuit devices configuring various logics.

[Conventional technology]

An example of a semiconductor integrated circuit device that can configure various logic circuits is a gate array. The individual elementary cells of the gate array consist of one, for example, a bipolar transistor and a resistive element.

A predetermined potential, for example Vcc (OV), is supplied to each basic cell. This predetermined potential is supplied by, for example, a first wiring made of a first layer of aluminum film extending in the vertical direction, and a second wiring made of a second layer of aluminum film extending in the horizontal direction.

In addition, P-channel MISFET and N-channel MISFE
The technology related to gate arrays that configure various logics with T is described in "Nikkei Micro Device J, September 1986 issue, pages 65 to 79, published by Nikkei McGraw-Hill.

[Problem that the invention seeks to solve]

As a result of studying the above technology, the inventor found the following problem.

The wiring patterns of the first wiring and the second wiring must be changed every time the arrangement of the basic cells or the configuration of the logic circuit is changed.

An object of the present invention is to increase the degree of freedom in wiring design.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a third wiring extending from one end of the logic area to the other end is provided in an intermediate layer between the first wiring in the lower layer and the second wiring in the upper layer,
The selected first wiring and the selected second wiring are connected by the third wiring.

[Effect]

According to the above means, the wiring pattern of the first wiring and the wiring pattern of the second wiring
Since each wiring pattern can be individually designed, the degree of freedom in wiring design can be increased.

The present invention will be explained below along with examples.

〔Example〕

FIG. 1 is a plan view of a semiconductor integrated circuit device in which various logic circuits are constructed using bipolar transistors.

In FIG. 1, it is a semiconductor substrate (chip) made of single-crystalline silicon, and a plurality of ■/○ cells 2 constituting an input/output circuit are arranged around the semiconductor substrate (chip). Each I10 cell 2 has, for example, a plurality of bipolar transistors and a plurality of resistance elements, and these bipolar transistors and resistance elements are connected by wiring made of, for example, an aluminum film to form an input buffer, an output buffer sofa, etc. 3
is a basic cell column, and each basic cell column 3 is made up of a plurality of basic cells 3A having a plurality of bipolar transistors and a plurality of resistance elements arranged in a column. A wiring region 4 is located between the basic cell rows 3 and 3.

In this wiring region 4, signal wirings or various power supply wirings made of the [th layer] aluminum film extend in the same direction as the direction in which the basic cell rows 3 extend, for example.

Examples of power supply wiring include wiring that supplies potential Vcc (OV), wiring that supplies potential vi:gL (-3V), wiring that supplies potential "1sL (4■), and potential ■1A (-
There are wirings for supplying power (2V), wirings for supplying potential VEM (5V), etc. The area inside the I10 cell 2, that is, the area where the basic cell column 3 is arranged, is the logic area. As will be described later, this logic area includes wiring made of the first layer of aluminum film, wiring made of the second layer of aluminum film, wiring made of the third layer of aluminum film, and wiring made of the fourth layer of aluminum film. Various logics are constructed using wiring consisting of.

Note that the fourth layer is only the power supply wiring. 5A and 5B are
This is a bump electrode as an external electrode of a semiconductor integrated circuit device. A plurality of bump electrodes 5A and 5B are arranged on the semiconductor substrate 1, and among them, for example, the outer three rows of bump electrodes 5A are for the ■/○ cells 2, and the inner (
The bump electrode 5B on the inner side of the arrow 1 is for a logic circuit configured in a logic area. The outer bump electrode 5A has a potential Vcc, a potential V5EL, a potential vEsL, and a potential VT.
Those for power supplies such as T and potential V6s, those for input signals, and those for output signals are arranged. Each bump electrode 5A is connected to a predetermined 110 cells 2. The inner bump electrode 5B has a potential ■cc, a potential VEli:L, a potential VE, a potential V, .

There is only one for power supply such as potential VEM, and there is no one for signal. Each bump electrode 5B is connected to a predetermined basic cell 3A.

Next, an example of the layout of the wiring made of the fourth layer of aluminum film and the wiring made of the third layer of aluminum film will be described.

FIG. 2 is a plan view of the semiconductor chip (substrate 1) showing wiring made of the fourth and third layers of aluminum film. In FIG. 2, the logical area is shown surrounded by a dashed line. The area outside the dashed line is the peripheral area where the l/○ cell 2 is provided.

In FIG. 2, 7 is a wiring area above the I10 cell 2. In FIG. Wirings 6A and 6B are made of a fourth layer of aluminum film and extend in the wiring region 7. The wiring 6A is a wiring that supplies, for example, a potential Vcc (OV), and the wiring 6B is a wiring that supplies, for example, a potential VEEL (-3V). In FIG. 2, the wirings 6A and 6B are shown to surround the semiconductor chip 1 continuously without being cut off, but they can be modified in various ways, for example, they may be provided separately on each of the four sides. good. On the other hand, although not shown, the wiring 5 wires 6A, 6
For example, a potential VE L (
4V), potential VTT (2V), potential VIEM
A wiring made of a fourth layer of aluminum film is provided for supplying power (5V). Further, a signal wiring made of a fourth layer of aluminum film is provided on the sides of the wirings 6A and 6B or between them. The wiring area 7 includes power supply wiring and signal wiring made of a third layer of aluminum film, power supply wiring and signal wiring made of a second layer of aluminum film, and power supply wiring and signal wiring made of a first layer of aluminum film. Wiring is provided. The bump electrode 5A shown in FIG. 1 is connected to a predetermined I10 cell 2 through these 4Nth to first layer power supply wirings or signal wirings.

Reference numeral 8 denotes a power supply wiring made of a fourth layer of aluminum film, which extends across the logic area from one end to the other. It does not reach the peripheral wiring area 7. Power wiring 8
For example, the potential Vcc (0■), the potential VE:EL (
3V), potential V+=L (-4V), potential ■7A
(-2V), potential VEX (-5V), etc. In the logic area, the fourth layer has only power supply wiring 8 and no signal wiring. The bump electrode 5B shown in FIG. 1 is connected to this power supply wiring a8.

Here, a method of connecting the bump electrode 5B and the wiring 8 is shown in FIG.

In FIG. 3, the bump electrodes are indicated by circles, and the alphabets in 60 without the reference numeral 5B are added to make it easier to distinguish between the bump electrodes. For example, bump A is Vcct, bump B is VEIEL, bump C is potential V[SL, bump D is VTT, bump E is V@H
+bump F is V c C2, and bump G is Vccs. Vcct, Vcc2°V c c 3 have the same potential, OV, but mean that the current capacities flowing through the wirings 8A, 8F, and 8G are different.

Each bump A-G is arranged in a regular manner. For example, in row 1, bumps A, B, and C are alternately arranged. As a result, the lengths from bumps A to A are approximately equal everywhere on the wiring 8A, for example, and the potential drop due to the resistance of the wiring 8A can be made equal. Furthermore, migration of the wiring 8A can be reduced. Other clever, column m, column ■
The same applies to Further, bump rows I and N have a similar structure in which bumps A, B, and C are arranged in sequence.

In other words, the hump rows l are arranged by repeating every second bump row. Further, the bump rows (2) are arranged, for example, every third row, and the bump rows (2) are arranged, for example, every four rows. That is, each of the bump rows 1 to 2 are arranged repeatedly in a regular manner.

As a result, the current density of the current supplied by, for example, bump A can be made approximately equal on the logic region.

In FIG. 2, reference numeral 9 denotes a power supply wiring made of a third layer of aluminum film, and is for connecting the wiring 8 and the second layer of power supply wiring. The wiring 9 extends in the Y direction, where the direction crossing the wiring 8, that is, the direction in which the wiring 8 extends is defined as the X direction. Further, it traverses the logical area so as to reach from one end of the logical area to the other end. Placement 9 is.

Irrespective of the layout of the wiring 8, it is designed. Further, the design is made without regard to the second layer power wiring and signal wiring, the first layer power wiring and signal wiring, the layout of the basic cell row 3, and the configuration and size of the basic cell 3. That is, the wiring 9 is a fixed pattern. Therefore, which wiring 9 has potential Vcc and fi level Vg [
L, potential V: It is not determined which of L, potential VT, and potential VEM should be supplied with power. In other words, which wiring 9 is connected to which wiring 8 is not determined. Similarly, which wiring 9 should be connected to which power supply wiring 12A in the second layer?
(Fig. 4) is not specified. it is.

Determined when designing the logic circuit.

By providing the wiring 9, the power supply wiring 8 above and the bump electrode 5B connected thereto, and the power supply wiring 12 below.
The wiring design for A and 13A (see Figure 4) can be done separately. Further, the wiring 8 and the bump electrode 5B,
Basic cell row 3. The layout of the basic cell 3A or the configuration of the basic cell 3A can be done separately.

A plurality of wiring lines 9 are provided at predetermined intervals.

Between the wires 9 and 9 is a wiring region l where the signal wire 11 extends.
It is O. Signal man! ! Since the line 11 connects the signal lines in the second layer, it does not necessarily extend from one end of the logic area to the other, and most of the line 11 is shorter than the line 9.

The wirings 9 and 11 and the wiring 8 are insulated.

Next, the power supply wiring 12 made of the second layer of aluminum film is
A, signal wiring 12B, power supply wiring made of first layer aluminum film! ! An example of the layout of the signal wiring 13A and the signal wiring 13B will be described.

FIG. 4 is a plan view of a portion of the logical area.

Although not shown, the bipolar transistor and the resistance element in the basic cell 3A are connected by wiring made of the first layer of aluminium film, for example, to form a NAND gate and a NOR gate.
Six signal wirings 12B and 13B forming gates etc. connect the basic cells 3A to form a larger logic circuit. The power supply wiring 12A and the upper layer wiring 8 are connected by the wiring 9 shown in FIG.

A predetermined potential is supplied by connecting the power supply wirings 12A and 13A to the basic cell 3A.

Connections between the wirings 12A, 12B, 13A, and 13B or connections between these wirings 12A, 12B, 13A, and 13B and the basic cell 3A are indicated by *. Power wiring 12A
, the signal wiring 12B, the power supply wiring 13A, and the signal wiring 13B are not long enough to cross the logic area.

next! FIG. 5 shows a cross section of the connecting portion between the upper layer wiring 8 and the bump electrode 5B.

In FIG. 5, 14 is a first layer insulating film, which is made of, for example, a silicon oxide film formed by CVD. The insulating film 14 covers an electrode made of, for example, a polycrystalline silicon film connected to, for example, an emitter region of a bipolar transistor. Wirings 13A and 13B made of a first layer of aluminum film extend over this insulating film 14. 15
1 is a second layer insulating film, and is constructed by laminating a phosphosilicate glass (PSG) film on a silicon oxide film formed by CVD, for example. Wirings 12A and 12B made of a second layer of aluminum film extend on the insulating film 15 (fifth layer).
(The wiring 12A is not shown in the figure.) Reference numeral 16 denotes a third layer insulating film, which is constructed by forming, for example, a coated glass (SOG) film on a silicon oxide film formed by, for example, CVD, and further laminating, for example, a silicon oxide film formed by CVD on top of the coated glass (SOG) film. . Wires 9 and 11 made of a third layer of aluminum film extend over the insulating film 16 . Reference numeral 17 denotes a fourth layer insulating film, which has the same structure as the insulating film 16.

A wiring 8 made of a fourth layer of aluminum film is connected to the wiring 9 through a connection hole 1B formed by selectively removing the insulating film 17. Reference numeral 19 denotes a final protective film, which is constructed by laminating a silicon nitride film on a silicon oxide film formed by, for example, CVD. 20 is a connection hole formed by selectively removing the insulating film 19, and the bump electrode 5B is connected to a predetermined wiring 8 through this connection hole 20. 21 is a tungsten film, for example, as a base film, and is connected to the wiring 8. The bump electrode 5B is made of solder, for example. The hump electrode 5A shown in FIG. 1 also has a similar configuration.

As described above, according to this embodiment, the following effects can be obtained.

(+) A plurality of fixed pattern wirings 9 are provided between the upper layer wiring W8 and the lower layer wiring 12Δ, and the selected predetermined wiring 8
By connecting 12A and 12A with the wiring 9, the upper layer wiring 8
The layout and the layout of the wirings 12A and 13A can be performed separately without affecting each other.

Further, the wiring widths and wiring spacings of the wirings 8.12A and 13A can be selected without affecting each other. Note that the wiring width and wiring spacing of the wiring 9 can be selected without being influenced by the wirings 8, 12A and 13A.

Further, the lower layer wirings 12A, 13A or the basic cell 3A can be connected to a desired bump electrode 5B on the logic area.

Further, since the wirings 8 and 9 are not affected by the layout and configuration of the basic cell row 3 and the basic cells 3A, the time required for wiring design can be shortened.

(2) By arranging the bump electrodes 5B regularly on the wiring 8, the current density on the wiring 8 can be made almost uniform, so that migration of the wiring 8 can be reduced. Further, the potential drop in the wiring 8 can be reduced.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly described as follows.

In other words, the degree of freedom in wiring design can be increased.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an outline of a semiconductor chip. FIG. 2 is a plan view of the semiconductor chip showing upper layer wiring, and FIG. 3 is a diagram for explaining a method of connecting the bump electrode 5B and the wiring 8. Figure 4 shows the second layer wiring and the first layer wiring in the logic circuit area.
FIG. 5 is a plan view of the wiring layer and a cross-sectional view of the bump electrode. 1... Semiconductor substrate, 2... Peripheral circuit (Ilo), 3
... Basic cell, 3A... Basic cell, 4... Wiring channel, 5A, 5B... Bump electrode, 6A, 6B... Power supply wiring. 7, lO... wiring area, 8, 9.11.12A, 12
B, 13A, 13B... Wiring (aluminum film), 1
4.15.16.17.19...Insulating film, 18.20
... Connection hole, 21 - Underlying metal film. (′

Claims (1)

[Claims] 1. A plurality of basic cells constituting a logic circuit are provided in a logic area on a semiconductor substrate, and a predetermined potential is applied to these basic cells by a first wiring and a second wiring connected to the first wiring. A semiconductor integrated circuit device that supplies power to a semiconductor integrated circuit device, wherein a third wiring is provided between the first wiring and the second wiring, and extends from one end of the logic area to the other end, and a third wiring is provided between the selected first wiring and the selected first wiring. A semiconductor integrated circuit device, characterized in that the second wiring is connected to the third wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein a signal wiring in the same layer as the third wiring extends between the third wirings. 3. The semiconductor integrated circuit device according to claim 1, further comprising a plurality of bump electrodes on the second wiring. 4. The semiconductor integrated circuit device according to claim 1, wherein the basic cell comprises a bipolar transistor and a resistance element.