JPS61290871A - Image memory device - Google Patents

Image memory device

Info

Publication number
JPS61290871A
JPS61290871A JP60131765A JP13176585A JPS61290871A JP S61290871 A JPS61290871 A JP S61290871A JP 60131765 A JP60131765 A JP 60131765A JP 13176585 A JP13176585 A JP 13176585A JP S61290871 A JPS61290871 A JP S61290871A
Authority
JP
Japan
Prior art keywords
circuit
image signal
output
memory
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60131765A
Other languages
Japanese (ja)
Inventor
Koichi Tomatsuri
戸祭 孝一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60131765A priority Critical patent/JPS61290871A/en
Publication of JPS61290871A publication Critical patent/JPS61290871A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To store a picture in a memory when a picture whose picture recording is desired exists by constituting the titled device with an image signal inputting circuit, a memory for storing the output of the image signal inputting circuit, an image signal outputting circuit, and a switching circuit for switching the output of the image signal inputting circuit and the output of the memory and supplying them to the image signal outputting circuit. CONSTITUTION:An image signal supplied to an image signal input terminal 1 is A/D-converted by an A/D converter 2, stored in a memory 3, and also applied to a switching circuit 4. As for a synchronizing separator circuit 11, the same image signal as an input to the A/D converter 2 is applied, and horizontal/vertical synchronizing signals are outputted. A flip-flop 8 outputs synchronizing output 22 by making an input signal 21 synchronize with a vertical synchronizing signal 20 outputted from the synchronizing separator circuit 11, and the second flip-flop 9 receives the output of the flip-flop 8, and outputs a freeze signal 23 of one vertical period. The outputs of the flip-flops 8, 9 are provided to an OR circuit 14, and the OR circuit 14 outputs a switching signal to the switching circuit 4 and a synchronization switching circuit 13.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、画像信号を半導体を使ったディジタルメモリ
ーに記憶させるか・フロッピーナトのアナログメモリー
に記憶させる場合に好適な回路である。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention is a circuit suitable for storing image signals in a digital memory using a semiconductor or in a floppy analog memory.

〔発明の背景〕[Background of the invention]

本発明に近い例としては、オーディオ又はビデオの磁気
テープレコーダがある。これらは録画(又は録音)時に
は、録画(録音)しようとする信号をモニタ端子へ出力
するのが普通である。
A close example of the invention is an audio or video magnetic tape recorder. When recording (or recording), these devices usually output the signal to be recorded (recorded) to a monitor terminal.

しかし、本発明は画像信号を1画面記憶させる装置に関
するものであり、本質的忙異なるものである。
However, the present invention relates to an apparatus for storing image signals in one screen, and is essentially different from the conventional method.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、画像をモニタしていて、録画したい画
面があった時忙、その画面をメモリに記憶できる画像メ
モリ装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an image memory device that can store a screen to be recorded in a memory when the screen is monitored.

〔発明の概要〕[Summary of the invention]

本発明は、画像信号入力回路と、該画像信号入力回路の
出力を記憶するメモリと、画像信号出力回路と、該画像
信号入力回路の出力と該メモリの出力とを切換えて該画
像信号出力回路へ供給する切換回路から成ることを特徴
とするものである。
The present invention includes an image signal input circuit, a memory for storing an output of the image signal input circuit, an image signal output circuit, and an image signal output circuit that switches between the output of the image signal input circuit and the output of the memory. It is characterized in that it consists of a switching circuit that supplies the

〔発明の実施例〕[Embodiments of the invention]

第1図に本発明の一実施例を示し電図により説明する。 An embodiment of the present invention is shown in FIG. 1 and will be explained using an electrogram.

画像信号入力端子1に供給された画像信号は、νD変換
器21CよりA/D変換され、メモリ5Vc記憶される
と共に、切換回路4に与えられる。
The image signal supplied to the image signal input terminal 1 is A/D converted by the νD converter 21C, stored in the memory 5Vc, and provided to the switching circuit 4.

同期分離回路11は、A/D変換器2への入力と同じ画
像信号が与えられ、水平・垂直の同期信号を出力する。
The synchronization separation circuit 11 is given the same image signal as the input to the A/D converter 2, and outputs horizontal and vertical synchronization signals.

スイッチ7が閉じられるとフリツプフロツプ8の入力に
は第2図の2のような信号が加えられる。7リクプフロ
クプ8は同期分離回路11から出力される垂直同期信号
2oに、入力信号21を同期させ同期出力22を出方す
る。第2の7リツプフロクプ9は、フリツプフロツプ8
の出力を受けて、1垂直期間のフリーズ信号23を出力
する。
When switch 7 is closed, a signal such as 2 in FIG. 2 is applied to the input of flip-flop 8. The 7-reply filter 8 synchronizes the input signal 21 with the vertical synchronization signal 2o output from the synchronization separation circuit 11, and outputs a synchronization output 22. The second 7 flip-flop 9 is a flip-flop 8.
In response to the output of , it outputs a freeze signal 23 for one vertical period.

フリツプフロップ8,9の出力はOR回路14に加えら
れ、OR回路14は、切換信号24を切換回路4同期切
換回路13に出力する。第1図の切換回路4と同期切換
回路13の状態は、切換信号24力いHilの時を示し
ている。切換信号24が1Hi“のとき、切換回路4は
νD変換器2の出力をD/A変換器5へ出力し、D/A
変換器5は画像信号入力端子1に与えられた画像信号を
んΦ変換→D/A変換し、信号出力端子61C出力する
The outputs of the flip-flops 8 and 9 are applied to an OR circuit 14, and the OR circuit 14 outputs a switching signal 24 to the switching circuit 4 and the synchronous switching circuit 13. The states of the switching circuit 4 and the synchronous switching circuit 13 in FIG. 1 are shown when the switching signal 24 is at a high level. When the switching signal 24 is 1Hi", the switching circuit 4 outputs the output of the νD converter 2 to the D/A converter 5, and
The converter 5 performs Φ conversion → D/A conversion on the image signal applied to the image signal input terminal 1, and outputs the signal from the signal output terminal 61C.

切換信号24カいHilのとき゛、同期切換回路13は
同期分離回路11からの信号をメモリコントロール回路
10 K出力し、メモリコント田−ル10は画像信号入
力端子1に与えられる画像信号の同期信号に同期したn
ビットのメモリアドレスをメモリ3に出力する。
When the switching signal 24 is High, the synchronization switching circuit 13 outputs the signal from the synchronization separation circuit 11 to the memory control circuit 10K, and the memory control circuit 10 outputs the synchronization signal of the image signal applied to the image signal input terminal 1. n synchronized with
Output the memory address of the bit to memory 3.

スイッチ7を開くと、7リ一ズ信号23が7リツプフロ
クプ9から出力され、この間メモリコントロール回路1
0は、ライトイネーブル信号WEをメモリ3に出力する
When the switch 7 is opened, the 7 reset signal 23 is output from the 7 reset signal 23, and during this time the memory control circuit 1
0 outputs the write enable signal WE to the memory 3.

スイッチ7を開いて、切換信号24がゝLo’ JBz
ると、同期切換回路15は同期信号発生回路12からの
出力をメモリコントロール回路10に出力し、メモリコ
ントロール回路yOは同期信号発生回路12の同期出力
に同期したアドレス信号をメモリ3に出力する。この為
、スイッチ7が開いている時には画像信号入力端子1に
画像信号が与えられなくても、メモリ3から画像信号を
読み出すことができる。切換信号力いLO”のときは、
切換回路4もメモリ3の出力をD/A変換器5に出力す
る。
Open the switch 7 and the switching signal 24 will be "Lo' JBz
Then, the synchronization switching circuit 15 outputs the output from the synchronization signal generation circuit 12 to the memory control circuit 10, and the memory control circuit yO outputs an address signal synchronized with the synchronization output of the synchronization signal generation circuit 12 to the memory 3. Therefore, when the switch 7 is open, the image signal can be read from the memory 3 even if no image signal is applied to the image signal input terminal 1. When the switching signal is “LO”,
The switching circuit 4 also outputs the output of the memory 3 to the D/A converter 5.

第1図の例では切換回路4によりA/D変換器2の出力
とメモリ5の出方とを切換えるよう  4に構成したが
、切換回路4により画像入力信号端子1に加えられる画
像信号と、D/A変換器5の出力信号を切換えるよう忙
構成することも同様な効果を得られる。以上のようにア
ナログ部で切換えることができるからA/D変換器2、
D/A変換器3を使わずに、メモリ3をアナログのメモ
リで構成することふできる。アナログでフレキシブルデ
ィスクに記憶させる場合も全く同様である。
In the example of FIG. 1, the switching circuit 4 is configured to switch between the output of the A/D converter 2 and the output of the memory 5, but the image signal applied to the image input signal terminal 1 by the switching circuit 4, A similar effect can be obtained by configuring the D/A converter 5 to switch its output signal. As mentioned above, since switching can be done in the analog section, the A/D converter 2,
The memory 3 can be configured with an analog memory without using the D/A converter 3. The same is true when storing analog information on a flexible disk.

〔発明の効果〕〔Effect of the invention〕

本発明忙よれば、スイッチ7を開いていれば、メモリ3
に記憶された画像信号を出力端子6でモニタでき、新し
い画像をメモリに記憶させたい場合には、スイッチ7を
閉じることにより画像信号入力端子1に加えられた画像
信号を出方端子でモニタできる。入力信号をモニタしな
がら記憶させたい画面が入った時にスイ、チ、ヲ開けば
、その画面をメモリ3に記憶させることができる。
According to the present invention, if switch 7 is open, memory 3
The image signal stored in the image signal input terminal 1 can be monitored at the output terminal 6, and when a new image is to be stored in the memory, the image signal applied to the image signal input terminal 1 can be monitored at the output terminal by closing the switch 7. . While monitoring the input signal, when the screen you want to memorize appears, open the button, and the screen can be stored in the memory 3.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロツク図。 第2図はそのタイミングチャートである。 1・・・画像信号入力端子、2・・・A/D変換器、3
・・・メモリ、      4・・・切換回路、5・・
・D/A変換器、  6・・・出力端子、7・・・2イ
タチ、 8.9・・・フリツプフロツプ、 10・・・メモリコントロール回路、 11・・・同期分離回路、 12・・・同期信号発生回路、 13・・・同期切換回路、  20・・・垂直同期信号
、24・・・切換信号。
FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a timing chart thereof. 1... Image signal input terminal, 2... A/D converter, 3
...Memory, 4...Switching circuit, 5...
・D/A converter, 6...Output terminal, 7...2 Weasel, 8.9...Flip-flop, 10...Memory control circuit, 11...Synchronization separation circuit, 12...Synchronization Signal generation circuit, 13... Synchronization switching circuit, 20... Vertical synchronization signal, 24... Switching signal.

Claims (1)

【特許請求の範囲】[Claims] 1、画像信号入力回路と、該画像信号入力回路の出力を
記憶するメモリと、画像信号出力回路と、該画像信号入
力回路の出力と該メモリの出力とを切換えて該画像信号
出力回路へ供給する切換回路から成ることを特徴とする
画像メモリ装置。
1. An image signal input circuit, a memory that stores the output of the image signal input circuit, an image signal output circuit, and switches between the output of the image signal input circuit and the output of the memory and supplies the output to the image signal output circuit. An image memory device comprising a switching circuit.
JP60131765A 1985-06-19 1985-06-19 Image memory device Pending JPS61290871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60131765A JPS61290871A (en) 1985-06-19 1985-06-19 Image memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60131765A JPS61290871A (en) 1985-06-19 1985-06-19 Image memory device

Publications (1)

Publication Number Publication Date
JPS61290871A true JPS61290871A (en) 1986-12-20

Family

ID=15065643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60131765A Pending JPS61290871A (en) 1985-06-19 1985-06-19 Image memory device

Country Status (1)

Country Link
JP (1) JPS61290871A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248884A (en) * 1988-03-30 1989-10-04 Matsushita Electric Ind Co Ltd Television image receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248884A (en) * 1988-03-30 1989-10-04 Matsushita Electric Ind Co Ltd Television image receiver

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